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White Rabbit core collection
Commit c6d1206b authored by Maciej Lipinski's avatar Maciej Lipinski
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[btrain code review] added suffix _p1 to i/o interface of streamer's entities 

This is to follow the naming convention and easy coding, if you know that a
signal is a single-cycle pulse, you don't need to worry about edge detection
parent 10a9a1a3
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Showing with 58 additions and 58 deletions
modules/wr_streamers/rx_streamer.vhd
View file @ c6d1206b
......@@ -36,12 +36,12 @@ entity rx_streamer is
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
rx_first_o : out std_logic;
rx_last_o : out std_logic;
rx_first_p1_o : out std_logic;
rx_last_p1_o : out std_logic;
rx_data_o : out std_logic_vector(g_data_width-1 downto 0);
rx_valid_o : out std_logic;
rx_dreq_i : in std_logic;
rx_lost_o : out std_logic := '0';
rx_lost_p1_o : out std_logic := '0';
rx_latency_o : out std_logic_vector(27 downto 0);
rx_latency_valid_o : out std_logic;
......@@ -69,12 +69,12 @@ architecture wrapper of rx_streamer is
tm_time_valid_i : in std_logic := '0';
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
rx_first_o : out std_logic;
rx_last_o : out std_logic;
rx_first_p1_o : out std_logic;
rx_last_p1_o : out std_logic;
rx_data_o : out std_logic_vector(g_data_width-1 downto 0);
rx_valid_o : out std_logic;
rx_dreq_i : in std_logic;
rx_lost_o : out std_logic := '0';
rx_lost_p1_o : out std_logic := '0';
rx_latency_o : out std_logic_vector(27 downto 0);
rx_latency_valid_o : out std_logic;
cfg_mac_local_i : in std_logic_vector(47 downto 0);
......@@ -105,9 +105,9 @@ begin -- rtl
rx_data_o => rx_data_o,
rx_valid_o => rx_valid_o,
rx_dreq_i => rx_dreq_i,
rx_lost_o => rx_lost_o,
rx_first_o => rx_first_o,
rx_last_o => rx_last_o,
rx_lost_p1_o => rx_lost_p1_o,
rx_first_p1_o => rx_first_p1_o,
rx_last_p1_o => rx_last_p1_o,
rx_latency_valid_o => rx_latency_valid_o,
rx_latency_o => rx_latency_o,
cfg_mac_local_i => cfg_mac_local_i,
......
modules/wr_streamers/streamers_pkg.vhd
View file @ c6d1206b
......@@ -24,10 +24,10 @@ package streamers_pkg is
tx_data_i : in std_logic_vector(g_data_width-1 downto 0);
tx_valid_i : in std_logic;
tx_dreq_o : out std_logic;
tx_last_i : in std_logic := '1';
tx_flush_i : in std_logic := '0';
tx_last_p1_i : in std_logic := '1';
tx_flush_p1_i : in std_logic := '0';
tx_reset_seq_i : in std_logic := '0';
tx_frame_o : out std_logic;
tx_frame_p1_o : out std_logic;
cfg_mac_local_i : in std_logic_vector(47 downto 0) := x"000000000000";
cfg_mac_target_i : in std_logic_vector(47 downto 0);
cfg_ethertype_i : in std_logic_vector(15 downto 0) := x"dbff");
......@@ -49,18 +49,18 @@ package streamers_pkg is
tm_time_valid_i : in std_logic := '0';
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
rx_first_o : out std_logic;
rx_last_o : out std_logic;
rx_first_p1_o : out std_logic;
rx_last_p1_o : out std_logic;
rx_data_o : out std_logic_vector(g_data_width-1 downto 0);
rx_valid_o : out std_logic;
rx_dreq_i : in std_logic;
rx_lost_o : out std_logic := '0';
rx_lost_blocks_o : out std_logic := '0';
rx_lost_frames_o : out std_logic := '0';
rx_lost_p1_o : out std_logic := '0';
rx_lost_blocks_p1_o : out std_logic := '0';
rx_lost_frames_p1_o : out std_logic := '0';
rx_lost_frames_cnt_o : out std_logic_vector(14 downto 0);
rx_latency_o : out std_logic_vector(27 downto 0);
rx_latency_valid_o : out std_logic;
rx_frame_o : out std_logic;
rx_frame_p1_o : out std_logic;
cfg_mac_local_i : in std_logic_vector(47 downto 0) := x"000000000000";
cfg_mac_remote_i : in std_logic_vector(47 downto 0) := x"000000000000";
cfg_ethertype_i : in std_logic_vector(15 downto 0) := x"dbff";
......
modules/wr_streamers/tx_streamer.vhd
View file @ c6d1206b
......@@ -37,8 +37,8 @@ entity tx_streamer is
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
tx_flush_i : in std_logic := '0';
tx_last_i : in std_logic := '1';
tx_flush_p1_i : in std_logic := '0';
tx_last_p1_i : in std_logic := '1';
tx_data_i : in std_logic_vector(g_data_width-1 downto 0);
tx_reset_seq_i : in std_logic := '0';
tx_valid_i : in std_logic;
......@@ -70,12 +70,12 @@ begin -- rtl
rst_n_i => rst_n_i,
src_i => src_in,
src_o => src_out,
tx_last_i => tx_last_i,
tx_last_p1_i => tx_last_p1_i,
tx_data_i => tx_data_i,
tx_reset_seq_i => tx_reset_seq_i,
tx_valid_i => tx_valid_i,
tx_dreq_o => tx_dreq_o,
tx_flush_i => tx_flush_i,
tx_flush_p1_i => tx_flush_p1_i,
clk_ref_i => clk_ref_i,
tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_tai_i,
......
modules/wr_streamers/xrtx_streamers_stats.vhd
View file @ c6d1206b
......@@ -47,7 +47,7 @@ use work.wishbone_pkg.all; -- needed for t_wishbone_slave_in, etc
use work.streamers_pkg.all; -- needed for streamers
use work.wr_fabric_pkg.all; -- neede for :t_wrf_source_in, etc
use work.wrcore_pkg.all; -- needed for t_generic_word_array
use work.wr_transmission_wbgen2_pkg.all;
-- use work.wr_transmission_wbgen2_pkg.all;
entity xrtx_streamers_stats is
......
modules/wr_streamers/xrx_streamer.vhd
View file @ c6d1206b
......@@ -91,9 +91,9 @@ entity xrx_streamer is
---------------------------------------------------------------------------
-- 1 indicates the 1st word of the data block on rx_data_o.
rx_first_o : out std_logic;
rx_first_p1_o : out std_logic;
-- 1 indicates the last word of the data block on rx_data_o.
rx_last_o : out std_logic;
rx_last_p1_o : out std_logic;
-- Received data.
rx_data_o : out std_logic_vector(g_data_width-1 downto 0);
-- 1 indicted that rx_data_o is outputting a valid data word.
......@@ -103,11 +103,11 @@ entity xrx_streamer is
rx_dreq_i : in std_logic;
-- Lost output: 1 indicates that one or more frames or blocks have been lost
-- (left for backward compatibility).
rx_lost_o : out std_logic := '0';
rx_lost_p1_o : out std_logic := '0';
-- indicates that one or more blocks within frame are missing
rx_lost_blocks_o : out std_logic := '0';
rx_lost_blocks_p1_o : out std_logic := '0';
-- indicates that one or more frames are missing, the number of frames is provied
rx_lost_frames_o : out std_logic := '0';
rx_lost_frames_p1_o : out std_logic := '0';
--number of lost frames, the 0xF...F means that counter overflew
rx_lost_frames_cnt_o : out std_logic_vector(14 downto 0);
-- Latency measurement output: indicates the transport latency (between the
......@@ -116,7 +116,7 @@ entity xrx_streamer is
-- 1 when the latency on rx_latency_o is valid.
rx_latency_valid_o : out std_logic;
-- received streamer frame (counts all frames, corrupted and not)
rx_frame_o : out std_logic;
rx_frame_p1_o : out std_logic;
-- MAC address
cfg_mac_local_i : in std_logic_vector(47 downto 0);
......@@ -325,8 +325,8 @@ begin -- rtl
fifo_din(g_data_width-1 downto 0) <= fifo_data;
rx_data_o <= fifo_dout(g_data_width-1 downto 0);
rx_first_o <= fifo_dout(g_data_width+1);
rx_last_o <= fifo_dout(g_data_width);
rx_first_p1_o <= fifo_dout(g_data_width+1);
rx_last_p1_o <= fifo_dout(g_data_width);
U_RX_Timestamper : pulse_stamper
port map (
......@@ -360,7 +360,7 @@ begin -- rtl
ser_count <= (others => '0');
word_count <= (others => '0');
sync_seq_no <= '1';
rx_frame_o <= '0';
rx_frame_p1_o <= '0';
rx_lost_frames_cnt_o <= (others => '0');
frames_lost <= '0';
else
......@@ -380,7 +380,7 @@ begin -- rtl
word_count <= (others => '0');
rx_latency_valid_o <= '0';
tx_tag_valid <= '0';
rx_frame_o <= '0';
rx_frame_p1_o <= '0';
rx_lost_frames_cnt_o <= (others => '0');
frames_lost <= '0';
blocks_lost <= '0';
......@@ -439,13 +439,13 @@ begin -- rtl
crc_en <= '1';
detect_escapes <= '1';
state <= FRAME_SEQ_ID;
rx_frame_o <= '1';
rx_frame_p1_o <= '1';
when others => null;
end case;
end if;
when FRAME_SEQ_ID =>
rx_frame_o <= '0';
rx_frame_p1_o <= '0';
if(fsm_in.eof = '1') then
state <= IDLE;
elsif(fsm_in.dvalid = '1') then
......@@ -632,9 +632,9 @@ begin -- rtl
end process;
-- fifo_data <= pack_data;
rx_lost_o <= frames_lost or blocks_lost;
rx_lost_blocks_o <= blocks_lost;
rx_lost_frames_o <= frames_lost;
rx_lost_p1_o <= frames_lost or blocks_lost;
rx_lost_blocks_p1_o <= blocks_lost;
rx_lost_frames_p1_o <= frames_lost;
crc_restart <= '1' when (state = FRAME_SEQ_ID or (is_escape = '1' and fsm_in.data(15) = '1')) else not rst_n_i;
......
modules/wr_streamers/xtx_streamer.vhd
View file @ c6d1206b
......@@ -102,17 +102,17 @@ entity xtx_streamer is
-- Last signal. Can be used to indicate the last data word in a larger
-- block of samples (see documentation for more details).
tx_last_i : in std_logic := '1';
tx_last_p1_i : in std_logic := '1';
-- Flush input. When asserted, the streamer will immediatly send out all
-- the data that is stored in its TX buffer, ignoring g_tx_timeout.
tx_flush_i : in std_logic := '0';
tx_flush_p1_i : in std_logic := '0';
-- Reset sequence number. When asserted, the internal sequence number
-- generator used to detect loss of frames is reset to 0. Advanced feature.
tx_reset_seq_i : in std_logic := '0';
-- successfully sent streamer frame
tx_frame_o : out std_logic;
tx_frame_p1_o : out std_logic;
---------------------------------------------------------------------------
-- Configuration
---------------------------------------------------------------------------
......@@ -295,7 +295,7 @@ begin -- rtl
tx_fifo_we <= tx_valid_i and not tx_fifo_full;
tx_fifo_d <= tx_last_i & tx_data_i;
tx_fifo_d <= tx_last_p1_i & tx_data_i;
U_TX_Buffer : generic_sync_fifo
generic map (
......@@ -352,9 +352,9 @@ begin -- rtl
if rst_n_i = '0' then
buf_frame_count <= (others => '0');
else
if(tx_fifo_we = '1' and tx_last_i = '1' and (tx_fifo_rd = '0' or tx_fifo_last = '0')) then
if(tx_fifo_we = '1' and tx_last_p1_i = '1' and (tx_fifo_rd = '0' or tx_fifo_last = '0')) then
buf_frame_count <= buf_frame_count+ 1;
elsif((tx_fifo_we = '0' or tx_last_i = '0') and (tx_fifo_rd = '1' and tx_fifo_last = '1')) then
elsif((tx_fifo_we = '0' or tx_last_p1_i = '0') and (tx_fifo_rd = '1' and tx_fifo_last = '1')) then
buf_frame_count <= buf_frame_count - 1;
end if;
end if;
......@@ -402,7 +402,7 @@ begin -- rtl
tx_flush_latched <= '0';
else
if(state = IDLE) then
tx_flush_latched <= tx_flush_i or tx_timeout_hit;
tx_flush_latched <= tx_flush_p1_i or tx_timeout_hit;
else
tx_flush_latched <= '0';
end if;
......@@ -422,7 +422,7 @@ begin -- rtl
seq_no <= (others => '0');
word_count <= (others => '0');
crc_reset <= '1';
tx_frame_o <= '0';
tx_frame_p1_o <= '0';
else
if(tx_reset_seq_i = '1') then
seq_no <= (others => '0');
......@@ -430,12 +430,12 @@ begin -- rtl
case state is
when IDLE =>
crc_en <= '0';
crc_reset <= '0';
fsm_out.eof <= '0';
tx_frame_o <= '0';
crc_en <= '0';
crc_reset <= '0';
fsm_out.eof <= '0';
tx_frame_p1_o <= '0';
if(fsm_out.dreq = '1' and (tx_flush_latched = '1' or tx_flush_i = '1' or tx_threshold_hit = '1')) then
if(fsm_out.dreq = '1' and (tx_flush_latched = '1' or tx_flush_p1_i = '1' or tx_threshold_hit = '1')) then
state <= SOF;
fsm_out.sof <= '1';
end if;
......@@ -578,7 +578,7 @@ begin -- rtl
fsm_out.dvalid <= '0';
if(fsm_out.dreq = '1') then
fsm_out.eof <= '1';
tx_frame_o <= '1';
tx_frame_p1_o <= '1';
state <= IDLE;
end if;
end case;
......
testbench/wr_streamers/streamers-only_multiword-transfer/main.sv
View file @ c6d1206b
......@@ -189,7 +189,7 @@ module main;
.tx_data_i (tx_streamer_data),
.tx_valid_i (tx_streamer_dvalid),
.tx_dreq_o (tx_streamer_dreq),
.tx_last_i (tx_streamer_last),
.tx_last_p1_i (tx_streamer_last),
.cfg_mac_local_i (g_mac_tx),
.cfg_mac_target_i (g_mac_rx),
......@@ -223,8 +223,8 @@ module main;
.rx_data_o (rx_streamer_data),
.rx_valid_o (rx_streamer_dvalid),
.rx_dreq_i (rx_streamer_dreq),
.rx_first_o (rx_streamer_first),
.rx_last_o (rx_streamer_last),
.rx_first_p1_o (rx_streamer_first),
.rx_last_p1_o (rx_streamer_last),
.rx_latency_o (rx_latency),
.rx_latency_valid_o(rx_latency_valid),
......
testbench/wr_streamers/streamers-only_multiword-transfer/run.do
View file @ c6d1206b
make -f Makefile
make -f Makefile > /dev/null 2>&1
vsim -L unisim work.main -voptargs="+acc" -suppress 8684,8683
set NumericStdNoWarnings 1
......
top/spec_1_1/wr_streamers_demo/spec_top.vhd
View file @ c6d1206b
......@@ -514,7 +514,7 @@ begin
g_ep_rxbuf_size => 1024,
g_tx_runt_padding => true,
g_pcs_16bit => false,
g_dpram_initf => "wrc.ram",
g_dpram_initf => "wrc-simulation.ram",
-- g_aux_sdb => c_etherbone_sdb, --ML
g_dpram_size => 131072/4,
g_interface_mode => PIPELINED,
......@@ -724,7 +724,7 @@ begin
tx_dreq_o => tx_dreq,
-- every data word we send is the last one, as a single transfer in our
-- case contains only one 80-bit data word.
tx_last_i => '1',
tx_last_p1_i => '1',
-- send broadcast packets, so that many receivers can use triggers sent
-- by us.
......
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