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White Rabbit core collection
Commit ca0ea0a9 authored by Peter Jansweijer's avatar Peter Jansweijer Committed by Grzegorz Daniluk
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reorganized xilinx PHY files by family and Added Artix-7 Determininstic PHY sources 

(cherry picked from commit 5f934d98)
parent cc28eacd
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Showing with 2395 additions and 1323 deletions
platform/xilinx/wr_gtp_phy/Manifest.py
View file @ ca0ea0a9
files = ["gtp_bitslide.vhd",
"gtp_phase_align.vhd",
"gtp_phase_align_virtex6.vhd",
"gtx_reset.vhd",
"whiterabbitgtx_wrapper_gtx.vhd",
# "whiterabbitgtp_wrapper.vhd",
"whiterabbitgtp_wrapper_tile.vhd",
"whiterabbit_gtxe2_channel_wrapper_gt.vhd",
"wr_gtp_phy_spartan6.vhd",
"wr_gtx_phy_virtex6.vhd",
"wr_gtx_phy_kintex7.vhd"];
files = [
"gtp_bitslide.vhd",
];
if (syn_device[0:4].upper()=="XC6S"): # Spartan6
files.extend(["spartan6/wr_gtp_phy_spartan6.vhd",
"spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd",
"spartan6/gtp_phase_align.vhd"])
elif (syn_device[0:4].upper()=="XC6V"): # Virtex6
files.extend(["virtex6/wr_gtx_phy_virtex6.vhd",
"virtex6/whiterabbitgtx_wrapper_gtx.vhd",
"virtex6/gtp_phase_align_virtex6.vhd",
"virtex6/gtx_reset.vhd"])
elif (syn_device[0:4].upper()=="XC7A"): # Family 7 GTP (Artix7)
files.extend(["family7-gtp/wr_gtp_phy_artix7.vhd",
"family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd",
"family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd",
"family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd" ]);
elif (syn_device[0:4].upper()=="XC7K" or # Family 7 GTX (Kintex-7 and Virtex 585, 2000, X485)
syn_device[0:7].upper()=="XC7V585" or
syn_device[0:8].upper()=="XC7V2000" or
syn_device[0:8].upper()=="XC7VX485"):
files.extend(["family7-gtx/wr_gtx_phy_kintex7.vhd",
"family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd"]);
#elif (syn_device[0:4].upper()=="XC7V"): # Virtex7
# files.extend(["family7-gth/wr_gth_phy_virtex7.vhd" ]);
\ No newline at end of file
platform/xilinx/wr_gtp_phy/family7-gth/readme.txt 0 → 100644
View file @ ca0ea0a9
future GTH files are to be placed here
\ No newline at end of file
platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd 0 → 100644
View file @ ca0ea0a9
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 3.6
-- \ \ Application : 7 Series FPGAs Transceivers Wizard
-- / / Filename : whiterabbit_gtpe2_channel_wrapper.vhd
-- /___/ /\
-- \ \ / \
-- \___\/\___\
--
--
-- Module whiterabbit_gtpe2_channel_wrapper (a GT Wrapper)
-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
--
--
-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
entity whiterabbit_gtpe2_channel_wrapper is
generic
(
-- Simulation attributes
EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to "true" to speed up sim reset
);
port
(
--_________________________________________________________________________
--_________________________________________________________________________
--____________________________CHANNEL PORTS________________________________
GT0_DRP_BUSY_OUT : out std_logic;
---------------------------- Channel - DRP Ports --------------------------
GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
GT0_DRPCLK_IN : in std_logic;
GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
GT0_DRPEN_IN : in std_logic;
GT0_DRPRDY_OUT : out std_logic;
GT0_DRPWE_IN : in std_logic;
------------------------------- Loopback Ports -----------------------------
GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
--------------------- RX Initialization and Reset Ports --------------------
GT0_RXUSERRDY_IN : in std_logic;
-------------------------- RX Margin Analysis Ports ------------------------
GT0_EYESCANDATAERROR_OUT : out std_logic;
------------------ Receive Ports - FPGA RX Interface Ports -----------------
GT0_RXDATA_OUT : out std_logic_vector(15 downto 0);
GT0_RXUSRCLK_IN : in std_logic;
GT0_RXUSRCLK2_IN : in std_logic;
------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
GT0_RXCHARISCOMMA_OUT : out std_logic_vector(1 downto 0);
GT0_RXCHARISK_OUT : out std_logic_vector(1 downto 0);
GT0_RXDISPERR_OUT : out std_logic_vector(1 downto 0);
GT0_RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
------------------------ Receive Ports - RX AFE Ports ----------------------
GT0_GTPRXN_IN : in std_logic;
GT0_GTPRXP_IN : in std_logic;
-------------- Receive Ports - RX Byte and Word Alignment Ports ------------
GT0_RXBYTEISALIGNED_OUT : out std_logic;
GT0_RXCOMMADET_OUT : out std_logic;
GT0_RXSLIDE_IN : in std_logic;
--------------------- Receive Ports - RX Equilizer Ports -------------------
GT0_RXLPMHFHOLD_IN : in std_logic;
GT0_RXLPMLFHOLD_IN : in std_logic;
--------------- Receive Ports - RX Fabric Output Control Ports -------------
GT0_RXOUTCLK_OUT : out std_logic;
------------- Receive Ports - RX Initialization and Reset Ports ------------
GT0_GTRXRESET_IN : in std_logic;
-------------- Receive Ports -RX Initialization and Reset Ports ------------
GT0_RXRESETDONE_OUT : out std_logic;
--------------------- TX Initialization and Reset Ports --------------------
GT0_GTTXRESET_IN : in std_logic;
GT0_TXUSERRDY_IN : in std_logic;
------------------ Transmit Ports - FPGA TX Interface Ports ----------------
GT0_TXDATA_IN : in std_logic_vector(15 downto 0);
GT0_TXUSRCLK_IN : in std_logic;
GT0_TXUSRCLK2_IN : in std_logic;
------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
GT0_TXCHARISK_IN : in std_logic_vector(1 downto 0);
--------------- Transmit Ports - TX Configurable Driver Ports --------------
GT0_GTPTXN_OUT : out std_logic;
GT0_GTPTXP_OUT : out std_logic;
----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
GT0_TXOUTCLK_OUT : out std_logic;
GT0_TXOUTCLKFABRIC_OUT : out std_logic;
GT0_TXOUTCLKPCS_OUT : out std_logic;
------------- Transmit Ports - TX Initialization and Reset Ports -----------
GT0_TXRESETDONE_OUT : out std_logic;
------------------ Transmit Ports - pattern Generator Ports ----------------
GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
--____________________________COMMON PORTS________________________________
----------------- Common Block - GTPE2_COMMON Clocking Ports ---------------
GT0_GTREFCLK0_IN : in std_logic;
-------------------------- Common Block - PLL Ports ------------------------
GT0_PLL1LOCK_OUT : out std_logic;
GT0_PLL1LOCKDETCLK_IN : in std_logic;
GT0_PLL1REFCLKLOST_OUT : out std_logic;
GT0_PLL1RESET_IN : in std_logic
);
end whiterabbit_gtpe2_channel_wrapper;
architecture RTL of whiterabbit_gtpe2_channel_wrapper is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of RTL : architecture is "whiterabbit_gtpe2_channel_wrapper,gtwizard_v3_6_1,{protocol_file=Start_from_scratch}";
--***********************************Parameter Declarations********************
constant DLY : time := 1 ns;
--***************************** Signal Declarations *****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal gt0_pll0outclk_i : std_logic;
signal gt0_pll0outrefclk_i : std_logic;
signal gt0_pll1outclk_i : std_logic;
signal gt0_pll1outrefclk_i : std_logic;
signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0);
signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0);
signal gt0_pll0clk_i : std_logic;
signal gt0_pll0refclk_i : std_logic;
signal gt0_pll1clk_i : std_logic;
signal gt0_pll1refclk_i : std_logic;
signal gt0_rst_i : std_logic;
--*************************** Component Declarations **************************
component whiterabbit_gtpe2_channel_wrapper_gt
generic
(
-- Simulation attributes
GT_SIM_GTRESET_SPEEDUP : string := "false";
EXAMPLE_SIMULATION : integer := 0;
TXSYNC_OVRD_IN : bit := '0';
TXSYNC_MULTILANE_IN : bit := '0'
);
port
(
RST_IN : in std_logic;
DRP_BUSY_OUT : out std_logic;
---------------------------- Channel - DRP Ports --------------------------
DRPADDR_IN : in std_logic_vector(8 downto 0);
DRPCLK_IN : in std_logic;
DRPDI_IN : in std_logic_vector(15 downto 0);
DRPDO_OUT : out std_logic_vector(15 downto 0);
DRPEN_IN : in std_logic;
DRPRDY_OUT : out std_logic;
DRPWE_IN : in std_logic;
------------------------ GTPE2_CHANNEL Clocking Ports ----------------------
PLL0CLK_IN : in std_logic;
PLL0REFCLK_IN : in std_logic;
PLL1CLK_IN : in std_logic;
PLL1REFCLK_IN : in std_logic;
------------------------------- Loopback Ports -----------------------------
LOOPBACK_IN : in std_logic_vector(2 downto 0);
--------------------- RX Initialization and Reset Ports --------------------
RXUSERRDY_IN : in std_logic;
-------------------------- RX Margin Analysis Ports ------------------------
EYESCANDATAERROR_OUT : out std_logic;
------------------ Receive Ports - FPGA RX Interface Ports -----------------
RXDATA_OUT : out std_logic_vector(15 downto 0);
RXUSRCLK_IN : in std_logic;
RXUSRCLK2_IN : in std_logic;
------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
RXCHARISCOMMA_OUT : out std_logic_vector(1 downto 0);
RXCHARISK_OUT : out std_logic_vector(1 downto 0);
RXDISPERR_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
------------------------ Receive Ports - RX AFE Ports ----------------------
GTPRXN_IN : in std_logic;
GTPRXP_IN : in std_logic;
-------------- Receive Ports - RX Byte and Word Alignment Ports ------------
RXBYTEISALIGNED_OUT : out std_logic;
RXCOMMADET_OUT : out std_logic;
RXSLIDE_IN : in std_logic;
--------------------- Receive Ports - RX Equilizer Ports -------------------
RXLPMHFHOLD_IN : in std_logic;
RXLPMLFHOLD_IN : in std_logic;
--------------- Receive Ports - RX Fabric Output Control Ports -------------
RXOUTCLK_OUT : out std_logic;
------------- Receive Ports - RX Initialization and Reset Ports ------------
GTRXRESET_IN : in std_logic;
-------------- Receive Ports -RX Initialization and Reset Ports ------------
RXRESETDONE_OUT : out std_logic;
--------------------- TX Initialization and Reset Ports --------------------
GTTXRESET_IN : in std_logic;
TXUSERRDY_IN : in std_logic;
------------------ Transmit Ports - FPGA TX Interface Ports ----------------
TXDATA_IN : in std_logic_vector(15 downto 0);
TXUSRCLK_IN : in std_logic;
TXUSRCLK2_IN : in std_logic;
------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
TXCHARISK_IN : in std_logic_vector(1 downto 0);
--------------- Transmit Ports - TX Configurable Driver Ports --------------
GTPTXN_OUT : out std_logic;
GTPTXP_OUT : out std_logic;
----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
TXOUTCLK_OUT : out std_logic;
TXOUTCLKFABRIC_OUT : out std_logic;
TXOUTCLKPCS_OUT : out std_logic;
------------- Transmit Ports - TX Initialization and Reset Ports -----------
TXRESETDONE_OUT : out std_logic;
------------------ Transmit Ports - pattern Generator Ports ----------------
TXPRBSSEL_IN : in std_logic_vector(2 downto 0)
);
end component;
constant PLL0_FBDIV_IN : integer := 1;
constant PLL1_FBDIV_IN : integer := 4;
constant PLL0_FBDIV_45_IN : integer := 4;
constant PLL1_FBDIV_45_IN : integer := 5;
constant PLL0_REFCLK_DIV_IN : integer := 1;
constant PLL1_REFCLK_DIV_IN : integer := 1;
--********************************* Main Body of Code**************************
begin
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
gt0_pll0clk_i <= gt0_pll0outclk_i;
gt0_pll0refclk_i <= gt0_pll0outrefclk_i;
gt0_pll1clk_i <= gt0_pll1outclk_i;
gt0_pll1refclk_i <= gt0_pll1outrefclk_i;
gt0_rst_i <= GT0_PLL1RESET_IN;
--------------------------- GT Instances -------------------------------
--_________________________________________________________________________
--_________________________________________________________________________
GT_INST : whiterabbit_gtpe2_channel_wrapper_gt
generic map
(
-- Simulation attributes
GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
TXSYNC_OVRD_IN => ('0'),
TXSYNC_MULTILANE_IN => ('0')
)
port map
(
RST_IN => gt0_rst_i,
DRP_BUSY_OUT => GT0_DRP_BUSY_OUT,
---------------------------- Channel - DRP Ports --------------------------
DRPADDR_IN => GT0_DRPADDR_IN,
DRPCLK_IN => GT0_DRPCLK_IN,
DRPDI_IN => GT0_DRPDI_IN,
DRPDO_OUT => GT0_DRPDO_OUT,
DRPEN_IN => GT0_DRPEN_IN,
DRPRDY_OUT => GT0_DRPRDY_OUT,
DRPWE_IN => GT0_DRPWE_IN,
------------------------ GTPE2_CHANNEL Clocking Ports ----------------------
PLL0CLK_IN => gt0_pll0clk_i,
PLL0REFCLK_IN => gt0_pll0refclk_i,
PLL1CLK_IN => gt0_pll1clk_i,
PLL1REFCLK_IN => gt0_pll1refclk_i,
------------------------------- Loopback Ports -----------------------------
LOOPBACK_IN => GT0_LOOPBACK_IN,
--------------------- RX Initialization and Reset Ports --------------------
RXUSERRDY_IN => GT0_RXUSERRDY_IN,
-------------------------- RX Margin Analysis Ports ------------------------
EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
------------------ Receive Ports - FPGA RX Interface Ports -----------------
RXDATA_OUT => GT0_RXDATA_OUT,
RXUSRCLK_IN => GT0_RXUSRCLK_IN,
RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
RXCHARISCOMMA_OUT => GT0_RXCHARISCOMMA_OUT,
RXCHARISK_OUT => GT0_RXCHARISK_OUT,
RXDISPERR_OUT => GT0_RXDISPERR_OUT,
RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT,
------------------------ Receive Ports - RX AFE Ports ----------------------
GTPRXN_IN => GT0_GTPRXN_IN,
GTPRXP_IN => GT0_GTPRXP_IN,
-------------- Receive Ports - RX Byte and Word Alignment Ports ------------
RXBYTEISALIGNED_OUT => GT0_RXBYTEISALIGNED_OUT,
RXCOMMADET_OUT => GT0_RXCOMMADET_OUT,
RXSLIDE_IN => GT0_RXSLIDE_IN,
--------------------- Receive Ports - RX Equilizer Ports -------------------
RXLPMHFHOLD_IN => GT0_RXLPMHFHOLD_IN,
RXLPMLFHOLD_IN => GT0_RXLPMLFHOLD_IN,
--------------- Receive Ports - RX Fabric Output Control Ports -------------
RXOUTCLK_OUT => GT0_RXOUTCLK_OUT,
------------- Receive Ports - RX Initialization and Reset Ports ------------
GTRXRESET_IN => GT0_GTRXRESET_IN,
-------------- Receive Ports -RX Initialization and Reset Ports ------------
RXRESETDONE_OUT => GT0_RXRESETDONE_OUT,
--------------------- TX Initialization and Reset Ports --------------------
GTTXRESET_IN => GT0_GTTXRESET_IN,
TXUSERRDY_IN => GT0_TXUSERRDY_IN,
------------------ Transmit Ports - FPGA TX Interface Ports ----------------
TXDATA_IN => GT0_TXDATA_IN,
TXUSRCLK_IN => GT0_TXUSRCLK_IN,
TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
TXCHARISK_IN => GT0_TXCHARISK_IN,
--------------- Transmit Ports - TX Configurable Driver Ports --------------
GTPTXN_OUT => GT0_GTPTXN_OUT,
GTPTXP_OUT => GT0_GTPTXP_OUT,
----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT,
TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT,
------------- Transmit Ports - TX Initialization and Reset Ports -----------
TXRESETDONE_OUT => GT0_TXRESETDONE_OUT,
------------------ Transmit Ports - pattern Generator Ports ----------------
TXPRBSSEL_IN => GT0_TXPRBSSEL_IN
);
--_________________________________________________________________________
--_________________________________________________________________________
--_________________________GTPE2_COMMON____________________________________
gtpe2_common_0_i : GTPE2_COMMON
generic map
(
-- Simulation attributes
SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
SIM_PLL0REFCLK_SEL => ("001"),
SIM_PLL1REFCLK_SEL => ("001"),
SIM_VERSION => ("1.0"),
PLL0_FBDIV => PLL0_FBDIV_IN ,
PLL0_FBDIV_45 => PLL0_FBDIV_45_IN ,
PLL0_REFCLK_DIV => PLL0_REFCLK_DIV_IN,
PLL1_FBDIV => PLL1_FBDIV_IN ,
PLL1_FBDIV_45 => PLL1_FBDIV_45_IN ,
PLL1_REFCLK_DIV => PLL1_REFCLK_DIV_IN,
------------------COMMON BLOCK Attributes---------------
BIAS_CFG => (x"0000000000050001"),
COMMON_CFG => (x"00000000"),
----------------------------PLL Attributes----------------------------
PLL0_CFG => (x"01F03DC"),
PLL0_DMON_CFG => ('0'),
PLL0_INIT_CFG => (x"00001E"),
PLL0_LOCK_CFG => (x"1E8"),
PLL1_CFG => (x"01F03DC"),
PLL1_DMON_CFG => ('0'),
PLL1_INIT_CFG => (x"00001E"),
PLL1_LOCK_CFG => (x"1E8"),
PLL_CLKOUT_CFG => (x"00"),
----------------------------Reserved Attributes----------------------------
RSVD_ATTR0 => (x"0000"),
RSVD_ATTR1 => (x"0000")
)
port map
(
DMONITOROUT => open,
------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
DRPADDR => tied_to_ground_vec_i(7 downto 0),
DRPCLK => tied_to_ground_i,
DRPDI => tied_to_ground_vec_i(15 downto 0),
DRPDO => open,
DRPEN => tied_to_ground_i,
DRPRDY => open,
DRPWE => tied_to_ground_i,
----------------- Common Block - GTPE2_COMMON Clocking Ports ---------------
GTEASTREFCLK0 => tied_to_ground_i,
GTEASTREFCLK1 => tied_to_ground_i,
GTGREFCLK1 => tied_to_ground_i,
GTREFCLK0 => GT0_GTREFCLK0_IN,
GTREFCLK1 => tied_to_ground_i,
GTWESTREFCLK0 => tied_to_ground_i,
GTWESTREFCLK1 => tied_to_ground_i,
PLL0OUTCLK => gt0_pll0outclk_i,
PLL0OUTREFCLK => gt0_pll0outrefclk_i,
PLL1OUTCLK => gt0_pll1outclk_i,
PLL1OUTREFCLK => gt0_pll1outrefclk_i,
-------------------------- Common Block - PLL Ports ------------------------
PLL0FBCLKLOST => open,
PLL0LOCK => open,
PLL0LOCKDETCLK => tied_to_ground_i,
PLL0LOCKEN => tied_to_vcc_i,
PLL0PD => '1',
PLL0REFCLKLOST => open,
PLL0REFCLKSEL => "001",
PLL0RESET => tied_to_ground_i,
PLL1FBCLKLOST => open,
PLL1LOCK => GT0_PLL1LOCK_OUT,
PLL1LOCKDETCLK => GT0_PLL1LOCKDETCLK_IN,
PLL1LOCKEN => tied_to_vcc_i,
PLL1PD => tied_to_ground_i,
PLL1REFCLKLOST => GT0_PLL1REFCLKLOST_OUT,
PLL1REFCLKSEL => "001",
PLL1RESET => GT0_PLL1RESET_IN,
---------------------------- Common Block - Ports --------------------------
BGRCALOVRDENB => tied_to_vcc_i,
GTGREFCLK0 => tied_to_ground_i,
PLLRSVD1 => "0000000000000000",
PLLRSVD2 => "00000",
REFCLKOUTMONITOR0 => open,
REFCLKOUTMONITOR1 => open,
------------------------ Common Block - RX AFE Ports -----------------------
PMARSVDOUT => open,
--------------------------------- QPLL Ports -------------------------------
BGBYPASSB => tied_to_vcc_i,
BGMONITORENB => tied_to_vcc_i,
BGPDB => tied_to_vcc_i,
BGRCALOVRD => "00000", -- ug482 table 2-8 says "111111"
PMARSVD => "00000000",
RCALENB => tied_to_vcc_i
);
end RTL;
platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd 0 → 100644
View file @ ca0ea0a9
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 3.6
-- \ \ Application : 7 Series FPGAs Transceivers Wizard
-- / / Filename : whiterabbit_gtpe2_channel_wrapper_gt.vhd
-- /___/ /\
-- \ \ / \
-- \___\/\___\
--
--
-- Module whiterabbit_gtpe2_channel_wrapper_GT (a GT Wrapper)
-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
--
--
-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
entity whiterabbit_gtpe2_channel_wrapper_gt is
generic
(
-- Simulation attributes
GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
TXSYNC_OVRD_IN : bit := '0';
TXSYNC_MULTILANE_IN : bit := '0'
);
port
(
RST_IN : in std_logic; -- Connect to System Reset
DRP_BUSY_OUT : out std_logic; -- Indicates that the DRP bus is not accessible to the User
---------------------------- Channel - DRP Ports --------------------------
drpaddr_in : in std_logic_vector(8 downto 0);
drpclk_in : in std_logic;
drpdi_in : in std_logic_vector(15 downto 0);
drpdo_out : out std_logic_vector(15 downto 0);
drpen_in : in std_logic;
drprdy_out : out std_logic;
drpwe_in : in std_logic;
------------------------ GTPE2_CHANNEL Clocking Ports ----------------------
pll0clk_in : in std_logic;
pll0refclk_in : in std_logic;
pll1clk_in : in std_logic;
pll1refclk_in : in std_logic;
------------------------------- Loopback Ports -----------------------------
loopback_in : in std_logic_vector(2 downto 0);
--------------------- RX Initialization and Reset Ports --------------------
rxuserrdy_in : in std_logic;
-------------------------- RX Margin Analysis Ports ------------------------
eyescandataerror_out : out std_logic;
------------------ Receive Ports - FPGA RX Interface Ports -----------------
rxdata_out : out std_logic_vector(15 downto 0);
rxusrclk_in : in std_logic;
rxusrclk2_in : in std_logic;
------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
rxchariscomma_out : out std_logic_vector(1 downto 0);
rxcharisk_out : out std_logic_vector(1 downto 0);
rxdisperr_out : out std_logic_vector(1 downto 0);
rxnotintable_out : out std_logic_vector(1 downto 0);
------------------------ Receive Ports - RX AFE Ports ----------------------
gtprxn_in : in std_logic;
gtprxp_in : in std_logic;
-------------- Receive Ports - RX Byte and Word Alignment Ports ------------
rxbyteisaligned_out : out std_logic;
rxcommadet_out : out std_logic;
rxslide_in : in std_logic;
--------------------- Receive Ports - RX Equilizer Ports -------------------
rxlpmhfhold_in : in std_logic;
rxlpmlfhold_in : in std_logic;
--------------- Receive Ports - RX Fabric Output Control Ports -------------
rxoutclk_out : out std_logic;
------------- Receive Ports - RX Initialization and Reset Ports ------------
gtrxreset_in : in std_logic;
-------------- Receive Ports -RX Initialization and Reset Ports ------------
rxresetdone_out : out std_logic;
--------------------- TX Initialization and Reset Ports --------------------
gttxreset_in : in std_logic;
txuserrdy_in : in std_logic;
------------------ Transmit Ports - FPGA TX Interface Ports ----------------
txdata_in : in std_logic_vector(15 downto 0);
txusrclk_in : in std_logic;
txusrclk2_in : in std_logic;
------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
txcharisk_in : in std_logic_vector(1 downto 0);
--------------- Transmit Ports - TX Configurable Driver Ports --------------
gtptxn_out : out std_logic;
gtptxp_out : out std_logic;
----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
txoutclk_out : out std_logic;
txoutclkfabric_out : out std_logic;
txoutclkpcs_out : out std_logic;
------------- Transmit Ports - TX Initialization and Reset Ports -----------
txresetdone_out : out std_logic;
------------------ Transmit Ports - pattern Generator Ports ----------------
txprbssel_in : in std_logic_vector(2 downto 0)
);
end whiterabbit_gtpe2_channel_wrapper_gt;
architecture RTL of whiterabbit_gtpe2_channel_wrapper_gt is
--*************************** Component Declarations **************************
component whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq
port (
RST : IN std_logic;
GTRXRESET_IN : IN std_logic;
RXPMARESETDONE: IN std_logic;
GTRXRESET_OUT : OUT std_logic;
DRPCLK : IN std_logic;
DRPADDR : OUT std_logic_vector(8 downto 0);
DRPDO : IN std_logic_vector(15 downto 0);
DRPDI : OUT std_logic_vector(15 downto 0);
DRPRDY : IN std_logic;
DRPEN : OUT std_logic;
DRPWE : OUT std_logic;
DRP_OP_DONE : OUT std_logic
);
end component;
--component whiterabbitgtp_wrapper_rxpmarst_seq
-- port (
-- RST : IN std_logic;
-- RXPMARESET_IN : IN std_logic;
-- RXPMARESETDONE : IN std_logic;
-- RXPMARESET_OUT : OUT std_logic;
--
-- DRPCLK : IN std_logic;
-- DRPADDR : OUT std_logic_vector(8 downto 0);
-- DRPDO : IN std_logic_vector(15 downto 0);
-- DRPDI : OUT std_logic_vector(15 downto 0);
-- DRPRDY : IN std_logic;
-- DRPEN : OUT std_logic;
-- DRPWE : OUT std_logic;
-- DRP_BUSY_IN : IN std_logic;
-- DRP_PMA_BUSY_OUT : OUT std_logic
--);
--end component;
--
--
--component whiterabbitgtp_wrapper_rxrate_seq
-- port (
-- RST : IN std_logic;
-- RXRATE_IN : IN std_logic_vector(2 downto 0);
-- RXPMARESETDONE : IN std_logic;
-- RXRATE_OUT : OUT std_logic_vector(2 downto 0);
--
-- DRPCLK : IN std_logic;
-- DRPADDR : OUT std_logic_vector(8 downto 0);
-- DRPDO : IN std_logic_vector(15 downto 0);
-- DRPDI : OUT std_logic_vector(15 downto 0);
-- DRPRDY : IN std_logic;
-- DRPEN : OUT std_logic;
-- DRPWE : OUT std_logic;
-- DRP_BUSY_IN : IN std_logic;
-- DRP_RATE_BUSY_OUT : OUT std_logic
--);
--end component;
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal rxpmaresetdone_t : std_logic;
signal gtrxreset_out : std_logic;
signal rxpmareset_out : std_logic;
signal rxrate_out : std_logic_vector(2 downto 0);
signal drp_op_done : std_logic;
signal drp_pma_busy : std_logic;
signal drp_rate_busy : std_logic;
signal drp_busy_i1 : std_logic:= '0';
signal drp_busy_i2 : std_logic:= '0';
signal drpen_rst_t : std_logic;
signal drpaddr_rst_t : std_logic_vector(8 downto 0);
signal drpwe_rst_t : std_logic;
signal drpdo_rst_t : std_logic_vector(15 downto 0);
signal drpdi_rst_t : std_logic_vector(15 downto 0);
signal drprdy_rst_t : std_logic;
signal drpen_pma_t : std_logic;
signal drpaddr_pma_t : std_logic_vector(8 downto 0);
signal drpwe_pma_t : std_logic;
signal drpdo_pma_t : std_logic_vector(15 downto 0);
signal drpdi_pma_t : std_logic_vector(15 downto 0);
signal drprdy_pma_t : std_logic;
signal drpen_rate_t : std_logic;
signal drpaddr_rate_t : std_logic_vector(8 downto 0);
signal drpwe_rate_t : std_logic;
signal drpdo_rate_t : std_logic_vector(15 downto 0);
signal drpdi_rate_t : std_logic_vector(15 downto 0);
signal drprdy_rate_t : std_logic;
signal drpen_i : std_logic;
signal drpaddr_i : std_logic_vector(8 downto 0);
signal drpwe_i : std_logic;
signal drpdo_i : std_logic_vector(15 downto 0);
signal drpdi_i : std_logic_vector(15 downto 0);
signal drprdy_i : std_logic;
-- RX Datapath signals
signal rxdata_i : std_logic_vector(31 downto 0);
signal rxchariscomma_float_i : std_logic_vector(1 downto 0);
signal rxcharisk_float_i : std_logic_vector(1 downto 0);
signal rxdisperr_float_i : std_logic_vector(1 downto 0);
signal rxnotintable_float_i : std_logic_vector(1 downto 0);
signal rxrundisp_float_i : std_logic_vector(1 downto 0);
-- TX Datapath signals
signal txdata_i : std_logic_vector(31 downto 0);
signal txkerr_float_i : std_logic_vector(1 downto 0);
signal txrundisp_float_i : std_logic_vector(1 downto 0);
signal rxdatavalid_float_i : std_logic;
--******************************** Main Body of Code***************************
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
------------------- GT Datapath byte mapping -----------------
RXDATA_OUT <= rxdata_i(15 downto 0);
txdata_i <= (tied_to_ground_vec_i(15 downto 0) & TXDATA_IN);
----------------------------- GTPE2 Instance --------------------------
gtpe2_i : GTPE2_CHANNEL
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => ("TRUE"),
SIM_RESET_SPEEDUP => (GT_SIM_GTRESET_SPEEDUP),
SIM_TX_EIDLE_DRIVE_LEVEL => ("X"),
SIM_VERSION => ("2.0"),
------------------RX Byte and Word Alignment Attributes---------------
ALIGN_COMMA_DOUBLE => ("FALSE"),
ALIGN_COMMA_ENABLE => ("0001111111"),
ALIGN_COMMA_WORD => (2),
ALIGN_MCOMMA_DET => ("TRUE"),
ALIGN_MCOMMA_VALUE => ("1010000011"),
ALIGN_PCOMMA_DET => ("TRUE"),
ALIGN_PCOMMA_VALUE => ("0101111100"),
SHOW_REALIGN_COMMA => ("FALSE"),
RXSLIDE_AUTO_WAIT => (7),
RXSLIDE_MODE => ("PCS"),
RX_SIG_VALID_DLY => (10),
------------------RX 8B/10B Decoder Attributes---------------
RX_DISPERR_SEQ_MATCH => ("TRUE"),
DEC_MCOMMA_DETECT => ("TRUE"),
DEC_PCOMMA_DETECT => ("TRUE"),
DEC_VALID_COMMA_ONLY => ("TRUE"),
------------------------RX Clock Correction Attributes----------------------
CBCC_DATA_SOURCE_SEL => ("DECODED"),
CLK_COR_SEQ_2_USE => ("FALSE"),
CLK_COR_KEEP_IDLE => ("FALSE"),
CLK_COR_MAX_LAT => (10),
CLK_COR_MIN_LAT => (8),
CLK_COR_PRECEDENCE => ("TRUE"),
CLK_COR_REPEAT_WAIT => (0),
CLK_COR_SEQ_LEN => (1),
CLK_COR_SEQ_1_ENABLE => ("1111"),
CLK_COR_SEQ_1_1 => ("0100000000"),
CLK_COR_SEQ_1_2 => ("0000000000"),
CLK_COR_SEQ_1_3 => ("0000000000"),
CLK_COR_SEQ_1_4 => ("0000000000"),
CLK_CORRECT_USE => ("FALSE"),
CLK_COR_SEQ_2_ENABLE => ("1111"),
CLK_COR_SEQ_2_1 => ("0100000000"),
CLK_COR_SEQ_2_2 => ("0000000000"),
CLK_COR_SEQ_2_3 => ("0000000000"),
CLK_COR_SEQ_2_4 => ("0000000000"),
------------------------RX Channel Bonding Attributes----------------------
CHAN_BOND_KEEP_ALIGN => ("FALSE"),
CHAN_BOND_MAX_SKEW => (1),
CHAN_BOND_SEQ_LEN => (1),
CHAN_BOND_SEQ_1_1 => ("0000000000"),
CHAN_BOND_SEQ_1_2 => ("0000000000"),
CHAN_BOND_SEQ_1_3 => ("0000000000"),
CHAN_BOND_SEQ_1_4 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE => ("1111"),
CHAN_BOND_SEQ_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2 => ("0000000000"),
CHAN_BOND_SEQ_2_3 => ("0000000000"),
CHAN_BOND_SEQ_2_4 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE => ("1111"),
CHAN_BOND_SEQ_2_USE => ("FALSE"),
FTS_DESKEW_SEQ_ENABLE => ("1111"),
FTS_LANE_DESKEW_CFG => ("1111"),
FTS_LANE_DESKEW_EN => ("FALSE"),
---------------------------RX Margin Analysis Attributes----------------------------
ES_CONTROL => ("000000"),
ES_ERRDET_EN => ("FALSE"),
ES_EYE_SCAN_EN => ("FALSE"),
ES_HORZ_OFFSET => (x"010"),
ES_PMA_CFG => ("0000000000"),
ES_PRESCALE => ("00000"),
ES_QUALIFIER => (x"00000000000000000000"),
ES_QUAL_MASK => (x"00000000000000000000"),
ES_SDATA_MASK => (x"00000000000000000000"),
ES_VERT_OFFSET => ("000000000"),
-------------------------FPGA RX Interface Attributes-------------------------
RX_DATA_WIDTH => (20),
---------------------------PMA Attributes----------------------------
OUTREFCLK_SEL_INV => ("11"),
PMA_RSV => (x"00000333"),
PMA_RSV2 => (x"00002040"),
PMA_RSV3 => ("00"),
PMA_RSV4 => ("0000"),
RX_BIAS_CFG => ("0000111100110011"),
DMONITOR_CFG => (x"000A00"),
RX_CM_SEL => ("01"),
RX_CM_TRIM => ("0000"),
RX_DEBUG_CFG => ("00000000000000"),
RX_OS_CFG => ("0000010000000"),
TERM_RCAL_CFG => ("100001000010000"),
TERM_RCAL_OVRD => ("000"),
TST_RSV => (x"00000000"),
RX_CLK25_DIV => (5),
TX_CLK25_DIV => (5),
UCODEER_CLR => ('0'),
---------------------------PCI Express Attributes----------------------------
PCS_PCIE_EN => ("FALSE"),
---------------------------PCS Attributes----------------------------
PCS_RSVD_ATTR => (x"000000000000"),
-------------RX Buffer Attributes------------
RXBUF_ADDR_MODE => ("FAST"),
RXBUF_EIDLE_HI_CNT => ("1000"),
RXBUF_EIDLE_LO_CNT => ("0000"),
RXBUF_EN => ("TRUE"),
RX_BUFFER_CFG => ("000000"),
RXBUF_RESET_ON_CB_CHANGE => ("TRUE"),
RXBUF_RESET_ON_COMMAALIGN => ("FALSE"),
RXBUF_RESET_ON_EIDLE => ("FALSE"),
RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
RXBUFRESET_TIME => ("00001"),
RXBUF_THRESH_OVFLW => (61),
RXBUF_THRESH_OVRD => ("FALSE"),
RXBUF_THRESH_UNDFLW => (4),
RXDLY_CFG => (x"001F"),
RXDLY_LCFG => (x"030"),
RXDLY_TAP_CFG => (x"0000"),
RXPH_CFG => (x"C00002"),
RXPHDLY_CFG => (x"084020"),
RXPH_MONITOR_SEL => ("00000"),
RX_XCLK_SEL => ("RXREC"),
RX_DDI_SEL => ("000000"),
RX_DEFER_RESET_BUF_EN => ("TRUE"),
-----------------------CDR Attributes-------------------------
--For Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
--For Display Port, HBR2 - set RXCDR_CFG=72'h038c008bff20200010
--For SATA Gen1 GTX- set RXCDR_CFG=72'h03_8000_8BFF_4010_0008
--For SATA Gen2 GTX- set RXCDR_CFG=72'h03_8800_8BFF_4020_0008
--For SATA Gen3 GTX- set RXCDR_CFG=72'h03_8000_8BFF_1020_0010
--For SATA Gen3 GTP- set RXCDR_CFG=83'h0_0000_87FE_2060_2444_1010
--For SATA Gen2 GTP- set RXCDR_CFG=83'h0_0000_47FE_2060_2448_1010
--For SATA Gen1 GTP- set RXCDR_CFG=83'h0_0000_47FE_1060_2448_1010
RXCDR_CFG => (x"0000107FE106001041010"),
RXCDR_FR_RESET_ON_EIDLE => ('0'),
RXCDR_HOLD_DURING_EIDLE => ('0'),
RXCDR_PH_RESET_ON_EIDLE => ('0'),
RXCDR_LOCK_CFG => ("001001"),
-------------------RX Initialization and Reset Attributes-------------------
RXCDRFREQRESET_TIME => ("00001"),
RXCDRPHRESET_TIME => ("00001"),
RXISCANRESET_TIME => ("00001"),
RXPCSRESET_TIME => ("00001"),
RXPMARESET_TIME => ("00011"),
-------------------RX OOB Signaling Attributes-------------------
RXOOB_CFG => ("0000110"),
-------------------------RX Gearbox Attributes---------------------------
RXGEARBOX_EN => ("FALSE"),
GEARBOX_MODE => ("000"),
-------------------------PRBS Detection Attribute-----------------------
RXPRBS_ERR_LOOPBACK => ('0'),
-------------Power-Down Attributes----------
PD_TRANS_TIME_FROM_P2 => (x"03c"),
PD_TRANS_TIME_NONE_P2 => (x"3c"),
PD_TRANS_TIME_TO_P2 => (x"64"),
-------------RX OOB Signaling Attributes----------
SAS_MAX_COM => (64),
SAS_MIN_COM => (36),
SATA_BURST_SEQ_LEN => ("0101"),
SATA_BURST_VAL => ("100"),
SATA_EIDLE_VAL => ("100"),
SATA_MAX_BURST => (8),
SATA_MAX_INIT => (21),
SATA_MAX_WAKE => (7),
SATA_MIN_BURST => (4),
SATA_MIN_INIT => (12),
SATA_MIN_WAKE => (4),
-------------RX Fabric Clock Output Control Attributes----------
TRANS_TIME_RATE => (x"0E"),
--------------TX Buffer Attributes----------------
TXBUF_EN => ("TRUE"),
TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
TXDLY_CFG => (x"001F"),
TXDLY_LCFG => (x"030"),
TXDLY_TAP_CFG => (x"0000"),
TXPH_CFG => (x"0780"),
TXPHDLY_CFG => (x"084020"),
TXPH_MONITOR_SEL => ("00000"),
TX_XCLK_SEL => ("TXOUT"),
-------------------------FPGA TX Interface Attributes-------------------------
TX_DATA_WIDTH => (20),
-------------------------TX Configurable Driver Attributes-------------------------
TX_DEEMPH0 => ("000000"),
TX_DEEMPH1 => ("000000"),
TX_EIDLE_ASSERT_DELAY => ("110"),
TX_EIDLE_DEASSERT_DELAY => ("100"),
TX_LOOPBACK_DRIVE_HIZ => ("FALSE"),
TX_MAINCURSOR_SEL => ('0'),
TX_DRIVE_MODE => ("DIRECT"),
TX_MARGIN_FULL_0 => ("1001110"),
TX_MARGIN_FULL_1 => ("1001001"),
TX_MARGIN_FULL_2 => ("1000101"),
TX_MARGIN_FULL_3 => ("1000010"),
TX_MARGIN_FULL_4 => ("1000000"),
TX_MARGIN_LOW_0 => ("1000110"),
TX_MARGIN_LOW_1 => ("1000100"),
TX_MARGIN_LOW_2 => ("1000010"),
TX_MARGIN_LOW_3 => ("1000000"),
TX_MARGIN_LOW_4 => ("1000000"),
-------------------------TX Gearbox Attributes--------------------------
TXGEARBOX_EN => ("FALSE"),
-------------------------TX Initialization and Reset Attributes--------------------------
TXPCSRESET_TIME => ("00001"),
TXPMARESET_TIME => ("00001"),
-------------------------TX Receiver Detection Attributes--------------------------
TX_RXDETECT_CFG => (x"1832"),
TX_RXDETECT_REF => ("100"),
------------------ JTAG Attributes ---------------
ACJTAG_DEBUG_MODE => ('0'),
ACJTAG_MODE => ('0'),
ACJTAG_RESET => ('0'),
------------------ CDR Attributes ---------------
CFOK_CFG => (x"49000040E80"),
CFOK_CFG2 => ("0100000"),
CFOK_CFG3 => ("0100000"),
CFOK_CFG4 => ('0'),
CFOK_CFG5 => (x"0"),
CFOK_CFG6 => ("0000"),
RXOSCALRESET_TIME => ("00011"),
RXOSCALRESET_TIMEOUT => ("00000"),
------------------ PMA Attributes ---------------
CLK_COMMON_SWING => ('0'),
RX_CLKMUX_EN => ('1'),
TX_CLKMUX_EN => ('1'),
ES_CLK_PHASE_SEL => ('0'),
USE_PCS_CLK_PHASE_SEL => ('0'),
PMA_RSV6 => ('0'),
PMA_RSV7 => ('0'),
------------------ TX Configuration Driver Attributes ---------------
TX_PREDRIVER_MODE => ('0'),
PMA_RSV5 => ('0'),
SATA_PLL_CFG => ("VCO_3000MHZ"),
------------------ RX Fabric Clock Output Control Attributes ---------------
RXOUT_DIV => (4),
------------------ TX Fabric Clock Output Control Attributes ---------------
TXOUT_DIV => (4),
------------------ RX Phase Interpolator Attributes---------------
RXPI_CFG0 => ("000"),
RXPI_CFG1 => ('1'),
RXPI_CFG2 => ('1'),
--------------RX Equalizer Attributes-------------
ADAPT_CFG0 => (x"00000"),
RXLPMRESET_TIME => ("0001111"),
RXLPM_BIAS_STARTUP_DISABLE => ('0'),
RXLPM_CFG => ("0110"),
RXLPM_CFG1 => ('0'),
RXLPM_CM_CFG => ('0'),
RXLPM_GC_CFG => ("111100010"),
RXLPM_GC_CFG2 => ("001"),
RXLPM_HF_CFG => ("00001111110000"),
RXLPM_HF_CFG2 => ("01010"),
RXLPM_HF_CFG3 => ("0000"),
RXLPM_HOLD_DURING_EIDLE => ('0'),
RXLPM_INCM_CFG => ('0'),
RXLPM_IPCM_CFG => ('1'),
RXLPM_LF_CFG => ("000000001111110000"),
RXLPM_LF_CFG2 => ("01010"),
RXLPM_OSINT_CFG => ("100"),
------------------ TX Phase Interpolator PPM Controller Attributes---------------
TXPI_CFG0 => ("00"),
TXPI_CFG1 => ("00"),
TXPI_CFG2 => ("00"),
TXPI_CFG3 => ('0'),
TXPI_CFG4 => ('0'),
TXPI_CFG5 => ("000"),
TXPI_GREY_SEL => ('0'),
TXPI_INVSTROBE_SEL => ('0'),
TXPI_PPMCLK_SEL => ("TXUSRCLK2"),
TXPI_PPM_CFG => (x"00"),
TXPI_SYNFREQ_PPM => ("001"),
------------------ LOOPBACK Attributes---------------
LOOPBACK_CFG => ('0'),
PMA_LOOPBACK_CFG => ('0'),
------------------RX OOB Signalling Attributes---------------
RXOOB_CLK_CFG => ("PMA"),
------------------TX OOB Signalling Attributes---------------
TXOOB_CFG => ('0'),
------------------RX Buffer Attributes---------------
RXSYNC_MULTILANE => ('0'),
RXSYNC_OVRD => ('0'),
RXSYNC_SKIP_DA => ('0'),
------------------TX Buffer Attributes---------------
TXSYNC_MULTILANE => (TXSYNC_MULTILANE_IN),
TXSYNC_OVRD => (TXSYNC_OVRD_IN),
TXSYNC_SKIP_DA => ('0')
)
port map
(
--------------------------------- CPLL Ports -------------------------------
GTRSVD => "0000000000000000",
PCSRSVDIN => "0000000000000000",
TSTIN => "11111111111111111111",
---------------------------- Channel - DRP Ports --------------------------
DRPADDR => drpaddr_i,
DRPCLK => DRPCLK_IN,
DRPDI => drpdi_i,
DRPDO => drpdo_i,
DRPEN => drpen_i,
DRPRDY => drprdy_i,
DRPWE => drpwe_i,
------------------------------- Clocking Ports -----------------------------
RXSYSCLKSEL => "11",
TXSYSCLKSEL => "11",
----------------- FPGA TX Interface Datapath Configuration ----------------
TX8B10BEN => tied_to_vcc_i,
------------------------ GTPE2_CHANNEL Clocking Ports ----------------------
PLL0CLK => PLL0CLK_IN,
PLL0REFCLK => PLL0REFCLK_IN,
PLL1CLK => PLL1CLK_IN,
PLL1REFCLK => PLL1REFCLK_IN,
------------------------------- Loopback Ports -----------------------------
LOOPBACK => LOOPBACK_IN,
----------------------------- PCI Express Ports ----------------------------
PHYSTATUS => open,
RXRATE => tied_to_ground_vec_i(2 downto 0),
RXVALID => open,
----------------------------- PMA Reserved Ports ---------------------------
PMARSVDIN3 => '0',
PMARSVDIN4 => '0',
------------------------------ Power-Down Ports ----------------------------
RXPD => "00",
TXPD => "00",
-------------------------- RX 8B/10B Decoder Ports -------------------------
SETERRSTATUS => tied_to_ground_i,
--------------------- RX Initialization and Reset Ports --------------------
EYESCANRESET => tied_to_ground_i,
RXUSERRDY => RXUSERRDY_IN,
-------------------------- RX Margin Analysis Ports ------------------------
EYESCANDATAERROR => EYESCANDATAERROR_OUT,
EYESCANMODE => tied_to_ground_i,
EYESCANTRIGGER => tied_to_ground_i,
------------------------------- Receive Ports ------------------------------
CLKRSVD0 => tied_to_ground_i,
CLKRSVD1 => tied_to_ground_i,
DMONFIFORESET => tied_to_ground_i,
DMONITORCLK => tied_to_ground_i,
RXPMARESETDONE => rxpmaresetdone_t,
SIGVALIDCLK => tied_to_ground_i,
------------------------- Receive Ports - CDR Ports ------------------------
RXCDRFREQRESET => tied_to_ground_i,
RXCDRHOLD => tied_to_ground_i,
RXCDRLOCK => open,
RXCDROVRDEN => tied_to_ground_i,
RXCDRRESET => tied_to_ground_i,
RXCDRRESETRSV => tied_to_ground_i,
RXOSCALRESET => tied_to_ground_i,
RXOSINTCFG => "0010",
RXOSINTDONE => open,
RXOSINTHOLD => tied_to_ground_i,
RXOSINTOVRDEN => tied_to_ground_i,
RXOSINTPD => tied_to_ground_i,
RXOSINTSTARTED => open,
RXOSINTSTROBE => tied_to_ground_i,
RXOSINTSTROBESTARTED => open,
RXOSINTTESTOVRDEN => tied_to_ground_i,
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT => open,
---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
RX8B10BEN => tied_to_vcc_i,
------------------ Receive Ports - FPGA RX Interface Ports -----------------
RXDATA => rxdata_i,
RXUSRCLK => RXUSRCLK_IN,
RXUSRCLK2 => RXUSRCLK2_IN,
------------------- Receive Ports - Pattern Checker Ports ------------------
RXPRBSERR => open,
RXPRBSSEL => tied_to_ground_vec_i(2 downto 0),
------------------- Receive Ports - Pattern Checker ports ------------------
RXPRBSCNTRESET => tied_to_ground_i,
------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
RXCHARISCOMMA(3 downto 2) => rxchariscomma_float_i,
RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA_OUT,
RXCHARISK(3 downto 2) => rxcharisk_float_i,
RXCHARISK(1 downto 0) => RXCHARISK_OUT,
RXDISPERR(3 downto 2) => rxdisperr_float_i,
RXDISPERR(1 downto 0) => RXDISPERR_OUT,
RXNOTINTABLE(3 downto 2) => rxnotintable_float_i,
RXNOTINTABLE(1 downto 0) => RXNOTINTABLE_OUT,
------------------------ Receive Ports - RX AFE Ports ----------------------
GTPRXN => GTPRXN_IN,
GTPRXP => GTPRXP_IN,
PMARSVDIN2 => '0',
PMARSVDOUT0 => open,
PMARSVDOUT1 => open,
------------------- Receive Ports - RX Buffer Bypass Ports -----------------
RXBUFRESET => tied_to_ground_i,
RXBUFSTATUS => open,
RXDDIEN => tied_to_ground_i,
RXDLYBYPASS => tied_to_vcc_i,
RXDLYEN => tied_to_ground_i,
RXDLYOVRDEN => tied_to_ground_i,
RXDLYSRESET => tied_to_ground_i,
RXDLYSRESETDONE => open,
RXPHALIGN => tied_to_ground_i,
RXPHALIGNDONE => open,
RXPHALIGNEN => tied_to_ground_i,
RXPHDLYPD => tied_to_ground_i,
RXPHDLYRESET => tied_to_ground_i,
RXPHMONITOR => open,
RXPHOVRDEN => tied_to_ground_i,
RXPHSLIPMONITOR => open,
RXSTATUS => open,
RXSYNCALLIN => tied_to_ground_i,
RXSYNCDONE => open,
RXSYNCIN => tied_to_ground_i,
RXSYNCMODE => tied_to_ground_i,
RXSYNCOUT => open,
-------------- Receive Ports - RX Byte and Word Alignment Ports ------------
RXBYTEISALIGNED => RXBYTEISALIGNED_OUT,
RXBYTEREALIGN => open,
RXCOMMADET => RXCOMMADET_OUT,
RXCOMMADETEN => tied_to_vcc_i,
RXMCOMMAALIGNEN => tied_to_ground_i,
RXPCOMMAALIGNEN => tied_to_ground_i,
RXSLIDE => RXSLIDE_IN,
------------------ Receive Ports - RX Channel Bonding Ports ----------------
RXCHANBONDSEQ => open,
RXCHBONDEN => tied_to_ground_i,
RXCHBONDI => "0000",
RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0),
RXCHBONDMASTER => tied_to_ground_i,
RXCHBONDO => open,
RXCHBONDSLAVE => tied_to_ground_i,
----------------- Receive Ports - RX Channel Bonding Ports ----------------
RXCHANISALIGNED => open,
RXCHANREALIGN => open,
------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
DMONITOROUT => open,
RXADAPTSELTEST => tied_to_ground_vec_i(13 downto 0),
RXDFEXYDEN => tied_to_ground_i,
RXOSINTEN => '1',
RXOSINTID0 => tied_to_ground_vec_i(3 downto 0),
RXOSINTNTRLEN => tied_to_ground_i,
RXOSINTSTROBEDONE => open,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXLPMLFOVRDEN => tied_to_ground_i,
RXLPMOSINTNTRLEN => tied_to_ground_i,
-------------------- Receive Ports - RX Equailizer Ports -------------------
RXLPMHFHOLD => rxlpmhfhold_in,
RXLPMHFOVRDEN => tied_to_ground_i,
RXLPMLFHOLD => rxlpmlfhold_in,
--------------------- Receive Ports - RX Equalizer Ports -------------------
RXOSHOLD => tied_to_ground_i,
RXOSOVRDEN => tied_to_ground_i,
------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
RXRATEDONE => open,
----------- Receive Ports - RX Fabric Clock Output Control Ports ----------
RXRATEMODE => '0',
--------------- Receive Ports - RX Fabric Output Control Ports -------------
RXOUTCLK => RXOUTCLK_OUT,
RXOUTCLKFABRIC => open,
RXOUTCLKPCS => open,
RXOUTCLKSEL => "010",
---------------------- Receive Ports - RX Gearbox Ports --------------------
RXDATAVALID => open,
RXHEADER => open,
RXHEADERVALID => open,
RXSTARTOFSEQ => open,
--------------------- Receive Ports - RX Gearbox Ports --------------------
RXGEARBOXSLIP => tied_to_ground_i,
------------- Receive Ports - RX Initialization and Reset Ports ------------
GTRXRESET => gtrxreset_out,
RXLPMRESET => tied_to_ground_i,
RXOOBRESET => tied_to_ground_i,
RXPCSRESET => tied_to_ground_i,
RXPMARESET => tied_to_ground_i,
------------------- Receive Ports - RX OOB Signaling ports -----------------
RXCOMSASDET => open,
RXCOMWAKEDET => open,
------------------ Receive Ports - RX OOB Signaling ports -----------------
RXCOMINITDET => open,
------------------ Receive Ports - RX OOB signalling Ports -----------------
RXELECIDLE => open,
RXELECIDLEMODE => "11",
----------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY => tied_to_ground_i,
-------------- Receive Ports -RX Initialization and Reset Ports ------------
RXRESETDONE => RXRESETDONE_OUT,
--------------------------- TX Buffer Bypass Ports -------------------------
TXPHDLYTSTCLK => tied_to_ground_i,
------------------------ TX Configurable Driver Ports ----------------------
TXPOSTCURSOR => "00000",
TXPOSTCURSORINV => tied_to_ground_i,
TXPRECURSOR => tied_to_ground_vec_i(4 downto 0),
TXPRECURSORINV => tied_to_ground_i,
-------------------- TX Fabric Clock Output Control Ports ------------------
TXRATEMODE => tied_to_ground_i,
--------------------- TX Initialization and Reset Ports --------------------
CFGRESET => tied_to_ground_i,
GTTXRESET => GTTXRESET_IN,
PCSRSVDOUT => open,
TXUSERRDY => TXUSERRDY_IN,
----------------- TX Phase Interpolator PPM Controller Ports ---------------
TXPIPPMEN => tied_to_ground_i,
TXPIPPMOVRDEN => tied_to_ground_i,
TXPIPPMPD => tied_to_ground_i,
TXPIPPMSEL => tied_to_vcc_i,
TXPIPPMSTEPSIZE => tied_to_ground_vec_i(4 downto 0),
---------------------- Transceiver Reset Mode Operation --------------------
GTRESETSEL => tied_to_ground_i,
RESETOVRD => tied_to_ground_i,
------------------------------- Transmit Ports -----------------------------
TXPMARESETDONE => open,
----------------- Transmit Ports - Configurable Driver Ports ---------------
PMARSVDIN0 => '0',
PMARSVDIN1 => '0',
------------------ Transmit Ports - FPGA TX Interface Ports ----------------
TXDATA => txdata_i,
TXUSRCLK => TXUSRCLK_IN,
TXUSRCLK2 => TXUSRCLK2_IN,
--------------------- Transmit Ports - PCI Express Ports -------------------
TXELECIDLE => tied_to_ground_i,
TXMARGIN => tied_to_ground_vec_i(2 downto 0),
TXRATE => tied_to_ground_vec_i(2 downto 0),
TXSWING => tied_to_ground_i,
------------------ Transmit Ports - Pattern Generator Ports ----------------
TXPRBSFORCEERR => tied_to_ground_i,
------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
TX8B10BBYPASS => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPVAL => tied_to_ground_vec_i(3 downto 0),
TXCHARISK(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
TXCHARISK(1 downto 0) => TXCHARISK_IN,
------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
TXDLYBYPASS => tied_to_vcc_i,
TXDLYEN => tied_to_ground_i,
TXDLYHOLD => tied_to_ground_i,
TXDLYOVRDEN => tied_to_ground_i,
TXDLYSRESET => tied_to_ground_i,
TXDLYSRESETDONE => open,
TXDLYUPDOWN => tied_to_ground_i,
TXPHALIGN => tied_to_ground_i,
TXPHALIGNDONE => open,
TXPHALIGNEN => tied_to_ground_i,
TXPHDLYPD => tied_to_ground_i,
TXPHDLYRESET => tied_to_ground_i,
TXPHINIT => tied_to_ground_i,
TXPHINITDONE => open,
TXPHOVRDEN => tied_to_ground_i,
---------------------- Transmit Ports - TX Buffer Ports --------------------
TXBUFSTATUS => open,
------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
TXSYNCALLIN => tied_to_ground_i,
TXSYNCDONE => open,
TXSYNCIN => tied_to_ground_i,
TXSYNCMODE => tied_to_ground_i,
TXSYNCOUT => open,
--------------- Transmit Ports - TX Configurable Driver Ports --------------
GTPTXN => GTPTXN_OUT,
GTPTXP => GTPTXP_OUT,
TXBUFDIFFCTRL => "100",
TXDEEMPH => tied_to_ground_i,
TXDIFFCTRL => "1000",
TXDIFFPD => tied_to_ground_i,
TXINHIBIT => tied_to_ground_i,
TXMAINCURSOR => "0000000",
TXPISOPD => tied_to_ground_i,
----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
TXOUTCLK => TXOUTCLK_OUT,
TXOUTCLKFABRIC => TXOUTCLKFABRIC_OUT,
TXOUTCLKPCS => TXOUTCLKPCS_OUT,
TXOUTCLKSEL => "010",
TXRATEDONE => open,
--------------------- Transmit Ports - TX Gearbox Ports --------------------
TXGEARBOXREADY => open,
TXHEADER => tied_to_ground_vec_i(2 downto 0),
TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
TXSTARTSEQ => tied_to_ground_i,
------------- Transmit Ports - TX Initialization and Reset Ports -----------
TXPCSRESET => tied_to_ground_i,
TXPMARESET => tied_to_ground_i,
TXRESETDONE => TXRESETDONE_OUT,
------------------ Transmit Ports - TX OOB signalling Ports ----------------
TXCOMFINISH => open,
TXCOMINIT => tied_to_ground_i,
TXCOMSAS => tied_to_ground_i,
TXCOMWAKE => tied_to_ground_i,
TXPDELECIDLEMODE => tied_to_ground_i,
----------------- Transmit Ports - TX Polarity Control Ports ---------------
TXPOLARITY => tied_to_ground_i,
--------------- Transmit Ports - TX Receiver Detection Ports --------------
TXDETECTRX => tied_to_ground_i,
------------------ Transmit Ports - pattern Generator Ports ----------------
TXPRBSSEL => TXPRBSSEL_IN
);
------------------------- Soft Fix for Production Silicon----------------------
gtrxreset_seq_i : whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq
port map
(
RST => RST_IN,
GTRXRESET_IN => GTRXRESET_IN,
RXPMARESETDONE => rxpmaresetdone_t,
GTRXRESET_OUT => gtrxreset_out,
DRP_OP_DONE => drp_op_done,
DRPCLK => DRPCLK_IN,
DRPEN => drpen_rst_t,
DRPADDR => drpaddr_rst_t,
DRPWE => drpwe_rst_t,
DRPDO => drpdo_rst_t,
DRPDI => drpdi_rst_t,
DRPRDY => drprdy_rst_t
);
drpen_i <= drpen_rst_t when drp_op_done ='0' else
drpen_pma_t when drp_pma_busy = '1' else
drpen_rate_t when drp_rate_busy ='1' else DRPEN_IN;
drpaddr_i <= drpaddr_rst_t when drp_op_done ='0' else
drpaddr_pma_t when drp_pma_busy = '1' else
drpaddr_rate_t when drp_rate_busy ='1' else DRPADDR_IN;
drpwe_i <= drpwe_rst_t when drp_op_done ='0' else
drpwe_pma_t when drp_pma_busy = '1' else
drpwe_rate_t when drp_rate_busy ='1' else DRPWE_IN;
DRPDO_OUT <= drpdo_i when (drp_op_done='1' or drp_pma_busy='0' or drp_rate_busy='0') else x"0000";
drpdo_rst_t <= drpdo_i;
drpdo_pma_t <= drpdo_i;
drpdo_rate_t <= drpdo_i;
drpdi_i <= drpdi_rst_t when drp_op_done ='0' else
drpdi_pma_t when drp_pma_busy = '1' else
drpdi_rate_t when drp_rate_busy ='1' else DRPDI_IN;
DRPRDY_OUT <= drprdy_i when (drp_op_done='1' or drp_pma_busy='0' or drp_rate_busy='0') else '0';
drprdy_rst_t <= drprdy_i;
drprdy_pma_t <= drprdy_i;
drprdy_rate_t <= drprdy_i;
drp_pma_busy <= '0';
drp_rate_busy <= '0';
process (DRPCLK_IN)
begin
if(rising_edge(DRPCLK_IN)) then
if(drp_op_done = '0' or drp_rate_busy='1') then
drp_busy_i1 <= '1';
else
drp_busy_i1 <= '0';
end if;
end if;
end process;
process (DRPCLK_IN)
begin
if(rising_edge(DRPCLK_IN)) then
if(drp_op_done = '0' or drp_pma_busy='1') then
drp_busy_i2 <= '1';
else
drp_busy_i2 <= '0';
end if;
end if;
end process;
DRP_BUSY_OUT <= drp_busy_i1 or drp_busy_i2;
end RTL;
platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd 0 → 100644
View file @ ca0ea0a9
------------------------------------------------------------------------------/
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 3.6
-- \ \ Application : 7 Series FPGAs Transceivers Wizard
-- / / Filename : whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd
-- /___/ /\
-- \ \ / \
-- \___\/\___\
--
--
-- Module whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq
-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
--
--
-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
ENTITY whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq IS
port (
RST : IN std_logic; --Please add a synchroniser if it is not generated in DRPCLK domain.
GTRXRESET_IN : IN std_logic; --Please add a synchroniser if it is not generated in DRPCLK domain.
RXPMARESETDONE: IN std_logic;
GTRXRESET_OUT : OUT std_logic;
DRPCLK : IN std_logic;
DRPADDR : OUT std_logic_vector(8 downto 0);
DRPDO : IN std_logic_vector(15 downto 0);
DRPDI : OUT std_logic_vector(15 downto 0);
DRPRDY : IN std_logic;
DRPEN : OUT std_logic;
DRPWE : OUT std_logic;
DRP_OP_DONE : OUT std_logic
);
END whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq;
ARCHITECTURE Behavioral of whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq is
-- component whiterabbit_gtpe2_channel_wrapper_sync_block
-- generic (
-- INITIALISE : bit_vector(5 downto 0) := "000000"
-- );
-- port (
-- clk : in std_logic;
-- data_in : in std_logic;
-- data_out : out std_logic
-- );
-- end component;
constant DLY : time := 1 ns;
type state_type is (idle,
drp_rd,
wait_rd_data,
wr_16,
wait_wr_done1,
wait_pmareset,
wr_20,
wait_wr_done2);
signal state : state_type := idle;
signal next_state : state_type := idle;
signal gtrxreset_s : std_logic;
signal gtrxreset_ss : std_logic;
signal rxpmaresetdone_ss : std_logic;
signal rxpmaresetdone_sss : std_logic;
signal rd_data : std_logic_vector(15 downto 0);
signal next_rd_data : std_logic_vector(15 downto 0);
signal original_rd_data : std_logic_vector(15 downto 0);
signal pmarstdone_fall_edge:std_logic;
signal gtrxreset_i :std_logic;
signal flag :std_logic := '0';
signal gtrxreset_o :std_logic;
signal drpen_o :std_logic;
signal drpwe_o :std_logic;
signal drpaddr_o :std_logic_vector(8 downto 0);
signal drpdi_o :std_logic_vector(15 downto 0);
signal drp_op_done_o :std_logic;
signal rst_n :std_logic;
BEGIN
-- sync0_RXPMARESETDONE : whiterabbit_gtpe2_channel_wrapper_sync_block
-- port map
-- (
-- clk => DRPCLK,
-- data_in => RXPMARESETDONE,
-- data_out => rxpmaresetdone_ss
-- );
rst_n <= not RST;
sync0_RXPMARESETDONE : gc_sync_ffs
port map
(
clk_i => DRPCLK,
rst_n_i => rst_n,
data_i => RXPMARESETDONE,
synced_o => rxpmaresetdone_ss,
npulse_o => open,
ppulse_o => open
);
--output assignment
GTRXRESET_OUT <= gtrxreset_o;
DRPEN <= drpen_o;
DRPWE <= drpwe_o;
DRPADDR <= drpaddr_o;
DRPDI <= drpdi_o;
DRP_OP_DONE <= drp_op_done_o;
PROCESS (DRPCLK,RST)
BEGIN
IF (RST = '1') THEN
state <= idle after DLY;
gtrxreset_s <= '0' after DLY;
gtrxreset_ss <= '0' after DLY;
rxpmaresetdone_sss <= '0' after DLY;
rd_data <= x"0000" after DLY;
gtrxreset_o <= '0' after DLY;
ELSIF (DRPCLK'event and DRPCLK='1') THEN
state <= next_state after DLY;
gtrxreset_s <= GTRXRESET_IN after DLY;
gtrxreset_ss <= gtrxreset_s after DLY;
rxpmaresetdone_sss <= rxpmaresetdone_ss after DLY;
rd_data <= next_rd_data after DLY;
gtrxreset_o <= gtrxreset_i after DLY;
END IF;
END PROCESS;
PROCESS (DRPCLK,GTRXRESET_IN)
BEGIN
IF (GTRXRESET_IN = '1') THEN
drp_op_done_o <= '0' after DLY;
ELSIF (DRPCLK'event and DRPCLK='1') THEN
IF (state = wait_wr_done2 and DRPRDY = '1') THEN
drp_op_done_o <= '1' after DLY;
ELSE
drp_op_done_o <= drp_op_done_o after DLY;
END IF;
END IF;
END PROCESS;
pmarstdone_fall_edge <= (not rxpmaresetdone_ss) and (rxpmaresetdone_sss);
PROCESS (gtrxreset_ss,DRPRDY,state,pmarstdone_fall_edge)
BEGIN
CASE state IS
WHEN idle =>
IF (gtrxreset_ss='1') THEN
next_state <= drp_rd;
ELSE
next_state <= idle;
END IF;
WHEN drp_rd =>
next_state<= wait_rd_data;
WHEN wait_rd_data =>
IF (DRPRDY='1')THEN
next_state <= wr_16;
ELSE
next_state <= wait_rd_data;
END IF;
WHEN wr_16 =>
next_state <= wait_wr_done1;
WHEN wait_wr_done1 =>
IF (DRPRDY='1') THEN
next_state <= wait_pmareset;
ELSE
next_state <= wait_wr_done1;
END IF;
WHEN wait_pmareset =>
IF (pmarstdone_fall_edge='1') THEN
next_state <= wr_20;
ELSE
next_state <= wait_pmareset;
END IF;
WHEN wr_20 =>
next_state <= wait_wr_done2;
WHEN wait_wr_done2 =>
IF (DRPRDY='1') THEN
next_state <= idle;
ELSE
next_state <= wait_wr_done2;
END IF;
WHEN others=>
next_state <= idle;
END CASE;
END PROCESS;
-- drives DRP interface and GTRXRESET_OUT
PROCESS(DRPRDY,state,rd_data,DRPDO,gtrxreset_ss,flag,original_rd_data)
BEGIN
-- assert gtrxreset_out until wr to 16-bit is complete
-- RX_DATA_WIDTH is located at addr x"0011", [13 downto 11]
-- encoding is this : /16 = x "2", /20 = x"3", /32 = x"4", /40 = x"5"
gtrxreset_i <= '0';
drpaddr_o <= '0'& x"11"; -- 000010001
drpen_o <= '0';
drpwe_o <= '0';
drpdi_o <= x"0000";
next_rd_data <= rd_data;
CASE state IS
--do nothing to DRP or reset
WHEN idle => null;
--assert reset and issue rd
WHEN drp_rd =>
gtrxreset_i <= '1';
drpen_o <= '1';
drpwe_o <= '0';
--assert reset and wait to load rd data
WHEN wait_rd_data =>
gtrxreset_i <= '1';
IF (DRPRDY='1' and flag = '0') THEN
next_rd_data <= DRPDO;
ELSIF (DRPRDY='1' and flag = '1') THEN
next_rd_data <= original_rd_data;
ELSE
next_rd_data <= rd_data;
END IF;
--assert reset and write to 16-bit mode
WHEN wr_16=>
gtrxreset_i<= '1';
drpen_o <= '1';
drpwe_o <= '1';
-- Addr "00001001" [11] = '0' puts width mode in /16 or /32
drpdi_o <= rd_data(15 downto 12) & '0' & rd_data(10 downto 0);
--keep asserting reset until write to 16-bit mode is complete
WHEN wait_wr_done1=>
gtrxreset_i <= '1';
--deassert reset and no DRP access until 2nd pmareset
WHEN wait_pmareset => null;
IF (gtrxreset_ss='1') THEN
gtrxreset_i <= '1';
ELSE
gtrxreset_i <= '0';
END IF;
--write to 20-bit mode
WHEN wr_20 =>
drpen_o <='1';
drpwe_o <= '1';
drpdi_o <= rd_data(15 downto 0); --restore user setting per prev read
--wait to complete write to 20-bit mode
WHEN wait_wr_done2 =>
WHEN others => null;
END CASE;
END PROCESS;
process (DRPCLK)
begin
if (DRPCLK'event and DRPCLK='1') then
if( state = wr_16 or state = wait_pmareset or state = wr_20 or state = wait_wr_done1) then
flag <= '1';
elsif(state = wait_wr_done2) then
flag <= '0';
end if;
end if;
end process;
process (DRPCLK)
begin
if (DRPCLK'event and DRPCLK='1') then
if( state = wait_rd_data and DRPRDY ='1' and flag = '0') then
original_rd_data <= DRPDO;
end if;
end if;
end process;
END Behavioral;
platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_artix7.vhd 0 → 100644
View file @ ca0ea0a9
-------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - artix-7 top module
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wr_gtp_phy_artix7.vhd
-- Author : Peter Jansweijer, Rick Lohlefink, Tomasz Wlostowski
-- Company : Nikhef, CERN BE-CO-HT
-- Created : 2016-05-19
-- Last update: 2016-05-19
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Dual channel wrapper for Xilinx Artix-7 GTP adapted for
-- deterministic delays at 1.25 Gbps.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009-2011 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-19 0.1 PeterJ Initial release based on "wr_gtx_phy_kintex7.vhd"
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.disparity_gen_pkg.all;
entity wr_gtp_phy_artix7 is
generic (
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation : integer := 0
);
port (
-- Dedicated reference 125 MHz clock for the GTP transceiver
clk_gtp_i : in std_logic;
-- TX path, synchronous to tx_out_clk_o (62.5 MHz):
tx_out_clk_o : out std_logic;
tx_locked_o : out std_logic;
-- data input (8 bits, not 8b10b-encoded)
tx_data_i : in std_logic_vector(15 downto 0) := (others => '0');
-- 1 when tx_data_i contains a control code, 0 when it's a data byte
tx_k_i : in std_logic_vector(1 downto 0) := (others => '0');
-- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
-- Necessary for the PCS to generate proper frame termination sequences.
-- Generated for the 2nd byte (LSB) of tx_data_i.
tx_disparity_o : out std_logic;
-- Encoding error indication (1 = error, 0 = no error)
tx_enc_err_o : out std_logic;
-- RX path, synchronous to ch0_rx_rbclk_o.
-- RX recovered clock
rx_rbclk_o : out std_logic;
-- 8b10b-decoded data output. The data output must be kept invalid before
-- the transceiver is locked on the incoming signal to prevent the EP from
-- detecting a false carrier.
rx_data_o : out std_logic_vector(15 downto 0);
-- 1 when the byte on rx_data_o is a control code
rx_k_o : out std_logic_vector(1 downto 0);
-- encoding error indication
rx_enc_err_o : out std_logic;
-- RX bitslide indication, indicating the delay of the RX path of the
-- transceiver (in UIs). Must be valid when ch0_rx_data_o is valid.
rx_bitslide_o : out std_logic_vector(4 downto 0);
-- reset input, active hi
rst_i : in std_logic := '0';
loopen_i : in std_logic_vector(2 downto 0) := (others => '0');
tx_prbs_sel_i : in std_logic_vector(2 downto 0) := (others => '0');
pad_rxn_i : in std_logic := '0';
pad_rxp_i : in std_logic := '0';
pad_txn_o : out std_logic;
pad_txp_o : out std_logic;
rdy_o : out std_logic
);
end entity wr_gtp_phy_artix7;
--------------------------------------------------------------------------------
-- Object : Architecture work.wr_gtp_phy_artix7.structure
-- Last modified : Mon Nov 23 12:54:18 2015.
--------------------------------------------------------------------------------
architecture structure of wr_gtp_phy_artix7 is
constant REQ_DELAY : integer := 500; -- unit = ns
constant CLK_PER : integer := 8; -- unit = ns
constant INITIAL_WAIT_CYCLES : integer := REQ_DELAY / CLK_PER; -- Required 500 ns divided by RefClk period
constant TOTAL_DELAY : integer := INITIAL_WAIT_CYCLES + 10; -- Add 10 clock cycles as delay to be sure
constant c_rxcdrlock_max : integer := 3;
constant c_reset_cnt_max : integer := 64; -- Reset pulse width 64 * 8 = 512 ns
type state_type is (init, count, count_done, wait_reset);
signal state : state_type;
signal rst_synced : std_logic;
signal rst_int : std_logic;
signal rx_rec_clk : std_logic;
signal rx_rec_clk_bufin : std_logic;
attribute buffer_type : string;
attribute buffer_type of rx_rec_clk_bufin : signal is "bufg";
signal tx_out_clk : std_logic;
signal tx_out_clk_bufin : std_logic;
--attribute buffer_type of tx_out_clk_bufin : signal is "bufg";
signal rx_lost_lock : std_logic;
signal ready_for_reset : std_logic := '0';
signal serdes_ready : std_logic := '0';
signal rx_slide : std_logic := '0';
signal rx_rst_done : std_logic;
signal tx_rst_done : std_logic;
signal rx_comma_det : std_logic;
signal rx_byte_is_aligned : std_logic;
signal forced_rx_reset : std_logic;
signal rx_synced : std_logic;
signal rst_done : std_logic;
signal rst_done_n : std_logic;
signal pll_locked_i : std_logic;
signal pll_locked_n_i : std_logic;
signal rx_reset : std_logic;
signal rx_k_int : std_logic_vector(1 downto 0);
signal rx_data_int : std_logic_vector(15 downto 0);
signal rx_disp_err : std_logic_vector(1 downto 0);
signal rx_code_err : std_logic_vector(1 downto 0);
signal cur_disp : t_8b10b_disparity;
signal tx_is_k_swapped : std_logic_vector(1 downto 0);
signal tx_data_swapped : std_logic_vector(15 downto 0);
component whiterabbit_gtpe2_channel_wrapper is
generic
(
-- Simulation attributes
EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to "true" to speed up sim reset
);
port
(
--_________________________________________________________________________
--____________________________CHANNEL PORTS________________________________
GT0_DRP_BUSY_OUT : out std_logic;
---------------------------- Channel - DRP Ports --------------------------
GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
GT0_DRPCLK_IN : in std_logic;
GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
GT0_DRPEN_IN : in std_logic;
GT0_DRPRDY_OUT : out std_logic;
GT0_DRPWE_IN : in std_logic;
------------------------------- Loopback Ports -----------------------------
GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
--------------------- RX Initialization and Reset Ports --------------------
GT0_RXUSERRDY_IN : in std_logic;
-------------------------- RX Margin Analysis Ports ------------------------
GT0_EYESCANDATAERROR_OUT : out std_logic;
------------------ Receive Ports - FPGA RX Interface Ports -----------------
GT0_RXDATA_OUT : out std_logic_vector(15 downto 0);
GT0_RXUSRCLK_IN : in std_logic;
GT0_RXUSRCLK2_IN : in std_logic;
------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
GT0_RXCHARISCOMMA_OUT : out std_logic_vector(1 downto 0);
GT0_RXCHARISK_OUT : out std_logic_vector(1 downto 0);
GT0_RXDISPERR_OUT : out std_logic_vector(1 downto 0);
GT0_RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
------------------------ Receive Ports - RX AFE Ports ----------------------
GT0_GTPRXN_IN : in std_logic;
GT0_GTPRXP_IN : in std_logic;
-------------- Receive Ports - RX Byte and Word Alignment Ports ------------
GT0_RXBYTEISALIGNED_OUT : out std_logic;
GT0_RXCOMMADET_OUT : out std_logic;
GT0_RXSLIDE_IN : in std_logic;
--------------------- Receive Ports - RX Equilizer Ports -------------------
GT0_RXLPMHFHOLD_IN : in std_logic;
GT0_RXLPMLFHOLD_IN : in std_logic;
--------------- Receive Ports - RX Fabric Output Control Ports -------------
GT0_RXOUTCLK_OUT : out std_logic;
------------- Receive Ports - RX Initialization and Reset Ports ------------
GT0_GTRXRESET_IN : in std_logic;
-------------- Receive Ports -RX Initialization and Reset Ports ------------
GT0_RXRESETDONE_OUT : out std_logic;
--------------------- TX Initialization and Reset Ports --------------------
GT0_GTTXRESET_IN : in std_logic;
GT0_TXUSERRDY_IN : in std_logic;
------------------ Transmit Ports - FPGA TX Interface Ports ----------------
GT0_TXDATA_IN : in std_logic_vector(15 downto 0);
GT0_TXUSRCLK_IN : in std_logic;
GT0_TXUSRCLK2_IN : in std_logic;
------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
GT0_TXCHARISK_IN : in std_logic_vector(1 downto 0);
--------------- Transmit Ports - TX Configurable Driver Ports --------------
GT0_GTPTXN_OUT : out std_logic;
GT0_GTPTXP_OUT : out std_logic;
----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
GT0_TXOUTCLK_OUT : out std_logic;
GT0_TXOUTCLKFABRIC_OUT : out std_logic;
GT0_TXOUTCLKPCS_OUT : out std_logic;
------------- Transmit Ports - TX Initialization and Reset Ports -----------
GT0_TXRESETDONE_OUT : out std_logic;
------------------ Transmit Ports - pattern Generator Ports ----------------
GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
--____________________________COMMON PORTS________________________________
----------------- Common Block - GTPE2_COMMON Clocking Ports ---------------
GT0_GTREFCLK0_IN : in std_logic;
-------------------------- Common Block - PLL Ports ------------------------
GT0_PLL1LOCK_OUT : out std_logic;
GT0_PLL1LOCKDETCLK_IN : in std_logic;
GT0_PLL1REFCLKLOST_OUT : out std_logic;
GT0_PLL1RESET_IN : in std_logic
);
end component whiterabbit_gtpe2_channel_wrapper;
component gtp_bitslide is
generic (
g_simulation : integer;
g_target : string := "artix7"
);
port (
gtp_rst_i : in std_logic;
gtp_rx_clk_i : in std_logic;
gtp_rx_comma_det_i : in std_logic;
gtp_rx_byte_is_aligned_i : in std_logic;
serdes_ready_i : in std_logic;
gtp_rx_slide_o : out std_logic;
gtp_rx_cdr_rst_o : out std_logic;
bitslide_o : out std_logic_vector(4 downto 0);
synced_o : out std_logic
);
end component;
component BUFG
port (
I : in std_ulogic;
O : out std_ulogic);
end component BUFG;
function f_to_bool(x : integer) return string is
begin
if(x /= 0) then
return "TRUE";
else
return "FALSE";
end if;
end f_to_bool;
begin
U_EdgeDet_rst_i : gc_sync_ffs port map (
clk_i => clk_gtp_i,
rst_n_i => '1',
data_i => rst_i,
ppulse_o => rst_synced);
p_reset_pulse : process(clk_gtp_i, rst_synced)
variable reset_cnt : integer range 0 to c_reset_cnt_max;
begin
if(rst_synced = '1') then
reset_cnt := 0;
rst_int <= '1';
elsif rising_edge(clk_gtp_i) then
if reset_cnt /= c_reset_cnt_max then
reset_cnt := reset_cnt + 1;
rst_int <= '1';
else
rst_int <= '0';
end if;
end if;
end process;
-- ug482 "GTP Transceiver TX/RX Reset in Response to Completion of Configuration"
-- 1. Wait a minimum of 500 ns after configuration is complete
process(clk_gtp_i, rst_int) is
variable reset_counter : integer range 0 to TOTAL_DELAY := 0;
begin
if rst_int = '1' then
state <= init;
elsif rising_edge(clk_gtp_i) then
case state is
when init =>
reset_counter := 0;
state <= count;
when count =>
if reset_counter = TOTAL_DELAY then
reset_counter := 0;
state <= count_done;
else
reset_counter := reset_counter + 1;
state <= count;
end if;
when count_done =>
state <= wait_reset;
when wait_reset =>
state <= wait_reset;
end case;
end if;
end process;
ready_for_reset <= '1' when state = count_done else '0';
-- 7-Series GTP RXCDRLOCK is reserved (ug482 Table 4.11) and can not be used for detection of proper RX lock.
-- Instead use rx_code_err (i.e. RXNOTINTABLE) to check integrity of the received characters.
process(rx_rec_clk, rst_int) is
begin
if rst_int = '1' then
rx_lost_lock <= '1';
elsif rising_edge(rx_rec_clk) then
if rx_synced = '1' then
if rx_code_err > "00" then
rx_lost_lock <= '1';
else
rx_lost_lock <= '0';
end if;
else
rx_lost_lock <= '0';
end if;
end if;
end process;
tx_enc_err_o <= '0';
U_BUF_TxOutClk: BUFG
port map(
I => tx_out_clk_bufin,
O => tx_out_clk);
tx_out_clk_o <= tx_out_clk;
tx_locked_o <= pll_locked_i;
U_BUF_RxRecClk: BUFG
port map(
I => rx_rec_clk_bufin,
O => rx_rec_clk);
rx_rbclk_o <= rx_rec_clk;
tx_is_k_swapped <= tx_k_i(0) & tx_k_i(1);
tx_data_swapped <= tx_data_i(7 downto 0) & tx_data_i(15 downto 8);
U_GTP_INST : whiterabbit_gtpe2_channel_wrapper
generic map
(
-- Simulation attributes
EXAMPLE_SIMULATION => g_simulation,
WRAPPER_SIM_GTRESET_SPEEDUP => f_to_bool(g_simulation)
)
port map
(
--_________________________________________________________________________
--_________________________________________________________________________
--____________________________CHANNEL PORTS________________________________
GT0_DRP_BUSY_OUT => open,
---------------------------- Channel - DRP Ports --------------------------
GT0_DRPADDR_IN => (others => '0'),
GT0_DRPCLK_IN => clk_gtp_i,
GT0_DRPDI_IN => (others => '0'),
GT0_DRPDO_OUT => open,
GT0_DRPEN_IN => '0',
GT0_DRPRDY_OUT => open,
GT0_DRPWE_IN => '0',
------------------------------- Loopback Ports -----------------------------
GT0_LOOPBACK_IN => loopen_i,
--------------------- RX Initialization and Reset Ports --------------------
GT0_RXUSERRDY_IN => pll_locked_i,
-------------------------- RX Margin Analysis Ports ------------------------
GT0_EYESCANDATAERROR_OUT => open,
------------------ Receive Ports - FPGA RX Interface Ports -----------------
GT0_RXDATA_OUT => rx_data_int,
GT0_RXUSRCLK_IN => rx_rec_clk,
GT0_RXUSRCLK2_IN => rx_rec_clk,
------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
GT0_RXCHARISCOMMA_OUT => open,
GT0_RXCHARISK_OUT => rx_k_int,
GT0_RXDISPERR_OUT => rx_disp_err,
GT0_RXNOTINTABLE_OUT => rx_code_err,
------------------------ Receive Ports - RX AFE Ports ----------------------
GT0_GTPRXN_IN => pad_rxn_i,
GT0_GTPRXP_IN => pad_rxp_i,
-------------- Receive Ports - RX Byte and Word Alignment Ports ------------
GT0_RXBYTEISALIGNED_OUT => rx_byte_is_aligned,
GT0_RXCOMMADET_OUT => rx_comma_det,
GT0_RXSLIDE_IN => rx_slide,
--------------------- Receive Ports - RX Equilizer Ports -------------------
GT0_RXLPMHFHOLD_IN => '0',
GT0_RXLPMLFHOLD_IN => '0',
--------------- Receive Ports - RX Fabric Output Control Ports -------------
GT0_RXOUTCLK_OUT => rx_rec_clk_bufin,
------------- Receive Ports - RX Initialization and Reset Ports ------------
GT0_GTRXRESET_IN => rx_reset,
-------------- Receive Ports -RX Initialization and Reset Ports ------------
GT0_RXRESETDONE_OUT => rx_rst_done,
--------------------- TX Initialization and Reset Ports --------------------
GT0_GTTXRESET_IN => pll_locked_n_i,
GT0_TXUSERRDY_IN => pll_locked_i,
------------------ Transmit Ports - FPGA TX Interface Ports ----------------
GT0_TXDATA_IN => tx_data_swapped,
GT0_TXUSRCLK_IN => tx_out_clk,
GT0_TXUSRCLK2_IN => tx_out_clk,
------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
GT0_TXCHARISK_IN => tx_is_k_swapped,
--------------- Transmit Ports - TX Configurable Driver Ports --------------
GT0_GTPTXN_OUT => pad_txn_o,
GT0_GTPTXP_OUT => pad_txp_o,
----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
GT0_TXOUTCLK_OUT => tx_out_clk_bufin,
GT0_TXOUTCLKFABRIC_OUT => open,
GT0_TXOUTCLKPCS_OUT => open,
------------- Transmit Ports - TX Initialization and Reset Ports -----------
GT0_TXRESETDONE_OUT => tx_rst_done,
------------------ Transmit Ports - pattern Generator Ports ----------------
GT0_TXPRBSSEL_IN => tx_prbs_sel_i,
--____________________________COMMON PORTS________________________________
----------------- Common Block - GTPE2_COMMON Clocking Ports ---------------
GT0_GTREFCLK0_IN => clk_gtp_i,
-------------------------- Common Block - PLL Ports ------------------------
GT0_PLL1LOCK_OUT => pll_locked_i,
GT0_PLL1LOCKDETCLK_IN => '0',
GT0_PLL1REFCLKLOST_OUT => open,
GT0_PLL1RESET_IN => ready_for_reset
);
U_Bitslide : gtp_bitslide
generic map (
g_simulation => g_simulation,
g_target => ("artix7")
)
port map (
gtp_rst_i => rst_done_n,
gtp_rx_clk_i => rx_rec_clk,
gtp_rx_comma_det_i => rx_comma_det,
gtp_rx_byte_is_aligned_i => rx_byte_is_aligned,
serdes_ready_i => serdes_ready,
gtp_rx_slide_o => rx_slide,
gtp_rx_cdr_rst_o => forced_rx_reset,
bitslide_o => rx_bitslide_o,
synced_o => rx_synced
);
pll_locked_n_i <= not pll_locked_i;
serdes_ready <= not rx_lost_lock and pll_locked_i and tx_rst_done and rx_rst_done;
rst_done <= tx_rst_done and rx_rst_done;
rst_done_n <= not rst_done;
rx_reset <= pll_locked_n_i or forced_rx_reset;
rdy_o <= serdes_ready;
p_gen_rx_outputs : process(rx_rec_clk, rst_done_n)
begin
if(rst_done_n = '1') then
rx_data_o <= (others => '0');
rx_k_o <= (others => '0');
rx_enc_err_o <= '0';
elsif rising_edge(rx_rec_clk) then
if(serdes_ready = '1' and rx_synced = '1') then
rx_data_o <= rx_data_int(7 downto 0) & rx_data_int(15 downto 8);
rx_k_o <= rx_k_int(0) & rx_k_int(1);
rx_enc_err_o <= rx_disp_err(0) or rx_disp_err(1) or rx_code_err(0) or rx_code_err(1);
else
rx_data_o <= (others => '1');
rx_k_o <= (others => '1');
rx_enc_err_o <= '1';
end if;
end if;
end process;
p_gen_tx_disparity : process(tx_out_clk, rst_done_n)
begin
if rising_edge(tx_out_clk) then
if rst_done_n = '1' then
cur_disp <= RD_MINUS;
else
cur_disp <= f_next_8b10b_disparity16(cur_disp, tx_k_i, tx_data_i);
end if;
end if;
end process;
tx_disparity_o <= to_std_logic(cur_disp);
end architecture structure ; -- of wr_gtp_phy_artix7
platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper.vhd deleted 100644 → 0
View file @ cc28eacd
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.4
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : whiterabbitgtp_wrapper.vhd
-- /___/ /\ Timestamp :
-- \ \ / \
-- \___\/\___\
--
--
-- Module WHITERABBITGTP_WRAPPER (a GTP Wrapper)
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of,
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
--***************************** Entity Declaration ****************************
entity WHITERABBITGTP_WRAPPER is
generic
(
-- Simulation attributes
WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
WRAPPER_CLK25_DIVIDER_0 : integer := 5;
WRAPPER_CLK25_DIVIDER_1 : integer := 5;
WRAPPER_PLL_DIVSEL_FB_0 : integer := 2;
WRAPPER_PLL_DIVSEL_FB_1 : integer := 2;
WRAPPER_PLL_DIVSEL_REF_0 : integer := 1;
WRAPPER_PLL_DIVSEL_REF_1 : integer := 1;
WRAPPER_SIMULATION : integer := 0 -- Set to 1 for simulation
);
port
(
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X1_Y0)
------------------------ Loopback and Powerdown Ports ----------------------
TILE0_LOOPBACK0_IN : in std_logic_vector(2 downto 0);
TILE0_LOOPBACK1_IN : in std_logic_vector(2 downto 0);
--------------------------------- PLL Ports --------------------------------
TILE0_CLK00_IN : in std_logic;
TILE0_CLK01_IN : in std_logic;
TILE0_GTPRESET0_IN : in std_logic;
TILE0_GTPRESET1_IN : in std_logic;
TILE0_PLLLKDET0_OUT : out std_logic;
TILE0_RESETDONE0_OUT : out std_logic;
TILE0_RESETDONE1_OUT : out std_logic;
TILE0_REFCLKOUT0_OUT : out std_logic;
TILE0_REFCLKOUT1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE0_RXCHARISK0_OUT : out std_logic;
TILE0_RXCHARISK1_OUT : out std_logic;
TILE0_RXDISPERR0_OUT : out std_logic;
TILE0_RXDISPERR1_OUT : out std_logic;
TILE0_RXNOTINTABLE0_OUT : out std_logic;
TILE0_RXNOTINTABLE1_OUT : out std_logic;
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE0_RXBYTEISALIGNED0_OUT : out std_logic;
TILE0_RXBYTEISALIGNED1_OUT : out std_logic;
TILE0_RXCOMMADET0_OUT : out std_logic;
TILE0_RXCOMMADET1_OUT : out std_logic;
TILE0_RXSLIDE0_IN : in std_logic;
TILE0_RXSLIDE1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
TILE0_RXDATA0_OUT : out std_logic_vector(7 downto 0);
TILE0_RXDATA1_OUT : out std_logic_vector(7 downto 0);
TILE0_RXUSRCLK0_IN : in std_logic;
TILE0_RXUSRCLK1_IN : in std_logic;
TILE0_RXUSRCLK20_IN : in std_logic;
TILE0_RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE0_RXCDRRESET0_IN : in std_logic;
TILE0_RXCDRRESET1_IN : in std_logic;
TILE0_RXN0_IN : in std_logic;
TILE0_RXN1_IN : in std_logic;
TILE0_RXP0_IN : in std_logic;
TILE0_RXP1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
TILE0_GTPCLKFBEAST_OUT : out std_logic_vector(1 downto 0);
TILE0_GTPCLKFBWEST_OUT : out std_logic_vector(1 downto 0);
TILE0_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
TILE0_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE0_TXCHARISK0_IN : in std_logic;
TILE0_TXCHARISK1_IN : in std_logic;
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TILE0_TXENPMAPHASEALIGN0_IN : in std_logic;
TILE0_TXENPMAPHASEALIGN1_IN : in std_logic;
TILE0_TXPMASETPHASE0_IN : in std_logic;
TILE0_TXPMASETPHASE1_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TILE0_TXDATA0_IN : in std_logic_vector(7 downto 0);
TILE0_TXDATA1_IN : in std_logic_vector(7 downto 0);
TILE0_TXUSRCLK0_IN : in std_logic;
TILE0_TXUSRCLK1_IN : in std_logic;
TILE0_TXUSRCLK20_IN : in std_logic;
TILE0_TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE0_TXN0_OUT : out std_logic;
TILE0_TXN1_OUT : out std_logic;
TILE0_TXP0_OUT : out std_logic;
TILE0_TXP1_OUT : out std_logic
);
end WHITERABBITGTP_WRAPPER;
architecture RTL of WHITERABBITGTP_WRAPPER is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of RTL : architecture is "WHITERABBITGTP_WRAPPER,s6_gtpwizard_v1_4,{gtp0_protocol_file=Start_from_scratch,gtp1_protocol_file=Use_GTP0_settings}";
--***************************** Signal Declarations *****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tile0_plllkdet0_i : std_logic;
signal tile0_plllkdet1_i : std_logic;
signal tile0_plllkdet0_i2 : std_logic;
--*************************** Component Declarations **************************
component WHITERABBITGTP_WRAPPER_TILE
generic
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
TILE_CLK25_DIVIDER_0 : integer := 4;
TILE_CLK25_DIVIDER_1 : integer := 4;
TILE_PLL_DIVSEL_FB_0 : integer := 5;
TILE_PLL_DIVSEL_FB_1 : integer := 5;
TILE_PLL_DIVSEL_REF_0 : integer := 2;
TILE_PLL_DIVSEL_REF_1 : integer := 2;
--
TILE_PLL_SOURCE_0 : string := "PLL0";
TILE_PLL_SOURCE_1 : string := "PLL1"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN : in std_logic_vector(2 downto 0);
LOOPBACK1_IN : in std_logic_vector(2 downto 0);
REFCLKOUT0_OUT : out std_logic;
REFCLKOUT1_OUT : out std_logic;
--------------------------------- PLL Ports --------------------------------
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT : out std_logic;
RXCHARISK1_OUT : out std_logic;
RXDISPERR0_OUT : out std_logic;
RXDISPERR1_OUT : out std_logic;
RXNOTINTABLE0_OUT : out std_logic;
RXNOTINTABLE1_OUT : out std_logic;
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0_OUT : out std_logic;
RXBYTEISALIGNED1_OUT : out std_logic;
RXCOMMADET0_OUT : out std_logic;
RXCOMMADET1_OUT : out std_logic;
RXSLIDE0_IN : in std_logic;
RXSLIDE1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT : out std_logic_vector(7 downto 0);
RXDATA1_OUT : out std_logic_vector(7 downto 0);
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET0_IN : in std_logic;
RXCDRRESET1_IN : in std_logic;
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST_OUT : out std_logic_vector(1 downto 0);
GTPCLKFBWEST_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARISK0_IN : in std_logic;
TXCHARISK1_IN : in std_logic;
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXENPMAPHASEALIGN0_IN : in std_logic;
TXENPMAPHASEALIGN1_IN : in std_logic;
TXPMASETPHASE0_IN : in std_logic;
TXPMASETPHASE1_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN : in std_logic_vector(7 downto 0);
TXDATA1_IN : in std_logic_vector(7 downto 0);
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic
);
end component;
--********************************* Main Body of Code**************************
begin
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
simulation : if WRAPPER_SIMULATION = 1 generate
TILE0_PLLLKDET0_OUT <= tile0_plllkdet0_i2;
process
begin
wait until tile0_plllkdet0_i'event;
if(tile0_plllkdet0_i = '1') then
tile0_plllkdet0_i2 <= '1' after 100 ns;
else
tile0_plllkdet0_i2 <= tile0_plllkdet0_i;
end if;
end process;
end generate simulation;
implementation : if WRAPPER_SIMULATION = 0 generate
TILE0_PLLLKDET0_OUT <= tile0_plllkdet0_i;
end generate implementation;
--------------------------- Tile Instances -------------------------------
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X1_Y0)
tile0_whiterabbitgtp_wrapper_i : WHITERABBITGTP_WRAPPER_TILE
generic map
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP => WRAPPER_SIM_GTPRESET_SPEEDUP,
TILE_CLK25_DIVIDER_0 => WRAPPER_CLK25_DIVIDER_0,
TILE_CLK25_DIVIDER_1 => WRAPPER_CLK25_DIVIDER_1,
TILE_PLL_DIVSEL_FB_0 => WRAPPER_PLL_DIVSEL_FB_0,
TILE_PLL_DIVSEL_FB_1 => WRAPPER_PLL_DIVSEL_FB_1,
TILE_PLL_DIVSEL_REF_0 => WRAPPER_PLL_DIVSEL_REF_0,
TILE_PLL_DIVSEL_REF_1 => WRAPPER_PLL_DIVSEL_REF_1,
--
TILE_PLL_SOURCE_0 => "PLL0",
TILE_PLL_SOURCE_1 => "PLL0"
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN => TILE0_LOOPBACK0_IN,
LOOPBACK1_IN => TILE0_LOOPBACK1_IN,
--------------------------------- PLL Ports --------------------------------
REFCLKOUT1_OUT => REFCLKOUT1_OUT,
REFCLKOUT0_OUT => REFCLKOUT0_OUT,
CLK00_IN => TILE0_CLK00_IN,
CLK01_IN => TILE0_CLK01_IN,
GTPRESET0_IN => TILE0_GTPRESET0_IN,
GTPRESET1_IN => TILE0_GTPRESET1_IN,
PLLLKDET0_OUT => tile0_plllkdet0_i,
PLLLKDET1_OUT => tile0_plllkdet1_i,
RESETDONE0_OUT => TILE0_RESETDONE0_OUT,
RESETDONE1_OUT => TILE0_RESETDONE1_OUT,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT => TILE0_RXCHARISK0_OUT,
RXCHARISK1_OUT => TILE0_RXCHARISK1_OUT,
RXDISPERR0_OUT => TILE0_RXDISPERR0_OUT,
RXDISPERR1_OUT => TILE0_RXDISPERR1_OUT,
RXNOTINTABLE0_OUT => TILE0_RXNOTINTABLE0_OUT,
RXNOTINTABLE1_OUT => TILE0_RXNOTINTABLE1_OUT,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0_OUT => TILE0_RXBYTEISALIGNED0_OUT,
RXBYTEISALIGNED1_OUT => TILE0_RXBYTEISALIGNED1_OUT,
RXCOMMADET0_OUT => TILE0_RXCOMMADET0_OUT,
RXCOMMADET1_OUT => TILE0_RXCOMMADET1_OUT,
RXSLIDE0_IN => TILE0_RXSLIDE0_IN,
RXSLIDE1_IN => TILE0_RXSLIDE1_IN,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT => TILE0_RXDATA0_OUT,
RXDATA1_OUT => TILE0_RXDATA1_OUT,
RXUSRCLK0_IN => TILE0_RXUSRCLK0_IN,
RXUSRCLK1_IN => TILE0_RXUSRCLK1_IN,
RXUSRCLK20_IN => TILE0_RXUSRCLK20_IN,
RXUSRCLK21_IN => TILE0_RXUSRCLK21_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET0_IN => TILE0_RXCDRRESET0_IN,
RXCDRRESET1_IN => TILE0_RXCDRRESET1_IN,
RXN0_IN => TILE0_RXN0_IN,
RXN1_IN => TILE0_RXN1_IN,
RXP0_IN => TILE0_RXP0_IN,
RXP1_IN => TILE0_RXP1_IN,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST_OUT => TILE0_GTPCLKFBEAST_OUT,
GTPCLKFBWEST_OUT => TILE0_GTPCLKFBWEST_OUT,
GTPCLKOUT0_OUT => TILE0_GTPCLKOUT0_OUT,
GTPCLKOUT1_OUT => TILE0_GTPCLKOUT1_OUT,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARISK0_IN => TILE0_TXCHARISK0_IN,
TXCHARISK1_IN => TILE0_TXCHARISK1_IN,
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXENPMAPHASEALIGN0_IN => TILE0_TXENPMAPHASEALIGN0_IN,
TXENPMAPHASEALIGN1_IN => TILE0_TXENPMAPHASEALIGN1_IN,
TXPMASETPHASE0_IN => TILE0_TXPMASETPHASE0_IN,
TXPMASETPHASE1_IN => TILE0_TXPMASETPHASE1_IN,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN => TILE0_TXDATA0_IN,
TXDATA1_IN => TILE0_TXDATA1_IN,
TXUSRCLK0_IN => TILE0_TXUSRCLK0_IN,
TXUSRCLK1_IN => TILE0_TXUSRCLK1_IN,
TXUSRCLK20_IN => TILE0_TXUSRCLK20_IN,
TXUSRCLK21_IN => TILE0_TXUSRCLK21_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT => TILE0_TXN0_OUT,
TXN1_OUT => TILE0_TXN1_OUT,
TXP0_OUT => TILE0_TXP0_OUT,
TXP1_OUT => TILE0_TXP1_OUT
);
end RTL;
platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile_spartan6.vhd deleted 100644 → 0
View file @ cc28eacd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
entity WHITERABBITGTP_WRAPPER_TILE is
generic
(
TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
TILE_CLK25_DIVIDER_0 : integer := 4;
TILE_CLK25_DIVIDER_1 : integer := 4;
TILE_PLL_DIVSEL_FB_0 : integer := 5;
TILE_PLL_DIVSEL_FB_1 : integer := 5;
TILE_PLL_DIVSEL_REF_0 : integer := 2;
TILE_PLL_DIVSEL_REF_1 : integer := 2;
TILE_PLL_SOURCE_0 : string := "PLL0";
TILE_PLL_SOURCE_1 : string := "PLL1"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN : in std_logic_vector(2 downto 0);
LOOPBACK1_IN : in std_logic_vector(2 downto 0);
--------------------------------- PLL Ports --------------------------------
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
CLK10_IN : in std_logic;
CLK11_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT : out std_logic;
RXCHARISK1_OUT : out std_logic;
RXDISPERR0_OUT : out std_logic;
RXDISPERR1_OUT : out std_logic;
RXNOTINTABLE0_OUT : out std_logic;
RXNOTINTABLE1_OUT : out std_logic;
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0_OUT : out std_logic;
RXBYTEISALIGNED1_OUT : out std_logic;
RXCOMMADET0_OUT : out std_logic;
RXCOMMADET1_OUT : out std_logic;
RXSLIDE0_IN : in std_logic;
RXSLIDE1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT : out std_logic_vector(7 downto 0);
RXDATA1_OUT : out std_logic_vector(7 downto 0);
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET0_IN : in std_logic;
RXCDRRESET1_IN : in std_logic;
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST_OUT : out std_logic_vector(1 downto 0);
GTPCLKFBWEST_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARISK0_IN : in std_logic;
TXCHARISK1_IN : in std_logic;
TXRUNDISP0_OUT : out std_logic_vector(3 downto 0);
TXRUNDISP1_OUT : out std_logic_vector(3 downto 0);
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXENPMAPHASEALIGN0_IN : in std_logic;
TXENPMAPHASEALIGN1_IN : in std_logic;
TXPMASETPHASE0_IN : in std_logic;
TXPMASETPHASE1_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN : in std_logic_vector(7 downto 0);
TXDATA1_IN : in std_logic_vector(7 downto 0);
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic
);
end WHITERABBITGTP_WRAPPER_TILE;
architecture RTL of WHITERABBITGTP_WRAPPER_TILE is
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
-- RX Datapath signals
signal rxdata0_i : std_logic_vector(31 downto 0);
signal rxchariscomma0_float_i : std_logic_vector(2 downto 0);
signal rxcharisk0_float_i : std_logic_vector(2 downto 0);
signal rxdisperr0_float_i : std_logic_vector(2 downto 0);
signal rxnotintable0_float_i : std_logic_vector(2 downto 0);
signal rxrundisp0_float_i : std_logic_vector(2 downto 0);
-- TX Datapath signals
signal txdata0_i : std_logic_vector(31 downto 0);
signal txkerr0_float_i : std_logic_vector(2 downto 0);
signal txrundisp0_float_i : std_logic_vector(2 downto 0);
-- RX Datapath signals
signal rxdata1_i : std_logic_vector(31 downto 0);
signal rxchariscomma1_float_i : std_logic_vector(2 downto 0);
signal rxcharisk1_float_i : std_logic_vector(2 downto 0);
signal rxdisperr1_float_i : std_logic_vector(2 downto 0);
signal rxnotintable1_float_i : std_logic_vector(2 downto 0);
signal rxrundisp1_float_i : std_logic_vector(2 downto 0);
-- TX Datapath signals
signal txdata1_i : std_logic_vector(31 downto 0);
signal txkerr1_float_i : std_logic_vector(2 downto 0);
signal txrundisp1_float_i : std_logic_vector(2 downto 0);
--******************************** Main Body of Code***************************
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
------------------- GTP Datapath byte mapping -----------------
RXDATA0_OUT <= rxdata0_i(7 downto 0);
txdata0_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA0_IN);
RXDATA1_OUT <= rxdata1_i(7 downto 0);
txdata1_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA1_IN);
----------------------------- GTPA1_DUAL Instance --------------------------
gtpa1_dual_i : GTPA1_DUAL
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => (true),
SIM_TX_ELEC_IDLE_LEVEL => ("X"),
SIM_VERSION => ("2.0"),
SIM_REFCLK0_SOURCE => ("000"),
SIM_REFCLK1_SOURCE => ("000"),
SIM_GTPRESET_SPEEDUP => (TILE_SIM_GTPRESET_SPEEDUP),
CLK25_DIVIDER_0 => (TILE_CLK25_DIVIDER_0),
CLK25_DIVIDER_1 => (TILE_CLK25_DIVIDER_1),
PLL_DIVSEL_FB_0 => (TILE_PLL_DIVSEL_FB_0),
PLL_DIVSEL_FB_1 => (TILE_PLL_DIVSEL_FB_1),
PLL_DIVSEL_REF_0 => (TILE_PLL_DIVSEL_REF_0),
PLL_DIVSEL_REF_1 => (TILE_PLL_DIVSEL_REF_1),
--PLL Attributes
CLKINDC_B_0 => (true),
CLKRCV_TRST_0 => (true),
OOB_CLK_DIVIDER_0 => (4),
PLL_COM_CFG_0 => (x"21680a"),
PLL_CP_CFG_0 => (x"00"),
PLL_RXDIVSEL_OUT_0 => (2),
PLL_SATA_0 => (false),
PLL_SOURCE_0 => (TILE_PLL_SOURCE_0),
PLL_TXDIVSEL_OUT_0 => (2),
PLLLKDET_CFG_0 => ("111"),
--
CLKINDC_B_1 => (true),
CLKRCV_TRST_1 => (true),
OOB_CLK_DIVIDER_1 => (4),
PLL_COM_CFG_1 => (x"21680a"),
PLL_CP_CFG_1 => (x"00"),
PLL_RXDIVSEL_OUT_1 => (2),
PLL_SATA_1 => (false),
PLL_SOURCE_1 => (TILE_PLL_SOURCE_1),
PLL_TXDIVSEL_OUT_1 => (2),
PLLLKDET_CFG_1 => ("111"),
PMA_COM_CFG_EAST => (x"000008000"),
PMA_COM_CFG_WEST => (x"000008000"),
TST_ATTR_0 => (x"00000000"),
TST_ATTR_1 => (x"00000000"),
--TX Interface Attributes
CLK_OUT_GTP_SEL_0 => ("REFCLKPLL0"),
TX_TDCC_CFG_0 => ("00"),
CLK_OUT_GTP_SEL_1 => ("REFCLKPLL1"),
TX_TDCC_CFG_1 => ("00"),
--TX Buffer and Phase Alignment Attributes
PMA_TX_CFG_0 => (x"80082"),
TX_BUFFER_USE_0 => (false),
TX_XCLK_SEL_0 => ("TXUSR"),
TXRX_INVERT_0 => ("111"),
PMA_TX_CFG_1 => (x"80082"),
TX_BUFFER_USE_1 => (false),
TX_XCLK_SEL_1 => ("TXUSR"),
TXRX_INVERT_1 => ("111"),
--TX Driver and OOB signalling Attributes
CM_TRIM_0 => ("00"),
TX_IDLE_DELAY_0 => ("011"),
CM_TRIM_1 => ("00"),
TX_IDLE_DELAY_1 => ("011"),
--TX PIPE/SATA Attributes
COM_BURST_VAL_0 => ("1111"),
COM_BURST_VAL_1 => ("1111"),
--RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
AC_CAP_DIS_0 => (true),
OOBDETECT_THRESHOLD_0 => ("110"),
PMA_CDR_SCAN_0 => (x"6404040"),
PMA_RX_CFG_0 => (x"05ce048"),
PMA_RXSYNC_CFG_0 => (x"00"),
RCV_TERM_GND_0 => (false),
RCV_TERM_VTTRX_0 => (true),
RXEQ_CFG_0 => ("01111011"),
TERMINATION_CTRL_0 => ("10100"),
TERMINATION_OVRD_0 => (false),
TX_DETECT_RX_CFG_0 => (x"1832"),
AC_CAP_DIS_1 => (true),
OOBDETECT_THRESHOLD_1 => ("110"),
PMA_CDR_SCAN_1 => (x"6404040"),
PMA_RX_CFG_1 => (x"05ce048"),
PMA_RXSYNC_CFG_1 => (x"00"),
RCV_TERM_GND_1 => (false),
RCV_TERM_VTTRX_1 => (true),
RXEQ_CFG_1 => ("01111011"),
TERMINATION_CTRL_1 => ("10100"),
TERMINATION_OVRD_1 => (false),
TX_DETECT_RX_CFG_1 => (x"1832"),
--PRBS Detection Attributes
RXPRBSERR_LOOPBACK_0 => ('0'),
RXPRBSERR_LOOPBACK_1 => ('0'),
--Comma Detection and Alignment Attributes
ALIGN_COMMA_WORD_0 => (1),
COMMA_10B_ENABLE_0 => ("1111111111"),
DEC_MCOMMA_DETECT_0 => (false),
DEC_PCOMMA_DETECT_0 => (false),
DEC_VALID_COMMA_ONLY_0 => (true),
MCOMMA_10B_VALUE_0 => ("1010000011"),
MCOMMA_DETECT_0 => (true),
PCOMMA_10B_VALUE_0 => ("0101111100"),
PCOMMA_DETECT_0 => (true),
RX_SLIDE_MODE_0 => ("PCS"),
ALIGN_COMMA_WORD_1 => (1),
COMMA_10B_ENABLE_1 => ("1111111111"),
DEC_MCOMMA_DETECT_1 => (false),
DEC_PCOMMA_DETECT_1 => (false),
DEC_VALID_COMMA_ONLY_1 => (true),
MCOMMA_10B_VALUE_1 => ("1010000011"),
MCOMMA_DETECT_1 => (true),
PCOMMA_10B_VALUE_1 => ("0101111100"),
PCOMMA_DETECT_1 => (true),
RX_SLIDE_MODE_1 => ("PCS"),
--RX Loss-of-sync State Machine Attributes
RX_LOS_INVALID_INCR_0 => (8),
RX_LOS_THRESHOLD_0 => (128),
RX_LOSS_OF_SYNC_FSM_0 => (false),
RX_LOS_INVALID_INCR_1 => (8),
RX_LOS_THRESHOLD_1 => (128),
RX_LOSS_OF_SYNC_FSM_1 => (false),
--RX Elastic Buffer and Phase alignment Attributes
RX_BUFFER_USE_0 => (true),
RX_EN_IDLE_RESET_BUF_0 => (true),
RX_IDLE_HI_CNT_0 => ("1000"),
RX_IDLE_LO_CNT_0 => ("0000"),
RX_XCLK_SEL_0 => ("RXREC"),
RX_BUFFER_USE_1 => (true),
RX_EN_IDLE_RESET_BUF_1 => (true),
RX_IDLE_HI_CNT_1 => ("1000"),
RX_IDLE_LO_CNT_1 => ("0000"),
RX_XCLK_SEL_1 => ("RXREC"),
--Clock Correction Attributes
CLK_COR_ADJ_LEN_0 => (1),
CLK_COR_DET_LEN_0 => (1),
CLK_COR_INSERT_IDLE_FLAG_0 => (false),
CLK_COR_KEEP_IDLE_0 => (false),
CLK_COR_MAX_LAT_0 => (18),
CLK_COR_MIN_LAT_0 => (16),
CLK_COR_PRECEDENCE_0 => (true),
CLK_COR_REPEAT_WAIT_0 => (0),
CLK_COR_SEQ_1_1_0 => ("0100000000"),
CLK_COR_SEQ_1_2_0 => ("0000000000"),
CLK_COR_SEQ_1_3_0 => ("0000000000"),
CLK_COR_SEQ_1_4_0 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_1_0 => ("0100000000"),
CLK_COR_SEQ_2_2_0 => ("0000000000"),
CLK_COR_SEQ_2_3_0 => ("0000000000"),
CLK_COR_SEQ_2_4_0 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_USE_0 => (false),
CLK_CORRECT_USE_0 => (false),
RX_DECODE_SEQ_MATCH_0 => (true),
CLK_COR_ADJ_LEN_1 => (1),
CLK_COR_DET_LEN_1 => (1),
CLK_COR_INSERT_IDLE_FLAG_1 => (false),
CLK_COR_KEEP_IDLE_1 => (false),
CLK_COR_MAX_LAT_1 => (18),
CLK_COR_MIN_LAT_1 => (16),
CLK_COR_PRECEDENCE_1 => (true),
CLK_COR_REPEAT_WAIT_1 => (0),
CLK_COR_SEQ_1_1_1 => ("0100000000"),
CLK_COR_SEQ_1_2_1 => ("0000000000"),
CLK_COR_SEQ_1_3_1 => ("0000000000"),
CLK_COR_SEQ_1_4_1 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_1_1 => ("0100000000"),
CLK_COR_SEQ_2_2_1 => ("0000000000"),
CLK_COR_SEQ_2_3_1 => ("0000000000"),
CLK_COR_SEQ_2_4_1 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_USE_1 => (false),
CLK_CORRECT_USE_1 => (false),
RX_DECODE_SEQ_MATCH_1 => (true),
--Channel Bonding Attributes
CHAN_BOND_1_MAX_SKEW_0 => (1),
CHAN_BOND_2_MAX_SKEW_0 => (1),
CHAN_BOND_KEEP_ALIGN_0 => (false),
CHAN_BOND_SEQ_1_1_0 => ("0000000000"),
CHAN_BOND_SEQ_1_2_0 => ("0000000000"),
CHAN_BOND_SEQ_1_3_0 => ("0000000000"),
CHAN_BOND_SEQ_1_4_0 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_1_0 => ("0000000000"),
CHAN_BOND_SEQ_2_2_0 => ("0000000000"),
CHAN_BOND_SEQ_2_3_0 => ("0000000000"),
CHAN_BOND_SEQ_2_4_0 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_USE_0 => (false),
CHAN_BOND_SEQ_LEN_0 => (1),
RX_EN_MODE_RESET_BUF_0 => (true),
CHAN_BOND_1_MAX_SKEW_1 => (1),
CHAN_BOND_2_MAX_SKEW_1 => (1),
CHAN_BOND_KEEP_ALIGN_1 => (false),
CHAN_BOND_SEQ_1_1_1 => ("0000000000"),
CHAN_BOND_SEQ_1_2_1 => ("0000000000"),
CHAN_BOND_SEQ_1_3_1 => ("0000000000"),
CHAN_BOND_SEQ_1_4_1 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_1_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_3_1 => ("0000000000"),
CHAN_BOND_SEQ_2_4_1 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_USE_1 => (false),
CHAN_BOND_SEQ_LEN_1 => (1),
RX_EN_MODE_RESET_BUF_1 => (true),
--RX PCI Express Attributes
CB2_INH_CC_PERIOD_0 => (8),
CDR_PH_ADJ_TIME_0 => ("01010"),
PCI_EXPRESS_MODE_0 => (false),
RX_EN_IDLE_HOLD_CDR_0 => (false),
RX_EN_IDLE_RESET_FR_0 => (true),
RX_EN_IDLE_RESET_PH_0 => (true),
RX_STATUS_FMT_0 => ("PCIE"),
TRANS_TIME_FROM_P2_0 => (x"03c"),
TRANS_TIME_NON_P2_0 => (x"19"),
TRANS_TIME_TO_P2_0 => (x"064"),
CB2_INH_CC_PERIOD_1 => (8),
CDR_PH_ADJ_TIME_1 => ("01010"),
PCI_EXPRESS_MODE_1 => (false),
RX_EN_IDLE_HOLD_CDR_1 => (false),
RX_EN_IDLE_RESET_FR_1 => (true),
RX_EN_IDLE_RESET_PH_1 => (true),
RX_STATUS_FMT_1 => ("PCIE"),
TRANS_TIME_FROM_P2_1 => (x"03c"),
TRANS_TIME_NON_P2_1 => (x"19"),
TRANS_TIME_TO_P2_1 => (x"064"),
--RX SATA Attributes
SATA_BURST_VAL_0 => ("100"),
SATA_IDLE_VAL_0 => ("100"),
SATA_MAX_BURST_0 => (9),
SATA_MAX_INIT_0 => (27),
SATA_MAX_WAKE_0 => (9),
SATA_MIN_BURST_0 => (5),
SATA_MIN_INIT_0 => (15),
SATA_MIN_WAKE_0 => (5),
SATA_BURST_VAL_1 => ("100"),
SATA_IDLE_VAL_1 => ("100"),
SATA_MAX_BURST_1 => (9),
SATA_MAX_INIT_1 => (27),
SATA_MAX_WAKE_1 => (9),
SATA_MIN_BURST_1 => (5),
SATA_MIN_INIT_1 => (15),
SATA_MIN_WAKE_1 => (5)
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0 => LOOPBACK0_IN,
LOOPBACK1 => LOOPBACK1_IN,
RXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
RXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
--------------------------------- PLL Ports --------------------------------
CLK00 => CLK00_IN,
CLK01 => CLK01_IN,
CLK10 => CLK10_IN,
CLK11 => CLK11_IN,
CLKINEAST0 => tied_to_ground_i,
CLKINEAST1 => tied_to_ground_i,
CLKINWEST0 => tied_to_ground_i,
CLKINWEST1 => tied_to_ground_i,
GCLK00 => tied_to_ground_i,
GCLK01 => tied_to_ground_i,
GCLK10 => tied_to_ground_i,
GCLK11 => tied_to_ground_i,
GTPRESET0 => GTPRESET0_IN,
GTPRESET1 => GTPRESET1_IN,
GTPTEST0 => "00010000",
GTPTEST1 => "00010000",
INTDATAWIDTH0 => tied_to_vcc_i,
INTDATAWIDTH1 => tied_to_vcc_i,
PLLCLK00 => tied_to_ground_i,
PLLCLK01 => tied_to_ground_i,
PLLCLK10 => tied_to_ground_i,
PLLCLK11 => tied_to_ground_i,
PLLLKDET0 => PLLLKDET0_OUT,
PLLLKDET1 => PLLLKDET1_OUT,
PLLLKDETEN0 => tied_to_vcc_i,
PLLLKDETEN1 => tied_to_vcc_i,
PLLPOWERDOWN0 => tied_to_ground_i,
PLLPOWERDOWN1 => tied_to_ground_i,
REFCLKOUT0 => open,
REFCLKOUT1 => open,
REFCLKPLL0 => open,
REFCLKPLL1 => open,
REFCLKPWRDNB0 => tied_to_vcc_i,
REFCLKPWRDNB1 => tied_to_vcc_i,
REFSELDYPLL0 => tied_to_ground_vec_i(2 downto 0),
REFSELDYPLL1 => tied_to_ground_vec_i(2 downto 0),
RESETDONE0 => RESETDONE0_OUT,
RESETDONE1 => RESETDONE1_OUT,
TSTCLK0 => tied_to_ground_i,
TSTCLK1 => tied_to_ground_i,
TSTIN0 => tied_to_ground_vec_i(11 downto 0),
TSTIN1 => tied_to_ground_vec_i(11 downto 0),
TSTOUT0 => open,
TSTOUT1 => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0 => open,
RXCHARISCOMMA1 => open,
RXCHARISK0(3 downto 1) => rxcharisk0_float_i,
RXCHARISK0(0) => RXCHARISK0_OUT,
RXCHARISK1(3 downto 1) => rxcharisk1_float_i,
RXCHARISK1(0) => RXCHARISK1_OUT,
RXDEC8B10BUSE0 => tied_to_vcc_i,
RXDEC8B10BUSE1 => tied_to_vcc_i,
RXDISPERR0(3 downto 1) => rxdisperr0_float_i,
RXDISPERR0(0) => RXDISPERR0_OUT,
RXDISPERR1(3 downto 1) => rxdisperr1_float_i,
RXDISPERR1(0) => RXDISPERR1_OUT,
RXNOTINTABLE0(3 downto 1) => rxnotintable0_float_i,
RXNOTINTABLE0(0) => RXNOTINTABLE0_OUT,
RXNOTINTABLE1(3 downto 1) => rxnotintable1_float_i,
RXNOTINTABLE1(0) => RXNOTINTABLE1_OUT,
RXRUNDISP0 => open,
RXRUNDISP1 => open,
USRCODEERR0 => tied_to_ground_i,
USRCODEERR1 => tied_to_ground_i,
---------------------- Receive Ports - Channel Bonding ---------------------
RXCHANBONDSEQ0 => open,
RXCHANBONDSEQ1 => open,
RXCHANISALIGNED0 => open,
RXCHANISALIGNED1 => open,
RXCHANREALIGN0 => open,
RXCHANREALIGN1 => open,
RXCHBONDI => tied_to_ground_vec_i(2 downto 0),
RXCHBONDMASTER0 => tied_to_ground_i,
RXCHBONDMASTER1 => tied_to_ground_i,
RXCHBONDO => open,
RXCHBONDSLAVE0 => tied_to_ground_i,
RXCHBONDSLAVE1 => tied_to_ground_i,
RXENCHANSYNC0 => tied_to_ground_i,
RXENCHANSYNC1 => tied_to_ground_i,
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0 => open,
RXCLKCORCNT1 => open,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0 => RXBYTEISALIGNED0_OUT,
RXBYTEISALIGNED1 => RXBYTEISALIGNED1_OUT,
RXBYTEREALIGN0 => open,
RXBYTEREALIGN1 => open,
RXCOMMADET0 => RXCOMMADET0_OUT,
RXCOMMADET1 => RXCOMMADET1_OUT,
RXCOMMADETUSE0 => tied_to_vcc_i,
RXCOMMADETUSE1 => tied_to_vcc_i,
RXENMCOMMAALIGN0 => tied_to_ground_i,
RXENMCOMMAALIGN1 => tied_to_ground_i,
RXENPCOMMAALIGN0 => tied_to_ground_i,
RXENPCOMMAALIGN1 => tied_to_ground_i,
RXSLIDE0 => RXSLIDE0_IN,
RXSLIDE1 => RXSLIDE1_IN,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET0 => tied_to_ground_i,
PRBSCNTRESET1 => tied_to_ground_i,
RXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
RXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
RXPRBSERR0 => open,
RXPRBSERR1 => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0 => rxdata0_i,
RXDATA1 => rxdata1_i,
RXDATAWIDTH0 => "00",
RXDATAWIDTH1 => "00",
RXRECCLK0 => open,
RXRECCLK1 => open,
RXRESET0 => tied_to_ground_i,
RXRESET1 => tied_to_ground_i,
RXUSRCLK0 => RXUSRCLK0_IN,
RXUSRCLK1 => RXUSRCLK1_IN,
RXUSRCLK20 => RXUSRCLK20_IN,
RXUSRCLK21 => RXUSRCLK21_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0 => tied_to_ground_i,
GATERXELECIDLE1 => tied_to_ground_i,
IGNORESIGDET0 => tied_to_ground_i,
IGNORESIGDET1 => tied_to_ground_i,
RCALINEAST => tied_to_ground_vec_i(4 downto 0),
RCALINWEST => tied_to_ground_vec_i(4 downto 0),
RCALOUTEAST => open,
RCALOUTWEST => open,
RXCDRRESET0 => RXCDRRESET0_IN,
RXCDRRESET1 => RXCDRRESET1_IN,
RXELECIDLE0 => open,
RXELECIDLE1 => open,
RXEQMIX0 => "00",
RXEQMIX1 => "00",
RXN0 => RXN0_IN,
RXN1 => RXN1_IN,
RXP0 => RXP0_IN,
RXP1 => RXP1_IN,
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXBUFRESET0 => tied_to_ground_i,
RXBUFRESET1 => tied_to_ground_i,
RXBUFSTATUS0 => open,
RXBUFSTATUS1 => open,
RXENPMAPHASEALIGN0 => tied_to_ground_i,
RXENPMAPHASEALIGN1 => tied_to_ground_i,
RXPMASETPHASE0 => tied_to_ground_i,
RXPMASETPHASE1 => tied_to_ground_i,
RXSTATUS0 => open,
RXSTATUS1 => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0 => open,
RXLOSSOFSYNC1 => open,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0 => open,
PHYSTATUS1 => open,
RXVALID0 => open,
RXVALID1 => open,
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0 => tied_to_ground_i,
RXPOLARITY1 => tied_to_ground_i,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(7 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DRDY => open,
DRPDO => open,
DWE => tied_to_ground_i,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST => GTPCLKFBEAST_OUT,
GTPCLKFBSEL0EAST => "10",
GTPCLKFBSEL0WEST => "00",
GTPCLKFBSEL1EAST => "11",
GTPCLKFBSEL1WEST => "01",
GTPCLKFBWEST => GTPCLKFBWEST_OUT,
GTPCLKOUT0 => GTPCLKOUT0_OUT,
GTPCLKOUT1 => GTPCLKOUT1_OUT,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXBYPASS8B10B0 => tied_to_ground_vec_i(3 downto 0),
TXBYPASS8B10B1 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE0 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE1 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPVAL0 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPVAL1 => tied_to_ground_vec_i(3 downto 0),
TXCHARISK0(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARISK0(0) => TXCHARISK0_IN,
TXCHARISK1(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARISK1(0) => TXCHARISK1_IN,
TXENC8B10BUSE0 => tied_to_vcc_i,
TXENC8B10BUSE1 => tied_to_vcc_i,
TXKERR0 => open,
TXKERR1 => open,
TXRUNDISP0 => TXRUNDISP0_OUT,
TXRUNDISP1 => TXRUNDISP1_OUT,
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXBUFSTATUS0 => open,
TXBUFSTATUS1 => open,
TXENPMAPHASEALIGN0 => TXENPMAPHASEALIGN0_IN,
TXENPMAPHASEALIGN1 => TXENPMAPHASEALIGN1_IN,
TXPMASETPHASE0 => TXPMASETPHASE0_IN,
TXPMASETPHASE1 => TXPMASETPHASE1_IN,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0 => txdata0_i,
TXDATA1 => txdata1_i,
TXDATAWIDTH0 => "00",
TXDATAWIDTH1 => "00",
TXOUTCLK0 => open,
TXOUTCLK1 => open,
TXRESET0 => tied_to_ground_i,
TXRESET1 => tied_to_ground_i,
TXUSRCLK0 => TXUSRCLK0_IN,
TXUSRCLK1 => TXUSRCLK1_IN,
TXUSRCLK20 => TXUSRCLK20_IN,
TXUSRCLK21 => TXUSRCLK21_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXBUFDIFFCTRL0 => "101",
TXBUFDIFFCTRL1 => "101",
TXDIFFCTRL0 => "0110",
TXDIFFCTRL1 => "0110",
TXINHIBIT0 => tied_to_ground_i,
TXINHIBIT1 => tied_to_ground_i,
TXN0 => TXN0_OUT,
TXN1 => TXN1_OUT,
TXP0 => TXP0_OUT,
TXP1 => TXP1_OUT,
TXPREEMPHASIS0 => "000",
TXPREEMPHASIS1 => "000",
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
TXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
TXPRBSFORCEERR0 => tied_to_ground_i,
TXPRBSFORCEERR1 => tied_to_ground_i,
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY0 => tied_to_ground_i,
TXPOLARITY1 => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0 => tied_to_ground_i,
TXDETECTRX1 => tied_to_ground_i,
TXELECIDLE0 => tied_to_ground_i,
TXELECIDLE1 => tied_to_ground_i,
TXPDOWNASYNCH0 => tied_to_ground_i,
TXPDOWNASYNCH1 => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
TXCOMSTART0 => tied_to_ground_i,
TXCOMSTART1 => tied_to_ground_i,
TXCOMTYPE0 => tied_to_ground_i,
TXCOMTYPE1 => tied_to_ground_i
);
end RTL;
platform/xilinx/wr_gtp_phy/wr_gtp_phy_spec.vhd deleted 100644 → 0
View file @ cc28eacd
library ieee;
use ieee.std_logic_1164.all;
entity wr_gtp_phy_spec_wrapper is
generic (
g_simulation : integer := 0);
port(
sfp_ref_clk_i : in std_logic;
sfp_ref_clk_o : out std_logic;
sfp_tx_data_i : in std_logic_vector(7 downto 0);
sfp_tx_k_i : in std_logic;
sfp_tx_disparity_o : out std_logic;
sfp_tx_enc_err_o : out std_logic;
sfp_rx_rbclk_o : out std_logic;
sfp_rx_data_o : out std_logic_vector(7 downto 0);
sfp_rx_k_o : out std_logic;
sfp_rx_enc_err_o : out std_logic;
sfp_rx_bitslide_o : out std_logic_vector(3 downto 0);
sfp_rst_i : in std_logic;
sfp_loopen_i : in std_logic;
sfp_txn_o : out std_logic;
sfp_txp_o : out std_logic;
sfp_rxn_i : in std_logic;
sfp_rxp_i : in std_logic;
sata0_ref_clk_i : in std_logic;
sata0_ref_clk_o : out std_logic;
sata0_tx_data_i : in std_logic_vector(7 downto 0);
sata0_tx_k_i : in std_logic;
sata0_tx_disparity_o : out std_logic;
sata0_tx_enc_err_o : out std_logic;
sata0_rx_rbclk_o : out std_logic;
sata0_rx_data_o : out std_logic_vector(7 downto 0);
sata0_rx_k_o : out std_logic;
sata0_rx_enc_err_o : out std_logic;
sata0_rx_bitslide_o : out std_logic_vector(3 downto 0);
sata0_rst_i : in std_logic;
sata0_loopen_i : in std_logic;
sata0_txn_o : out std_logic;
sata0_txp_o : out std_logic;
sata0_rxn_i : in std_logic;
sata0_rxp_i : in std_logic;
sata1_ref_clk_i : in std_logic;
sata1_ref_clk_o : out std_logic;
sata1_tx_data_i : in std_logic_vector(7 downto 0);
sata1_tx_k_i : in std_logic;
sata1_tx_disparity_o : out std_logic;
sata1_tx_enc_err_o : out std_logic;
sata1_rx_rbclk_o : out std_logic;
sata1_rx_data_o : out std_logic_vector(7 downto 0);
sata1_rx_k_o : out std_logic;
sata1_rx_enc_err_o : out std_logic;
sata1_rx_bitslide_o : out std_logic_vector(3 downto 0);
sata1_rst_i : in std_logic;
sata1_loopen_i : in std_logic;
sata1_txn_o : out std_logic;
sata1_txp_o : out std_logic;
sata1_rxn_i : in std_logic;
sata1_rxp_i : in std_logic;
fmc_ref_clk_i : in std_logic;
fmc_ref_clk_o : out std_logic;
fmc_tx_data_i : in std_logic_vector(7 downto 0);
fmc_tx_k_i : in std_logic;
fmc_tx_disparity_o : out std_logic;
fmc_tx_enc_err_o : out std_logic;
fmc_rx_rbclk_o : out std_logic;
fmc_rx_data_o : out std_logic_vector(7 downto 0);
fmc_rx_k_o : out std_logic;
fmc_rx_enc_err_o : out std_logic;
fmc_rx_bitslide_o : out std_logic_vector(3 downto 0);
fmc_rst_i : in std_logic;
fmc_loopen_i : in std_logic;
fmc_txn_o : out std_logic;
fmc_txp_o : out std_logic;
fmc_rxn_i : in std_logic;
fmc_rxp_i : in std_logic
);
end wr_gtp_phy_spec_wrapper;
architecture rtl of wr_gtp_phy_spec_wrapper is
component wr_gtp_phy_spartan6
generic (
g_simulation : integer);
port (
ch0_ref_clk_i : in std_logic;
ch0_ref_clk_o : out std_logic;
ch0_tx_data_i : in std_logic_vector(7 downto 0);
ch0_tx_k_i : in std_logic;
ch0_tx_disparity_o : out std_logic;
ch0_tx_enc_err_o : out std_logic;
ch0_rx_rbclk_o : out std_logic;
ch0_rx_data_o : out std_logic_vector(7 downto 0);
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic;
ch0_loopen_i : in std_logic;
ch1_ref_clk_i : in std_logic;
ch1_ref_clk_o : out std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
ch1_tx_disparity_o : out std_logic;
ch1_tx_enc_err_o : out std_logic;
ch1_rx_data_o : out std_logic_vector(7 downto 0);
ch1_rx_rbclk_o : out std_logic;
ch1_rx_k_o : out std_logic;
ch1_rx_enc_err_o : out std_logic;
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
pad_rxp0_i : in std_logic := '0';
pad_txn1_o : out std_logic;
pad_txp1_o : out std_logic;
pad_rxn1_i : in std_logic := '0';
pad_rxp1_i : in std_logic := '0');
end component;
begin -- rtl
U_GTP1 : wr_gtp_phy_spartan6
generic map (
g_simulation => g_simulation)
port map (
ch0_ref_clk_i => fmc_ref_clk_i,
ch0_ref_clk_o => fmc_ref_clk_o,
ch0_tx_data_i => fmc_tx_data_i,
ch0_tx_k_i => fmc_tx_k_i,
ch0_tx_disparity_o => fmc_tx_disparity_o,
ch0_tx_enc_err_o => fmc_tx_enc_err_o,
ch0_rx_rbclk_o => fmc_rx_rbclk_o,
ch0_rx_data_o => fmc_rx_data_o,
ch0_rx_k_o => fmc_rx_k_o,
ch0_rx_enc_err_o => fmc_rx_enc_err_o,
ch0_rx_bitslide_o => fmc_rx_bitslide_o,
ch0_rst_i => fmc_rst_i,
ch0_loopen_i => fmc_loopen_i,
ch1_ref_clk_i => sata0_ref_clk_i,
ch1_ref_clk_o => sata0_ref_clk_o,
ch1_tx_data_i => sata0_tx_data_i,
ch1_tx_k_i => sata0_tx_k_i,
ch1_tx_disparity_o => sata0_tx_disparity_o,
ch1_tx_enc_err_o => sata0_tx_enc_err_o,
ch1_rx_data_o => sata0_rx_data_o,
ch1_rx_rbclk_o => sata0_rx_rbclk_o,
ch1_rx_k_o => sata0_rx_k_o,
ch1_rx_enc_err_o => sata0_rx_enc_err_o,
ch1_rx_bitslide_o => sata0_rx_bitslide_o,
ch1_rst_i => sata0_rst_i,
ch1_loopen_i => sata0_loopen_i,
pad_txn0_o => fmc_txn_o,
pad_txp0_o => fmc_txp_o,
pad_rxn0_i => fmc_rxn_i,
pad_rxp0_i => fmc_rxp_i,
pad_txn1_o => sata0_txn_o,
pad_txp1_o => sata0_txp_o,
pad_rxn1_i => sata0_rxn_i,
pad_rxp1_i => sata0_rxp_i);
U_GTP2 : wr_gtp_phy_spartan6
generic map (
g_simulation => g_simulation)
port map (
ch0_ref_clk_i => sata1_ref_clk_i,
ch0_ref_clk_o => sata1_ref_clk_o,
ch0_tx_data_i => sata1_tx_data_i,
ch0_tx_k_i => sata1_tx_k_i,
ch0_tx_disparity_o => sata1_tx_disparity_o,
ch0_tx_enc_err_o => sata1_tx_enc_err_o,
ch0_rx_rbclk_o => sata1_rx_rbclk_o,
ch0_rx_data_o => sata1_rx_data_o,
ch0_rx_k_o => sata1_rx_k_o,
ch0_rx_enc_err_o => sata1_rx_enc_err_o,
ch0_rx_bitslide_o => sata1_rx_bitslide_o,
ch0_rst_i => sata1_rst_i,
ch0_loopen_i => sata1_loopen_i,
ch1_ref_clk_i => sfp_ref_clk_i,
ch1_ref_clk_o => sfp_ref_clk_o,
ch1_tx_data_i => sfp_tx_data_i,
ch1_tx_k_i => sfp_tx_k_i,
ch1_tx_disparity_o => sfp_tx_disparity_o,
ch1_tx_enc_err_o => sfp_tx_enc_err_o,
ch1_rx_data_o => sfp_rx_data_o,
ch1_rx_rbclk_o => sfp_rx_rbclk_o,
ch1_rx_k_o => sfp_rx_k_o,
ch1_rx_enc_err_o => sfp_rx_enc_err_o,
ch1_rx_bitslide_o => sfp_rx_bitslide_o,
ch1_rst_i => sfp_rst_i,
ch1_loopen_i => sfp_loopen_i,
pad_txn0_o => sata1_txn_o,
pad_txp0_o => sata1_txp_o,
pad_rxn0_i => sata1_rxn_i,
pad_rxp0_i => sata1_rxp_i,
pad_txn1_o => sfp_txn_o,
pad_txp1_o => sfp_txp_o,
pad_rxn1_i => sfp_rxn_i,
pad_rxp1_i => sfp_rxp_i);
end rtl;
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