Commit cb8aa26a authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

xwrc_platform_xilinx: initial support for Kintex Ultrascale family

parent 7bfdf71a
......@@ -49,6 +49,7 @@ package wr_xilinx_pkg is
port (
areset_n_i : in std_logic := '1';
clk_10m_ext_i : in std_logic := '0';
clk_125m_pci_i : in std_logic := '0';
clk_125m_gtp_p_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_20m_vcxo_i : in std_logic := '0';
......@@ -188,4 +189,33 @@ package wr_xilinx_pkg is
rdy_o : out std_logic);
end component;
component wr_gthe3_phy_family7 is
generic (
g_simulation : integer);
port (
clk_gth_p_i : in std_logic;
clk_gth_n_i : in std_logic;
clk_freerun_i : in std_logic;
tx_out_clk_o : out std_logic;
tx_locked_o : out std_logic;
tx_data_i : in std_logic_vector(15 downto 0);
tx_k_i : in std_logic_vector(1 downto 0);
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_data_o : out std_logic_vector(15 downto 0);
rx_k_o : out std_logic_vector(1 downto 0);
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(4 downto 0);
rst_i : in std_logic;
loopen_i : in std_logic_vector(2 downto 0);
debug_i : in std_logic_vector(15 downto 0):=x"0000";
debug_o : out std_logic_vector(15 downto 0);
pad_txn_o : out std_logic;
pad_txp_o : out std_logic;
pad_rxn_i : in std_logic := '0';
pad_rxp_i : in std_logic := '0';
rdy_o : out std_logic);
end component wr_gthe3_phy_family7;
end wr_xilinx_pkg;
......@@ -89,6 +89,8 @@ entity xwrc_platform_xilinx is
clk_125m_pllref_i : in std_logic := '0';
-- 124.992 MHz DMTD reference (CLBv3 reference design)
clk_125m_dmtd_i : in std_logic := '0';
-- 125 MHz system clock (from PCI Express core, Xilinx Family 7)
clk_125m_pci_i: in std_logic := '0';
---------------------------------------------------------------------------
-- Clock inputs from custom PLLs (g_use_default_plls = FALSE)
---------------------------------------------------------------------------
......@@ -149,13 +151,14 @@ architecture rtl of xwrc_platform_xilinx is
signal pll_arst : std_logic := '0';
signal clk_125m_pllref_buf : std_logic;
signal clk_62m5_sys : std_logic;
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Check for unsupported features and/or misconfiguration
-----------------------------------------------------------------------------
gen_unknown_fpga : if (g_fpga_family /= "spartan6" and g_fpga_family /= "kintex7" and g_fpga_family /= "artix7") generate
gen_unknown_fpga : if (g_fpga_family /= "spartan6" and g_fpga_family /= "kintex7" and g_fpga_family /= "artix7" and g_fpga_family /= "kintexultrascale") generate
assert FALSE
report "Xilinx FPGA family [" & g_fpga_family & "] is not supported"
severity ERROR;
......@@ -575,6 +578,155 @@ begin -- architecture rtl
end generate gen_kintex7_default_plls;
---------------------------------------------------------------------------
-- Kintex Ultrascale PLLs
---------------------------------------------------------------------------
gen_kintexultrascale_default_plls : if (g_fpga_family = "kintexultrascale") generate
signal clk_sys : std_logic;
signal clk_sys_out : std_logic;
signal clk_sys_fb : std_logic;
signal pll_sys_locked : std_logic;
signal clk_dmtd : std_logic;
signal clk_dmtd_fb : std_logic;
signal pll_dmtd_locked : std_logic;
signal clk_20m_vcxo_buf : std_logic;
signal mmcm_sys_clk_fb_prebuf : std_logic;
signal mmcm_sys_clk_fb : std_logic;
begin
-- System PLL (100 MHz -> 62.5 MHz)
cmp_sys_clk_pll : MMCME3_ADV
generic map (
BANDWIDTH => "OPTIMIZED", -- Jitter programming (HIGH, LOW, OPTIMIZED)
COMPENSATION => "AUTO", -- AUTO, BUF_IN, EXTERNAL, INTERNAL, ZHOLD
STARTUP_WAIT => "FALSE", -- Delays DONE until MMCM is locked (FALSE, TRUE)
CLKOUT4_CASCADE => "FALSE",
-- CLKIN_PERIOD: Input clock period in ns units, ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => 8.0,
CLKFBOUT_MULT_F => 8.0, -- Multiply value for all CLKOUT (2.000-64.000)
DIVCLK_DIVIDE => 1, -- Master division value (1-106)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000)
CLKFBOUT_USE_FINE_PS => "FALSE",
CLKOUT0_DIVIDE_F => 16.0, -- clk_sys: 100 MHz * 10 / 16 = 62.5 MHz
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT0_PHASE => 0.0,
CLKOUT0_USE_FINE_PS => "FALSE"
)
port map (
-- Clock Inputs inputs: Clock inputs
CLKIN1 => clk_125m_pci_i,
CLKIN2 => '0',
-- Clock Outputs outputs: User configurable clock outputs
CLKOUT0 => clk_sys,
-- Feedback
CLKFBOUT => mmcm_sys_clk_fb_prebuf,
CLKFBIN => mmcm_sys_clk_fb,
-- Status Ports outputs: MMCM status ports
LOCKED => pll_sys_locked,
CDDCREQ => '0',
-- Control Ports inputs: MMCM control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => pll_arst,
-- DRP Ports inputs: Dynamic reconfiguration ports
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
-- Dynamic Phase Shift Ports inputs: Ports used for dynamic phase shifting of the outputs
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0'
);
cmp_buf_mmcm_sys_fb : BUFG
port map (
I => mmcm_sys_clk_fb_prebuf,
O => mmcm_sys_clk_fb);
-- System PLL output clock buffer
cmp_clk_sys_buf_o : BUFG
port map (
I => clk_sys,
O => clk_sys_out);
clk_62m5_sys_o <= clk_sys_out;
clk_62m5_sys <= clk_sys_out;
pll_locked_o <= pll_dmtd_locked and pll_sys_locked;
-- DMTD PLL (20 MHz -> ~62,5 MHz)
cmp_dmtd_clk_pll : MMCME3_ADV
generic map (
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => "FALSE",
COMPENSATION => "ZHOLD",
STARTUP_WAIT => "FALSE",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 50.000, -- 20 MHz -> 1 GHz
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => "FALSE",
CLKOUT0_DIVIDE_F => 16.000, -- 1GHz/16 -> 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => "FALSE",
CLKIN1_PERIOD => 50.000, -- 50ns for 20 MHz
REF_JITTER1 => 0.010)
port map (
-- Output clocks
CLKFBOUT => clk_dmtd_fb,
CLKOUT0 => clk_dmtd,
-- Input clock control
CLKFBIN => clk_dmtd_fb,
CLKIN1 => clk_20m_vcxo_buf,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
CDDCREQ => '0',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => pll_dmtd_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => pll_arst);
-- DMTD PLL input clock buffer
cmp_clk_dmtd_buf_i : BUFG
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
-- DMTD PLL output clock buffer
cmp_clk_dmtd_buf_o : BUFG
port map (
O => clk_62m5_dmtd_o,
I => clk_dmtd);
-- External 10MHz reference PLL for Kintex Ultrascale
gen_kintexultrascale_ext_ref_plls : if (g_with_external_clock_input = TRUE) generate
assert false report "External clock inputs not supported yet for Kintex Ultrascale family" severity FAILURE;
end generate gen_kintexultrascale_ext_ref_plls;
end generate gen_kintexultrascale_default_plls;
---------------------------------------------------------------------------
-- Artix7 PLLs
---------------------------------------------------------------------------
......@@ -585,9 +737,6 @@ begin -- architecture rtl
signal clk_sys_fb : std_logic;
signal pll_sys_locked : std_logic;
signal clk_dmtd : std_logic := '0'; -- initialize for simulation
-- signal clk_dmtd_fb : std_logic;
-- signal pll_dmtd_locked : std_logic;
-- signal clk_20m_vcxo_buf : std_logic;
begin
-- System PLL (125 MHz -> 62.5 MHz)
......@@ -941,6 +1090,58 @@ begin -- architecture rtl
end generate gen_phy_spartan6;
---------------------------------------------------------------------------
-- Kintex7 PHY
---------------------------------------------------------------------------
gen_phy_kintexultrascale : if (g_fpga_family = "kintexultrascale") generate
signal clk_ref : std_logic;
signal clk_125m_gtx_buf : std_logic;
signal clk_ref_locked : std_logic;
begin
cmp_gthe3 : wr_gthe3_phy_family7
generic map (
g_simulation => g_simulation)
port map (
clk_gth_p_i => clk_125m_gtp_p_i,
clk_gth_n_i => clk_125m_gtp_n_i,
clk_freerun_i => clk_62m5_sys,
tx_out_clk_o => clk_ref,
tx_data_i => phy16_i.tx_data,
tx_k_i => phy16_i.tx_k,
tx_disparity_o => phy16_o.tx_disparity,
tx_enc_err_o => phy16_o.tx_enc_err,
rx_rbclk_o => phy16_o.rx_clk,
rx_data_o => phy16_o.rx_data,
rx_k_o => phy16_o.rx_k,
rx_enc_err_o => phy16_o.rx_enc_err,
rx_bitslide_o => phy16_o.rx_bitslide,
rst_i => phy16_i.rst,
loopen_i => phy16_i.loopen_vec,
-- tx_prbs_sel_i => phy16_i.tx_prbs_sel,
rdy_o => phy16_o.rdy,
pad_txn_o => sfp_txn_o,
pad_txp_o => sfp_txp_o,
pad_rxn_i => sfp_rxn_i,
pad_rxp_i => sfp_rxp_i,
tx_locked_o => clk_ref_locked);
clk_125m_ref_o <= clk_ref;
clk_ref_locked_o <= clk_ref_locked;
phy16_o.ref_clk <= clk_ref;
phy16_o.sfp_tx_fault <= sfp_tx_fault_i;
phy16_o.sfp_los <= sfp_los_i;
sfp_tx_disable_o <= phy16_i.sfp_tx_disable;
phy8_o <= c_dummy_phy8_to_wrc;
end generate gen_phy_kintexultrascale;
---------------------------------------------------------------------------
-- Kintex7 PHY
---------------------------------------------------------------------------
......
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