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White Rabbit core collection
Commit d2f24245 authored by Peter Jansweijer's avatar Peter Jansweijer Committed by Grzegorz Daniluk
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clbv2 reference design files 

added clbv2_ref_design files
added initial clbv2_ref_design ucf file
removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization
removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization, phy16
Merge branch 'peter_clbv2_ref_design' of ohwr.org:hdl-core-lib/wr-cores into peter_clbv2_ref_design
clk_20m_vcxo_i free running clock for reset gen. (thus no need for separate 125 MHz fpga input; remove clk_125m_pllref_p/n_i)
updates kintex7 phy name to reflect new peter_xilinx_phys convention
last commit also needs artix7 support in xwrc_platform_xilinx.vhd
CLBv2: reference clock is 62.5 MHz for 16 bit PHYs. Changed naming convention accordingly.
CLBv2: point proper bram file
CLBv2: implementation (including bmm)
CLBv2 reference design cleaned
CLBv2: updated (hdlmake made) Xilinx ISE project file
parent 6b8136ef
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Showing with 3421 additions and 2 deletions
board/clbv2/Manifest.py 0 → 100644
View file @ d2f24245
files = [
"wr_clbv2_pkg.vhd",
"xwrc_board_clbv2.vhd",
"wrc_board_clbv2.vhd",
]
modules = {
"local" : [
"../common",
]
}
board/clbv2/wr_clbv2_pkg.vhd 0 → 100644
View file @ d2f24245
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wr_board_pkg.all;
use work.streamers_pkg.all;
package wr_clbv2_pkg is
component xwrc_board_clbv2 is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE;
g_aux_clks : integer := 0;
g_fabric_iface : t_board_fabric_iface := plain;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_dpram_initf : string := "default_xilinx";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
clk_20m_vcxo_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_62m5_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_62m5_n_o : out std_logic;
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic;
pll20dac_cs_n_o : out std_logic;
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_det_i : in std_logic := '1';
sfp_sda_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_i : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
link_ok_o : out std_logic);
end component xwrc_board_clbv2;
component wrc_board_clbv2 is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : integer := 1;
g_aux_clks : integer := 0;
g_fabric_iface : string := "PLAINFBRC";
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_dpram_initf : string := "default_xilinx";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_vector_width : integer := 0;
g_diag_rw_vector_width : integer := 0);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
clk_20m_vcxo_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_62m5_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_62m5_n_o : out std_logic;
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic;
pll20dac_cs_n_o : out std_logic;
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_det_i : in std_logic := '1';
sfp_sda_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
aux_master_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
aux_master_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
aux_master_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
aux_master_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
aux_master_we_o : out std_logic;
aux_master_cyc_o : out std_logic;
aux_master_stb_o : out std_logic;
aux_master_ack_i : in std_logic := '0';
aux_master_int_i : in std_logic := '0';
aux_master_err_i : in std_logic := '0';
aux_master_rty_i : in std_logic := '0';
aux_master_stall_i : in std_logic := '0';
wrf_src_adr_o : out std_logic_vector(1 downto 0);
wrf_src_dat_o : out std_logic_vector(15 downto 0);
wrf_src_cyc_o : out std_logic;
wrf_src_stb_o : out std_logic;
wrf_src_we_o : out std_logic;
wrf_src_sel_o : out std_logic_vector(1 downto 0);
wrf_src_ack_i : in std_logic;
wrf_src_stall_i : in std_logic;
wrf_src_err_i : in std_logic;
wrf_src_rty_i : in std_logic;
wrf_snk_adr_i : in std_logic_vector(1 downto 0);
wrf_snk_dat_i : in std_logic_vector(15 downto 0);
wrf_snk_cyc_i : in std_logic;
wrf_snk_stb_i : in std_logic;
wrf_snk_we_i : in std_logic;
wrf_snk_sel_i : in std_logic_vector(1 downto 0);
wrf_snk_ack_o : out std_logic;
wrf_snk_stall_o : out std_logic;
wrf_snk_err_o : out std_logic;
wrf_snk_rty_o : out std_logic;
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_tx_cfg_mac_t_i : in std_logic_vector(47 downto 0) := x"ffffffffffff";
wrs_tx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_rx_cfg_mac_r_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_rx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
wrs_rx_cfg_acc_b_i : in std_logic := '1';
wrs_rx_cfg_flt_r_i : in std_logic := '0';
wrs_rx_cfg_fix_l_i : in std_logic_vector(27 downto 0) := x"0000000";
wb_eth_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_eth_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_eth_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_eth_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
wb_eth_we_o : out std_logic;
wb_eth_cyc_o : out std_logic;
wb_eth_stb_o : out std_logic;
wb_eth_ack_i : in std_logic := '0';
wb_eth_int_i : in std_logic := '0';
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
aux_diag_i : in std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
tstamps_stb_o : out std_logic;
tstamps_tsval_o : out std_logic_vector(31 downto 0);
tstamps_port_id_o : out std_logic_vector(5 downto 0);
tstamps_frame_id_o : out std_logic_vector(15 downto 0);
tstamps_incorrect_o : out std_logic;
tstamps_ack_i : in std_logic := '1';
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
link_ok_o : out std_logic);
end component wrc_board_clbv2;
end wr_clbv2_pkg;
board/clbv2/wrc_board_clbv2.vhd 0 → 100644
View file @ d2f24245
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for clbv2
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wrc_board_clbv2.vhd
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Company : Nikhef
-- Created : 2017-11-08
-- Last update: 2017-11-08
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
-- needed to operate the core on the clbv2 board.
-- Version with no VHDL records on the top-level (mainly for Verilog
-- instantiation).
-------------------------------------------------------------------------------
-- Copyright (c) 2017 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wishbone_pkg.all;
use work.etherbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.streamers_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_clbv2_pkg.all;
entity wrc_board_clbv2 is
generic(
-- set to 1 to speed up some initialization processes during simulation
g_simulation : integer := 0;
-- Select whether to include external ref clock input
g_with_external_clock_input : integer := 1;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks : integer := 0;
-- "plainfbrc" = expose WRC fabric interface
-- "streamers" = attach WRC streamers to fabric interface
-- "etherbone" = attach Etherbone slave to fabric interface
g_fabric_iface : string := "plainfbrc";
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "default_xilinx";
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_vector_width : integer := 0;
g_diag_rw_vector_width : integer := 0
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset from system fpga
areset_n_i : in std_logic;
-- Optional reset input active low with rising edge detection. Does not
-- reset PLLs.
areset_edge_n_i : in std_logic := '1';
-- Clock inputs from the board
clk_20m_vcxo_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_i : in std_logic := '0';
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i : in std_logic := '0';
-- 62.5MHz sys clock output
clk_sys_62m5_o : out std_logic;
-- 125MHz ref clock output
clk_ref_62m5_o : out std_logic;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o : out std_logic;
rst_ref_62m5_n_o : out std_logic;
---------------------------------------------------------------------------
-- Shared SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic;
pll20dac_cs_n_o : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver and SFP management info
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_det_i : in std_logic := '1';
sfp_sda_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
---------------------------------------------------------------------------
-- I2C EEPROM
---------------------------------------------------------------------------
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- No Flash memory SPI interface
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plain")
---------------------------------------------------------------------------
wrf_src_adr_o : out std_logic_vector(1 downto 0);
wrf_src_dat_o : out std_logic_vector(15 downto 0);
wrf_src_cyc_o : out std_logic;
wrf_src_stb_o : out std_logic;
wrf_src_we_o : out std_logic;
wrf_src_sel_o : out std_logic_vector(1 downto 0);
wrf_src_ack_i : in std_logic;
wrf_src_stall_i : in std_logic;
wrf_src_err_i : in std_logic;
wrf_src_rty_i : in std_logic;
wrf_snk_adr_i : in std_logic_vector(1 downto 0);
wrf_snk_dat_i : in std_logic_vector(15 downto 0);
wrf_snk_cyc_i : in std_logic;
wrf_snk_stb_i : in std_logic;
wrf_snk_we_i : in std_logic;
wrf_snk_sel_i : in std_logic_vector(1 downto 0);
wrf_snk_ack_o : out std_logic;
wrf_snk_stall_o : out std_logic;
wrf_snk_err_o : out std_logic;
wrf_snk_rty_o : out std_logic;
---------------------------------------------------------------------------
-- WR streamers (when g_fabric_iface = "streamers")
---------------------------------------------------------------------------
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_tx_cfg_mac_t_i : in std_logic_vector(47 downto 0) := x"ffffffffffff";
wrs_tx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_rx_cfg_mac_r_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_rx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
wrs_rx_cfg_acc_b_i : in std_logic := '1';
wrs_rx_cfg_flt_r_i : in std_logic := '0';
wrs_rx_cfg_fix_l_i : in std_logic_vector(27 downto 0) := x"0000000";
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
wb_eth_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_eth_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_eth_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_eth_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
wb_eth_we_o : out std_logic;
wb_eth_cyc_o : out std_logic;
wb_eth_stb_o : out std_logic;
wb_eth_ack_i : in std_logic := '0';
wb_eth_int_i : in std_logic := '0';
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
---------------------------------------------------------------------------
-- Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i : in std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
---------------------------------------------------------------------------
-- External Tx Timestamping I/F
---------------------------------------------------------------------------
tstamps_stb_o : out std_logic;
tstamps_tsval_o : out std_logic_vector(31 downto 0);
tstamps_port_id_o : out std_logic_vector(5 downto 0);
tstamps_frame_id_o : out std_logic_vector(15 downto 0);
tstamps_incorrect_o : out std_logic;
tstamps_ack_i : in std_logic := '1';
-----------------------------------------
-- Timestamp helper signals, used for Absolute Calibration
-----------------------------------------
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
---------------------------------------------------------------------------
-- Pause Frame Control
---------------------------------------------------------------------------
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
---------------------------------------------------------------------------
-- Timecode I/F
---------------------------------------------------------------------------
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
---------------------------------------------------------------------------
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
-- 1PPS output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
-- Link ok indication
link_ok_o : out std_logic
);
end entity wrc_board_clbv2;
architecture std_wrapper of wrc_board_clbv2 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- WR fabric interface
signal wrf_src_out : t_wrf_source_out;
signal wrf_src_in : t_wrf_source_in;
signal wrf_snk_out : t_wrf_sink_out;
signal wrf_snk_in : t_wrf_sink_in;
-- Aux diagnostics
constant c_diag_ro_size : integer := g_diag_ro_vector_width/32;
constant c_diag_rw_size : integer := g_diag_rw_vector_width/32;
signal aux_diag_in : t_generic_word_array(c_diag_ro_size-1 downto 0);
signal aux_diag_out : t_generic_word_array(c_diag_rw_size-1 downto 0);
-- External Tx Timestamping I/F
signal timestamps_out : t_txtsu_timestamp;
-- streamers config
signal wrs_tx_cfg_in : t_tx_streamer_cfg;
signal wrs_rx_cfg_in : t_rx_streamer_cfg;
begin -- architecture struct
wrf_src_adr_o <= wrf_src_out.adr;
wrf_src_dat_o <= wrf_src_out.dat;
wrf_src_cyc_o <= wrf_src_out.cyc;
wrf_src_stb_o <= wrf_src_out.stb;
wrf_src_we_o <= wrf_src_out.we;
wrf_src_sel_o <= wrf_src_out.sel;
wrf_src_in.ack <= wrf_src_ack_i;
wrf_src_in.stall <= wrf_src_stall_i;
wrf_src_in.err <= wrf_src_err_i;
wrf_src_in.rty <= wrf_src_rty_i;
wrf_snk_in.adr <= wrf_snk_adr_i;
wrf_snk_in.dat <= wrf_snk_dat_i;
wrf_snk_in.cyc <= wrf_snk_cyc_i;
wrf_snk_in.stb <= wrf_snk_stb_i;
wrf_snk_in.we <= wrf_snk_we_i;
wrf_snk_in.sel <= wrf_snk_sel_i;
wrf_snk_ack_o <= wrf_snk_out.ack;
wrf_snk_stall_o <= wrf_snk_out.stall;
wrf_snk_err_o <= wrf_snk_out.err;
wrf_snk_rty_o <= wrf_snk_out.rty;
aux_diag_in <= f_de_vectorize_diag(aux_diag_i, g_diag_ro_vector_width);
aux_diag_o <= f_vectorize_diag(aux_diag_out, g_diag_rw_vector_width);
tstamps_stb_o <= timestamps_out.stb;
tstamps_tsval_o <= timestamps_out.tsval;
tstamps_port_id_o <= timestamps_out.port_id;
tstamps_frame_id_o <= timestamps_out.frame_id;
wrs_tx_cfg_in.mac_local <= wrs_tx_cfg_mac_l_i;
wrs_tx_cfg_in.mac_target <= wrs_tx_cfg_mac_t_i;
wrs_tx_cfg_in.ethertype <= wrs_tx_cfg_etype_i;
wrs_rx_cfg_in.mac_local <= wrs_rx_cfg_mac_l_i;
wrs_rx_cfg_in.mac_remote <= wrs_rx_cfg_mac_r_i;
wrs_rx_cfg_in.ethertype <= wrs_rx_cfg_etype_i;
wrs_rx_cfg_in.accept_broadcasts <= wrs_rx_cfg_acc_b_i;
wrs_rx_cfg_in.filter_remote <= wrs_rx_cfg_flt_r_i;
wrs_rx_cfg_in.fixed_latency <= wrs_rx_cfg_fix_l_i;
-- Instantiate the records-based module
cmp_xwrc_board_clbv2 : xwrc_board_clbv2
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
g_aux_clks => g_aux_clks,
g_fabric_iface => f_str2iface_type(g_fabric_iface),
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
g_dpram_initf => g_dpram_initf,
g_diag_id => g_diag_id,
g_diag_ver => g_diag_ver,
g_diag_ro_size => c_diag_ro_size,
g_diag_rw_size => c_diag_rw_size)
port map (
areset_n_i => areset_n_i,
areset_edge_n_i => areset_edge_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_10m_ext_i => clk_10m_ext_i,
pps_ext_i => pps_ext_i,
clk_sys_62m5_o => clk_sys_62m5_o,
clk_ref_62m5_o => clk_ref_62m5_o,
rst_sys_62m5_n_o => rst_sys_62m5_n_o,
rst_ref_62m5_n_o => rst_ref_62m5_n_o,
plldac_din_o => plldac_din_o,
plldac_sclk_o => plldac_sclk_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_det_i,
sfp_sda_i => sfp_sda_i,
sfp_sda_o => sfp_sda_o,
sfp_scl_i => sfp_scl_i,
sfp_scl_o => sfp_scl_o,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
eeprom_sda_i => eeprom_sda_i,
eeprom_sda_o => eeprom_sda_o,
eeprom_scl_i => eeprom_scl_i,
eeprom_scl_o => eeprom_scl_o,
onewire_i => onewire_i,
onewire_oen_o => onewire_oen_o,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
wrf_src_o => wrf_src_out,
wrf_src_i => wrf_src_in,
wrf_snk_o => wrf_snk_out,
wrf_snk_i => wrf_snk_in,
wrs_tx_data_i => wrs_tx_data_i,
wrs_tx_valid_i => wrs_tx_valid_i,
wrs_tx_dreq_o => wrs_tx_dreq_o,
wrs_tx_last_i => wrs_tx_last_i,
wrs_tx_flush_i => wrs_tx_flush_i,
wrs_tx_cfg_i => wrs_tx_cfg_in,
wrs_rx_first_o => wrs_rx_first_o,
wrs_rx_last_o => wrs_rx_last_o,
wrs_rx_data_o => wrs_rx_data_o,
wrs_rx_valid_o => wrs_rx_valid_o,
wrs_rx_dreq_i => wrs_rx_dreq_i,
wrs_rx_cfg_i => wrs_rx_cfg_in,
aux_diag_i => aux_diag_in,
aux_diag_o => aux_diag_out,
tm_dac_value_o => tm_dac_value_o,
tm_dac_wr_o => tm_dac_wr_o,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
tm_clk_aux_locked_o => tm_clk_aux_locked_o,
timestamps_o => timestamps_out,
timestamps_ack_i => tstamps_ack_i,
abscal_txts_o => abscal_txts_o,
abscal_rxts_o => abscal_rxts_o,
fc_tx_pause_req_i => fc_tx_pause_req_i,
fc_tx_pause_delay_i => fc_tx_pause_delay_i,
fc_tx_pause_ready_o => fc_tx_pause_ready_o,
tm_link_up_o => tm_link_up_o,
tm_time_valid_o => tm_time_valid_o,
tm_tai_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
led_act_o => led_act_o,
led_link_o => led_link_o,
btn1_i => btn1_i,
btn2_i => btn2_i,
pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
link_ok_o => link_ok_o);
end architecture std_wrapper;
board/clbv2/xwrc_board_clbv2.vhd 0 → 100644
View file @ d2f24245
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for clbv2
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : xwrc_board_clbv2.vhd
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Company : Nikhef
-- Created : 2017-11-08
-- Last update: 2017-11-08
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
-- needed to operate the core on the clbv2 board.
-------------------------------------------------------------------------------
-- Copyright (c) 2017 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wishbone_pkg.all;
--use work.etherbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.streamers_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_clbv2_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity xwrc_board_clbv2 is
generic(
-- set to 1 to speed up some initialization processes during simulation
g_simulation : integer := 0;
-- Select whether to include external ref clock input
g_with_external_clock_input : boolean := TRUE;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks : integer := 1;
-- plain = expose WRC fabric interface
-- streamers = attach WRC streamers to fabric interface
-- etherbone = attach Etherbone slave to fabric interface
g_fabric_iface : t_board_fabric_iface := plain;
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "default_xilinx";
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset input (active low, can be async)
areset_n_i : in std_logic;
-- Optional reset input active low with rising edge detection. Does not
-- reset PLLs.
areset_edge_n_i : in std_logic := '1';
-- Clock inputs from the board
clk_20m_vcxo_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_i : in std_logic := '0';
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i : in std_logic := '0';
-- 62.5MHz sys clock output
clk_sys_62m5_o : out std_logic;
-- 62.5MHz ref clock output
clk_ref_62m5_o : out std_logic;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o : out std_logic;
rst_ref_62m5_n_o : out std_logic;
---------------------------------------------------------------------------
-- Shared SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic;
pll20dac_cs_n_o : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver and SFP management info
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_det_i : in std_logic := '1';
sfp_sda_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
---------------------------------------------------------------------------
-- I2C EEPROM
---------------------------------------------------------------------------
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- No Flash memory SPI interface
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- No External WB interface
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plainfbrc")
---------------------------------------------------------------------------
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
---------------------------------------------------------------------------
-- WR streamers (when g_fabric_iface = "streamers")
---------------------------------------------------------------------------
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_i : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
---------------------------------------------------------------------------
-- No Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
---------------------------------------------------------------------------
-- External Tx Timestamping I/F
---------------------------------------------------------------------------
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
-----------------------------------------
-- Timestamp helper signals, used for Absolute Calibration
-----------------------------------------
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
---------------------------------------------------------------------------
-- Pause Frame Control
---------------------------------------------------------------------------
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
---------------------------------------------------------------------------
-- Timecode I/F
---------------------------------------------------------------------------
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
---------------------------------------------------------------------------
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
-- 1PPS output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
-- Link ok indication
link_ok_o : out std_logic
);
end entity xwrc_board_clbv2;
architecture struct of xwrc_board_clbv2 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- PLLs, clocks
signal clk_pll_62m5 : std_logic;
signal clk_ref_62m5 : std_logic;
signal clk_pll_dmtd : std_logic;
signal pll_locked : std_logic;
signal clk_10m_ext : std_logic;
-- Reset logic
signal areset_edge_ppulse : std_logic;
signal rst_62m5_n : std_logic;
signal rstlogic_arst_n : std_logic;
signal rstlogic_clk_in : std_logic_vector(1 downto 0);
signal rstlogic_rst_out : std_logic_vector(1 downto 0);
-- PLL DACs
signal dac_hpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_load_p1 : std_logic;
signal dac_dpll_data : std_logic_vector(15 downto 0);
-- OneWire
signal onewire_in : std_logic_vector(1 downto 0);
signal onewire_en : std_logic_vector(1 downto 0);
-- PHY
signal phy16_to_wrc : t_phy_16bits_to_wrc;
signal phy16_from_wrc : t_phy_16bits_from_wrc;
-- External reference
signal ext_ref_mul : std_logic;
signal ext_ref_mul_locked : std_logic;
signal ext_ref_mul_stopped : std_logic;
signal ext_ref_rst : std_logic;
begin -- architecture struct
-----------------------------------------------------------------------------
-- Platform-dependent part (PHY, PLLs, buffers, etc)
-----------------------------------------------------------------------------
cmp_xwrc_platform : xwrc_platform_xilinx
generic map (
g_fpga_family => "kintex7",
g_with_external_clock_input => g_with_external_clock_input,
g_use_default_plls => TRUE,
g_simulation => g_simulation)
port map (
areset_n_i => areset_n_i,
clk_10m_ext_i => clk_10m_ext_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
sfp_txn_o => sfp_txn_o,
sfp_txp_o => sfp_txp_o,
sfp_rxn_i => sfp_rxn_i,
sfp_rxp_i => sfp_rxp_i,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_los_i => sfp_los_i,
sfp_tx_disable_o => sfp_tx_disable_o,
clk_62m5_sys_o => clk_pll_62m5,
clk_125m_ref_o => clk_ref_62m5, -- Note: This is a 62m5 Clock for 16 bit PHYs!
clk_62m5_dmtd_o => clk_pll_dmtd,
pll_locked_o => pll_locked,
clk_10m_ext_o => clk_10m_ext,
phy16_o => phy16_to_wrc,
phy16_i => phy16_from_wrc,
ext_ref_mul_o => ext_ref_mul,
ext_ref_mul_locked_o => ext_ref_mul_locked,
ext_ref_mul_stopped_o => ext_ref_mul_stopped,
ext_ref_rst_i => ext_ref_rst);
clk_sys_62m5_o <= clk_pll_62m5;
clk_ref_62m5_o <= clk_ref_62m5;
-----------------------------------------------------------------------------
-- Reset logic
-----------------------------------------------------------------------------
-- Detect when areset_edge_n_i goes high (end of reset) and use this edge to
-- generate rstlogic_arst_n. This is needed to connect optional reset like PCIe
-- reset. When baord runs standalone, we need to ignore PCIe reset being
-- constantly low.
cmp_arst_edge: gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_pll_62m5,
rst_n_i => '1',
data_i => areset_edge_n_i,
ppulse_o => areset_edge_ppulse);
-- logic AND of all async reset sources (active low)
rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse);
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in(0) <= clk_pll_62m5;
rstlogic_clk_in(1) <= clk_ref_62m5;
cmp_rstlogic_reset : gc_reset
generic map (
g_clocks => 2, -- 62.5MHz, 125MHz
g_logdelay => 4, -- 16 clock cycles
g_syncdepth => 3) -- length of sync chains
port map (
free_clk_i => clk_20m_vcxo_i,
locked_i => rstlogic_arst_n,
clks_i => rstlogic_clk_in,
rstn_o => rstlogic_rst_out);
-- distribution of resets (already synchronized to their clock domains)
rst_62m5_n <= rstlogic_rst_out(0);
rst_sys_62m5_n_o <= rst_62m5_n;
rst_ref_62m5_n_o <= rstlogic_rst_out(1);
-----------------------------------------------------------------------------
-- 2x SPI DAC
-----------------------------------------------------------------------------
cmp_dac_arb : spec_serial_dac_arb
generic map (
g_invert_sclk => FALSE,
g_num_extra_bits => 8)
port map (
clk_i => clk_pll_62m5,
rst_n_i => rst_62m5_n,
val1_i => dac_dpll_data,
load1_i => dac_dpll_load_p1,
val2_i => dac_hpll_data,
load2_i => dac_hpll_load_p1,
dac_cs_n_o(0) => pll25dac_cs_n_o,
dac_cs_n_o(1) => pll20dac_cs_n_o,
dac_sclk_o => plldac_sclk_o,
dac_din_o => plldac_din_o);
-----------------------------------------------------------------------------
-- The WR PTP core with optional fabric interface attached
-----------------------------------------------------------------------------
cmp_board_common : xwrc_board_common
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => g_with_external_clock_input,
g_board_name => "CLB2",
g_phys_uart => TRUE,
g_virtual_uart => TRUE,
g_aux_clks => g_aux_clks,
g_ep_rxbuf_size => 1024,
g_tx_runt_padding => TRUE,
g_dpram_initf => g_dpram_initf,
g_dpram_size => 131072/4,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_aux_sdb => c_wrc_periph3_sdb,
g_softpll_enable_debugger => FALSE,
g_vuart_fifo_size => 1024,
g_pcs_16bit => TRUE,
g_diag_id => g_diag_id,
g_diag_ver => g_diag_ver,
g_diag_ro_size => g_diag_ro_size,
g_diag_rw_size => g_diag_rw_size,
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
g_fabric_iface => g_fabric_iface
)
port map (
clk_sys_i => clk_pll_62m5,
clk_dmtd_i => clk_pll_dmtd,
clk_ref_i => clk_ref_62m5,
clk_aux_i => clk_aux_i,
clk_10m_ext_i => clk_10m_ext,
clk_ext_mul_i => ext_ref_mul,
clk_ext_mul_locked_i => ext_ref_mul_locked,
clk_ext_stopped_i => ext_ref_mul_stopped,
clk_ext_rst_o => ext_ref_rst,
pps_ext_i => pps_ext_i,
rst_n_i => rst_62m5_n,
dac_hpll_load_p1_o => dac_hpll_load_p1,
dac_hpll_data_o => dac_hpll_data,
dac_dpll_load_p1_o => dac_dpll_load_p1,
dac_dpll_data_o => dac_dpll_data,
phy16_o => phy16_from_wrc,
phy16_i => phy16_to_wrc,
scl_o => eeprom_scl_o,
scl_i => eeprom_scl_i,
sda_o => eeprom_sda_o,
sda_i => eeprom_sda_i,
sfp_scl_o => sfp_scl_o,
sfp_scl_i => sfp_scl_i,
sfp_sda_o => sfp_sda_o,
sfp_sda_i => sfp_sda_i,
sfp_det_i => sfp_det_i,
spi_sclk_o => open,
spi_ncs_o => open,
spi_mosi_o => open,
spi_miso_i => '0',
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
owr_pwren_o => open,
owr_en_o => onewire_en,
owr_i => onewire_in,
wrf_src_o => wrf_src_o,
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
wrf_snk_i => wrf_snk_i,
wrs_tx_data_i => wrs_tx_data_i,
wrs_tx_valid_i => wrs_tx_valid_i,
wrs_tx_dreq_o => wrs_tx_dreq_o,
wrs_tx_last_i => wrs_tx_last_i,
wrs_tx_flush_i => wrs_tx_flush_i,
wrs_tx_cfg_i => wrs_tx_cfg_i,
wrs_rx_first_o => wrs_rx_first_o,
wrs_rx_last_o => wrs_rx_last_o,
wrs_rx_data_o => wrs_rx_data_o,
wrs_rx_valid_o => wrs_rx_valid_o,
wrs_rx_dreq_i => wrs_rx_dreq_i,
wrs_rx_cfg_i => wrs_rx_cfg_i,
aux_diag_i => aux_diag_i,
aux_diag_o => aux_diag_o,
tm_dac_value_o => tm_dac_value_o,
tm_dac_wr_o => tm_dac_wr_o,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
tm_clk_aux_locked_o => tm_clk_aux_locked_o,
timestamps_o => timestamps_o,
timestamps_ack_i => timestamps_ack_i,
abscal_txts_o => abscal_txts_o,
abscal_rxts_o => abscal_rxts_o,
fc_tx_pause_req_i => fc_tx_pause_req_i,
fc_tx_pause_delay_i => fc_tx_pause_delay_i,
fc_tx_pause_ready_o => fc_tx_pause_ready_o,
tm_link_up_o => tm_link_up_o,
tm_time_valid_o => tm_time_valid_o,
tm_tai_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
led_act_o => led_act_o,
led_link_o => led_link_o,
btn1_i => btn1_i,
btn2_i => btn2_i,
pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
link_ok_o => link_ok_o);
sfp_rate_select_o <= '1';
onewire_oen_o <= onewire_en(0);
onewire_in(0) <= onewire_i;
onewire_in(1) <= '1';
end architecture struct;
platform/xilinx/wr_xilinx_pkg.vhd
View file @ d2f24245
......@@ -99,7 +99,7 @@ package wr_xilinx_pkg is
pad_rxp1_i : in std_logic := '0');
end component;
component wr_gtx_phy_kintex7 is
component wr_gtx_phy_family7 is
generic (
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation : integer := 0);
......@@ -126,4 +126,31 @@ package wr_xilinx_pkg is
rdy_o : out std_logic);
end component;
component wr_gtp_phy_family7 is
generic (
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation : integer := 0);
port (
clk_gtp_i : in std_logic;
tx_out_clk_o : out std_logic;
tx_locked_o : out std_logic;
tx_data_i : in std_logic_vector(15 downto 0);
tx_k_i : in std_logic_vector(1 downto 0);
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_data_o : out std_logic_vector(15 downto 0);
rx_k_o : out std_logic_vector(1 downto 0);
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(4 downto 0);
rst_i : in std_logic;
loopen_i : in std_logic_vector(2 downto 0);
tx_prbs_sel_i : in std_logic_vector(2 downto 0);
pad_txn_o : out std_logic;
pad_txp_o : out std_logic;
pad_rxn_i : in std_logic := '0';
pad_rxp_i : in std_logic := '0';
rdy_o : out std_logic);
end component;
end wr_xilinx_pkg;
platform/xilinx/xwrc_platform_xilinx.vhd
View file @ d2f24245
......@@ -569,8 +569,233 @@ begin -- architecture rtl
end generate gen_kintex7_ext_ref_pll;
end generate gen_kintex7_default_plls;
---------------------------------------------------------------------------
-- Artix7 PLLs
---------------------------------------------------------------------------
gen_artix7_default_plls : if (g_fpga_family = "artix7") generate
signal clk_sys : std_logic;
signal clk_sys_out : std_logic;
signal clk_sys_fb : std_logic;
signal pll_sys_locked : std_logic;
-- signal clk_dmtd : std_logic;
-- signal clk_dmtd_fb : std_logic;
-- signal pll_dmtd_locked : std_logic;
-- signal clk_20m_vcxo_buf : std_logic;
begin
-- System PLL (125 MHz -> 62.5 MHz)
cmp_sys_clk_pll : MMCME2_ADV
generic map (
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => false,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => false,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 8.000, -- 125 MHz x 8.
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => false,
CLKOUT0_DIVIDE_F => 16.000, -- 62.5 MHz sys clock
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => false,
CLKIN1_PERIOD => 8.000, -- 8 ns means 125 MHz
REF_JITTER1 => 0.010)
port map (
-- Output clocks
CLKFBOUT => clk_sys_fb,
CLKOUT0 => clk_sys,
-- Input clock control
CLKFBIN => clk_sys_fb,
CLKIN1 => clk_125m_pllref_buf,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => pll_sys_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => pll_arst);
-- System PLL output clock buffer
cmp_clk_sys_buf_o : BUFG
port map (
I => clk_sys,
O => clk_sys_out);
clk_62m5_sys_o <= clk_sys_out;
-- pll_locked_o <= pll_dmtd_locked and pll_sys_locked;
pll_locked_o <= pll_sys_locked;
-- -- DMTD PLL (20 MHz -> ~62,5 MHz)
-- cmp_dmtd_clk_pll : MMCME2_ADV
-- generic map (
-- BANDWIDTH => "OPTIMIZED",
-- CLKOUT4_CASCADE => false,
-- COMPENSATION => "ZHOLD",
-- STARTUP_WAIT => false,
-- DIVCLK_DIVIDE => 1,
-- CLKFBOUT_MULT_F => 50.000, -- 20 MHz -> 1 GHz
-- CLKFBOUT_PHASE => 0.000,
-- CLKFBOUT_USE_FINE_PS => false,
-- CLKOUT0_DIVIDE_F => 16.000, -- 1GHz/16 -> 62.5 MHz
-- CLKOUT0_PHASE => 0.000,
-- CLKOUT0_DUTY_CYCLE => 0.500,
-- CLKOUT0_USE_FINE_PS => false,
-- CLKOUT1_DIVIDE => 16, -- 1GHz/16 -> 62.5 MHz
-- CLKOUT1_PHASE => 0.000,
-- CLKOUT1_DUTY_CYCLE => 0.500,
-- CLKOUT1_USE_FINE_PS => false,
-- CLKIN1_PERIOD => 50.000, -- 50ns for 20 MHz
-- REF_JITTER1 => 0.010)
-- port map (
-- -- Output clocks
-- CLKFBOUT => clk_dmtd_fb,
-- CLKOUT0 => clk_dmtd,
-- -- Input clock control
-- CLKFBIN => clk_dmtd_fb,
-- CLKIN1 => clk_20m_vcxo_buf,
-- CLKIN2 => '0',
-- -- Tied to always select the primary input clock
-- CLKINSEL => '1',
-- -- Ports for dynamic reconfiguration
-- DADDR => (others => '0'),
-- DCLK => '0',
-- DEN => '0',
-- DI => (others => '0'),
-- DO => open,
-- DRDY => open,
-- DWE => '0',
-- -- Ports for dynamic phase shift
-- PSCLK => '0',
-- PSEN => '0',
-- PSINCDEC => '0',
-- PSDONE => open,
-- -- Other control and status signals
-- LOCKED => pll_dmtd_locked,
-- CLKINSTOPPED => open,
-- CLKFBSTOPPED => open,
-- PWRDWN => '0',
-- RST => pll_arst);
--
-- -- DMTD PLL input clock buffer
-- cmp_clk_dmtd_buf_i : BUFG
-- port map (
-- O => clk_20m_vcxo_buf,
-- I => clk_20m_vcxo_i);
--
-- -- DMTD PLL output clock buffer
-- cmp_clk_dmtd_buf_o : BUFG
-- port map (
-- O => clk_62m5_dmtd_o,
-- I => clk_dmtd);
-- External 10MHz reference PLL for Artix7
gen_artix7_ext_ref_pll : if (g_with_external_clock_input = TRUE) generate
signal clk_ext_fbi : std_logic;
signal clk_ext_fbo : std_logic;
signal clk_ext_buf : std_logic;
signal clk_ext_mul : std_logic;
signal pll_ext_rst : std_logic;
begin
mmcm_adv_inst : MMCME2_ADV
generic map (
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 62.500,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 10.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 100.000,
REF_JITTER1 => 0.005)
port map (
-- Output clocks
CLKFBOUT => clk_ext_fbo,
CLKOUT0 => clk_ext_mul,
-- Input clock control
CLKFBIN => clk_ext_fbi,
CLKIN1 => clk_ext_buf,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open, -- Other control and status signals
LOCKED => ext_ref_mul_locked_o,
CLKINSTOPPED => ext_ref_mul_stopped_o,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => pll_ext_rst);
-- External reference input buffer
cmp_clk_ext_buf_i : BUFG
port map (
O => clk_ext_buf,
I => clk_10m_ext_i);
clk_10m_ext_o <= clk_ext_buf;
-- External reference feedback buffer
cmp_clk_ext_buf_fb : BUFG
port map (
O => clk_ext_fbi,
I => clk_ext_fbo);
-- External reference output buffer
cmp_clk_ext_buf_o : BUFG
port map (
O => ext_ref_mul_o,
I => clk_ext_mul);
cmp_extend_ext_reset : gc_extend_pulse
generic map (
g_width => 1000)
port map (
clk_i => clk_sys_out,
rst_n_i => pll_sys_locked,
pulse_i => ext_ref_rst_i,
extended_o => pll_ext_rst);
end generate gen_artix7_ext_ref_pll;
end generate gen_artix7_default_plls;
---------------------------------------------------------------------------
gen_no_ext_ref_pll : if (g_with_external_clock_input = FALSE) generate
clk_10m_ext_o <= '0';
ext_ref_mul_o <= '0';
......@@ -731,7 +956,7 @@ begin -- architecture rtl
I => clk_125m_gtx_buf,
O => clk_125m_pllref_buf);
cmp_gtx: wr_gtx_phy_kintex7
cmp_gtx: wr_gtx_phy_family7
generic map(
g_simulation => g_simulation)
port map(
......@@ -769,5 +994,72 @@ begin -- architecture rtl
end generate gen_phy_kintex7;
---------------------------------------------------------------------------
-- Artix7 PHY
---------------------------------------------------------------------------
gen_phy_artix7 : if (g_fpga_family = "artix7") generate
signal clk_ref : std_logic;
signal clk_125m_gtp_buf : std_logic;
begin
-- Dedicated GTP clock.
cmp_gtp_dedicated_clk : IBUFDS_GTE2
generic map(
CLKCM_CFG => true,
CLKRCV_TRST => true,
CLKSWING_CFG => "11")
port map (
O => clk_125m_gtp_buf,
ODIV2 => open,
CEB => '0',
I => clk_125m_gtp_p_i,
IB => clk_125m_gtp_n_i);
-- System PLL input clock buffer
cmp_clk_sys_buf_i : BUFG
port map (
I => clk_125m_gtp_buf,
O => clk_125m_pllref_buf);
cmp_gtp: wr_gtp_phy_family7
generic map(
g_simulation => g_simulation)
port map(
clk_gtp_i => clk_125m_gtp_buf,
tx_out_clk_o => clk_ref,
tx_data_i => phy16_i.tx_data,
tx_k_i => phy16_i.tx_k,
tx_disparity_o => phy16_o.tx_disparity,
tx_enc_err_o => phy16_o.tx_enc_err,
rx_rbclk_o => phy16_o.rx_clk,
rx_data_o => phy16_o.rx_data,
rx_k_o => phy16_o.rx_k,
rx_enc_err_o => phy16_o.rx_enc_err,
rx_bitslide_o => phy16_o.rx_bitslide,
rst_i => phy16_i.rst,
loopen_i => phy16_i.loopen_vec,
tx_prbs_sel_i => phy16_i.tx_prbs_sel,
rdy_o => phy16_o.rdy,
pad_txn_o => sfp_txn_o,
pad_txp_o => sfp_txp_o,
pad_rxn_i => sfp_rxn_i,
pad_rxp_i => sfp_rxp_i,
tx_locked_o => open);
clk_125m_ref_o <= clk_ref;
phy16_o.ref_clk <= clk_ref;
phy16_o.sfp_tx_fault <= sfp_tx_fault_i;
phy16_o.sfp_los <= sfp_los_i;
sfp_tx_disable_o <= phy16_i.sfp_tx_disable;
phy8_o <= c_dummy_phy8_to_wrc;
end generate gen_phy_artix7;
---------------------------------------------------------------------------
end architecture rtl;
syn/clbv2_ref_design/Manifest.py 0 → 100644
View file @ d2f24245
target = "xilinx"
action = "synthesis"
syn_device = "xc7k160t"
syn_grade = "-2"
syn_package = "fbg676"
syn_top = "clbv2_wr_ref_top"
syn_project = "clbv2_wr_ref.xise"
syn_tool = "ise"
modules = { "local" : "../../top/clbv2_ref_design/"}
syn/clbv2_ref_design/clbv2_wr_ref.xise 0 → 100644
View file @ d2f24245
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../board/clbv2/xwrc_board_clbv2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xrx_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
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<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="clbv2_wr_ref.xise" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-11-30T12:58:29" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9A7162D46C074C4395ECD9E6FDD4DA79" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
top/clbv2_ref_design/Manifest.py 0 → 100644
View file @ d2f24245
fetchto = "../../ip_cores"
files = [
"clbv2_wr_ref_top.vhd",
"clbv2_wr_ref_top.ucf",
"clbv2_wr_ref_top.bmm",
]
modules = {
"local" : [
"../../",
"../../board/clbv2",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
}
top/clbv2_ref_design/clbv2_wr_ref_top.bmm 0 → 100644
View file @ d2f24245
/* FILE : clbv2_wr_ref_top.bmm
* Define a BRAM map for the LM32 memory.
* Run ISE Translate -> "Floorplan Area/IO/Logic (PlanAhead)" once (without this BMM file
* attached to the ISE Project) to find out that there are 16 ramloops and each RAMB36E1
* Note: *THE RAMLOOP ORDER WITHIN A BUS_BLOCK IS VERY IMPORTANT!!!*
* Define ramloop 15 downto 0 and databits 31 downto 0 !!! Otherwise the memory
* content will be swapped and the program fails to execute. Aperently the ramloop
* number and bit definitions are not read by data2mem.
*
*
* Address space LM32 memory
* g_dpram_size = 90112/4 = 22528
* This size is in 32 bit words => byte size = 4 * 22528 = 90112 bytes
*
* ATTENTION PARITY!
* Although the memory is implemented in RAMB36E1 the address same MUST be defined as
* RAMB32 (insetad of RAMB36) since we are NOT using parity! If the address space is
* defined as RAMB36 then data2mem is expecting an extra nibble for each 32 bit instruction
* in the ".elf" file and since this nibble is not provided, the ramblocks will be filled
* such that a nibble shift is accumulating in the data.
* Note that this can be examined using the command
* "data2mem -bm clbv2_wr_ref_top_bd.bmm -bt clbv2_wr_ref_top_elf.bit -d > dump.txt"
*
* ATTENTION Xilinx Synthesis
* XST implements the 22K * 32 bit as:
* 22 blocks of 1K * 32 bits
*
****************************************************************************************/
ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF]
ADDRESS_RANGE RAMB32
BUS_BLOCK
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram38 [31];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram37 [30];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram36 [29];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram35 [28];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram34 [27];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram33 [26];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram32 [25];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram31 [24];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram28 [23];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram27 [22];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram26 [21];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram25 [20];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram24 [19];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram23 [18];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram22 [17];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram21 [16];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram18 [15];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram17 [14];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram16 [13];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram15 [12];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram14 [11];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram13 [10];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram12 [9];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram11 [8];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram08 [7];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram07 [6];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram06 [5];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram05 [4];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram04 [3];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram03 [2];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram02 [1];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram01 [0];
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
\ No newline at end of file
top/clbv2_ref_design/clbv2_wr_ref_top.ucf 0 → 100644
View file @ d2f24245
# ---------------------------------------------------------------------------`
# -- Clocks/resets
# ---------------------------------------------------------------------------
# -- Local oscillators
NET "clk_20m_vcxo_i" LOC = F22 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- 20MHz VCXO clock
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
#NET "clk_125m_pllref_p_i" LOC = F6 | IOSTANDARD = "LVDS_25"; #Bank 116 -- 125 MHz PLL reference
#NET "clk_125m_pllref_n_i" LOC = F5 | IOSTANDARD = "LVDS_25"; #Bank 116 -- 125 MHz PLL reference
#NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
#TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
#NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
#TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtx_p_i" LOC = D6 | IOSTANDARD = "LVDS_25"; #Bank 116 -- 125 MHz GTX reference
NET "clk_125m_gtx_n_i" LOC = D5 | IOSTANDARD = "LVDS_25"; #Bank 116 -- 125 MHz GTX reference
NET "clk_125m_gtx_p_i" TNM_NET = clk_125m_gtx_p_i;
TIMESPEC TS_clk_125m_gtx_p_i = PERIOD "clk_125m_gtx_p_i" 8 ns HIGH 50%;
NET "clk_125m_gtx_n_i" TNM_NET = clk_125m_gtx_n_i;
TIMESPEC TS_clk_125m_gtx_n_i = PERIOD "clk_125m_gtx_n_i" 8 ns HIGH 50%;
# ---------------------------------------------------------------------------
# -- SPI interface to DACs
# ---------------------------------------------------------------------------
NET "pll25dac_cs_n_o" LOC = A14 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V -- cs1
NET "pll20dac_cs_n_o" LOC = A15 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V -- cs2
NET "plldac_din_o" LOC = A13 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "plldac_sclk_o" LOC = A12 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
# ---------------------------------------------------------------------------
# -- SFP I/O for transceiver
# ---------------------------------------------------------------------------
NET "sfp_txp_o" LOC = A4; #Bank 116
NET "sfp_txn_o" LOC = A3; #Bank 116
NET "sfp_rxp_i" LOC = B6; #Bank 116
NET "sfp_rxn_i" LOC = B5; #Bank 116
NET "sfp_mod_def0_i" LOC = E26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- sfp detect
NET "sfp_mod_def1_b" LOC = J26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- scl
NET "sfp_mod_def2_b" LOC = H26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- sda
NET "sfp_rate_select_o" LOC = G26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_tx_fault_i" LOC = C26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_tx_disable_o" LOC = D26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_los_i" LOC = F25 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
# ---------------------------------------------------------------------------
# -- Onewire interface
# ---------------------------------------------------------------------------
NET "onewire_b" LOC = L23 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
# ---------------------------------------------------------------------------
# -- UART
# ---------------------------------------------------------------------------
#TEST & DEBUG
# Signal uart_txd_o is an output in the design and must be connected to pin 20/12 (RXD_I) of U34 (CP2105GM)
# Signal uart_rxd_i is an input in the design and must be connected to pin 21/13 (TXD_O) of U34 (CP2105GM)
# Rx signals are pulled down so the USB on the CLB and the USB on the G-Board can be OR-ed
NET "uart_rxd_i" LOC = D19 | IOSTANDARD = LVCMOS25 | PULLDOWN; #Bank 15 VCCO - 2.5 V
NET "uart_txd_o" LOC = D20 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "USB_RX2" LOC = C19 | IOSTANDARD = LVCMOS25 | PULLDOWN; #Bank 15 VCCO - 2.5 V
#NET "USB_TX2" LOC = B19 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#USB Connection on Test&Debug Connector (J35)
#NET "USBEXT_RX1" LOC = F14 | IOSTANDARD = LVCMOS33 | PULLDOWN; #Bank 16 VCCO - 3.3 V
#NET "USBEXT_TX1" LOC = F13 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "USBEXT_RX2" LOC = C14 | IOSTANDARD = LVCMOS33 | PULLDOWN; #Bank 16 VCCO - 3.3 V
#NET "USBEXT_TX2" LOC = C13 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
# ---------------------------------------------------------------------------
# -- Flash memory SPI interface
# ---------------------------------------------------------------------------
# flash_sclk_o : out std_logic;
# flash_ncs_o : out std_logic;
# flash_mosi_o : out std_logic;
# flash_miso_i : in std_logic;
# ---------------------------------------------------------------------------
# -- Miscellanous CLBv2 pins
# ---------------------------------------------------------------------------
#NET "GPIO_LED[0]" LOC = C16 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
NET "led_act_o" LOC = C16 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V -- LED D2: blinking indicates that packets are being transferred.
#NET "GPIO_LED[1]" LOC = B16 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[2]" LOC = B17 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[3]" LOC = A17 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[4]" LOC = A18 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[5]" LOC = A19 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
NET "led_link_o" LOC = A19 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V -- LED D7: indicates if the link is up.
NET "reset_i" LOC = E11 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V --Reset
# ---------------------------------------------------------------------------
# -- Digital I/O FMC Pins
# -- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
# -- 10MHz & 1-PPS from external reference (in GrandMaster mode).
# ---------------------------------------------------------------------------
# -- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
# -- external reference input.
NET "dio_clk_p_i" LOC = Y22 | IOSTANDARD=LVDS_25; #CLK1_M2C_P L20
NET "dio_clk_n_i" LOC = AA22 | IOSTANDARD=LVDS_25; #CLK1_M2C_N L22
# -- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
# -- the mezzanine front panel.
NET "dio_p_i[4]" LOC = N21 | IOSTANDARD=LVDS_25; #LA00_P Y11
NET "dio_n_i[4]" LOC = N22 | IOSTANDARD=LVDS_25; #LA00_N AB11
NET "dio_p_i[3]" LOC = P16 | IOSTANDARD=LVDS_25; #LA03_P V7
NET "dio_n_i[3]" LOC = N17 | IOSTANDARD=LVDS_25; #LA03_N W8
NET "dio_p_i[2]" LOC = AB26 | IOSTANDARD=LVDS_25; #LA16_P W12
NET "dio_n_i[2]" LOC = AC26 | IOSTANDARD=LVDS_25; #LA16_N Y12
NET "dio_p_i[1]" LOC = K20 | IOSTANDARD=LVDS_25; #LA20_P R11
NET "dio_n_i[1]" LOC = J20 | IOSTANDARD=LVDS_25; #LA20_N T11
NET "dio_p_i[0]" LOC = P19 | IOSTANDARD=LVDS_25; #LA33_P C19
NET "dio_n_i[0]" LOC = P20 | IOSTANDARD=LVDS_25; #LA33_N A19
# -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
# -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
# -- of I/O (N+1) on the front panel of the mezzanine
NET "dio_p_o[4]" LOC = N18 | IOSTANDARD=LVDS_25; #LA04_P T8
NET "dio_n_o[4]" LOC = M19 | IOSTANDARD=LVDS_25; #LA04_N U8
NET "dio_p_o[3]" LOC = U19 | IOSTANDARD=LVDS_25; #LA07_P U9
NET "dio_n_o[3]" LOC = U20 | IOSTANDARD=LVDS_25; #LA07_N V9
NET "dio_p_o[2]" LOC = W20 | IOSTANDARD=LVDS_25; #LA08_P R9
NET "dio_n_o[2]" LOC = Y21 | IOSTANDARD=LVDS_25; #LA08_N R8
NET "dio_p_o[1]" LOC = M21 | IOSTANDARD=LVDS_25; #LA28_P Y16
NET "dio_n_o[1]" LOC = M22 | IOSTANDARD=LVDS_25; #LA28_N W15
NET "dio_p_o[0]" LOC = N19 | IOSTANDARD=LVDS_25; #LA29_P W17
NET "dio_n_o[0]" LOC = M20 | IOSTANDARD=LVDS_25; #LA29_N Y18
# -- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
# -- panel is configured as an output.
NET "dio_oe_n_o[4]" LOC = AE22 | IOSTANDARD=LVCMOS25; #LA05_P AA6
NET "dio_oe_n_o[3]" LOC = U26 | IOSTANDARD=LVCMOS25; #LA11_P W10
NET "dio_oe_n_o[2]" LOC = AB25 | IOSTANDARD=LVCMOS25; #LA15_N W11
NET "dio_oe_n_o[1]" LOC = N23 | IOSTANDARD=LVCMOS25; #LA24_N Y14
NET "dio_oe_n_o[0]" LOC = P24 | IOSTANDARD=LVCMOS25; #LA30_P V17
# -- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
# -- panel is 50-ohm terminated
NET "dio_term_en_o[4]" LOC = P25 | IOSTANDARD=LVCMOS25; #LA09_N AB7
NET "dio_term_en_o[3]" LOC = R25 | IOSTANDARD=LVCMOS25; #LA09_P Y7
NET "dio_term_en_o[2]" LOC = AF22 | IOSTANDARD=LVCMOS25; #LA05_N AB6
NET "dio_term_en_o[1]" LOC = AF25 | IOSTANDARD=LVCMOS25; #LA06_N AB5
NET "dio_term_en_o[0]" LOC = N24 | IOSTANDARD=LVCMOS25; #LA30_N W18
# -- Two LEDs on the mezzanine panel. Only Top one is currently used - to
# -- blink 1-PPS.
NET "dio_led_top_o" LOC = R21 | IOSTANDARD=LVCMOS25; #LA01_P AA12
NET "dio_led_bot_o" LOC = P21 | IOSTANDARD=LVCMOS25; #LA01_N AB12
# -- I2C interface for accessing FMC EEPROM. Deprecated, was used in
# -- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
NET "dio_scl_b" LOC = D24 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "dio_sda_b" LOC = D23 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
# ---------------------------------------------------------------------------
# -- GPIO connector
# ---------------------------------------------------------------------------
#NET "GPIO[1]" LOC = H8 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[2]" LOC = J8 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[3]" LOC = G9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[4]" LOC = H9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[5]" LOC = F8 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[6]" LOC = G10 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[7]" LOC = F9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[8]" LOC = F10 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[9]" LOC = D9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[10]" LOC = D8 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[11]" LOC = B9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[12]" LOC = C9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[13]" LOC = A9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[14]" LOC = A8 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[15]" LOC = A10 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[16]" LOC = B10 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#FMC SIGNALS CLK LPC
#NET "FMC_CLK0_M2C_P" LOC = Y23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_CLK0_M2C_N" LOC = AA24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_CLK1_M2C_P" LOC = Y22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_CLK1_M2C_N" LOC = AA22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA00_CC_P" LOC = N21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA00_CC_N" LOC = N22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA01_CC_P" LOC = R21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA01_CC_N" LOC = P21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA17_CC_P" LOC = R22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA17_CC_N" LOC = R23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA18_CC_P" LOC = AA23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA18_CC_N" LOC = AB24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#FMC SIGNALS CLK HPC
#NET "FMC_HA00_CC_P" LOC = AC23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA00_CC_N" LOC = AC24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA01_CC_P" LOC = F17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA01_CC_N" LOC = E17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA17_CC_P" LOC = E18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA17_CC_N" LOC = D18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
########################################################
#FMC SIGNALS LPC
#NET "FMC_PRSNT_B" LOC = K21 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#NET "FMC_LA02_P" LOC = H19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA02_N" LOC = G20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA03_P" LOC = P16 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA03_N" LOC = N17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA04_P" LOC = N18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA04_N" LOC = M19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA05_P" LOC = AE22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA05_N" LOC = AF22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 23
#NET "FMC_LA06_P" LOC = AF24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 25
#NET "FMC_LA06_N" LOC = AF25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 27
#NET "FMC_LA07_P" LOC = U19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 29
#NET "FMC_LA07_N" LOC = U20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 31
#NET "FMC_LA08_P" LOC = W20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 33
#NET "FMC_LA08_N" LOC = Y21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 35
#NET "FMC_LA09_P" LOC = R25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 37
#NET "FMC_LA09_N" LOC = P25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 39
#NET "FMC_LA10_P" LOC = U24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA10_N" LOC = U25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA11_P" LOC = U26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA11_N" LOC = V26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA12_P" LOC = R26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA12_N" LOC = P26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA13_P" LOC = AE23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA13_N" LOC = AF23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA14_P" LOC = AD23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA14_N" LOC = AD24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA15_P" LOC = AA25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA15_N" LOC = AB25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA16_P" LOC = AB26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA16_N" LOC = AC26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA19_P" LOC = W23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 38
#NET "FMC_LA19_N" LOC = W24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 40
#NET "FMC_LA20_P" LOC = K20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA20_N" LOC = J20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA21_P" LOC = M25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA21_N" LOC = L25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA22_P" LOC = L19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA22_N" LOC = L20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA23_P" LOC = K25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA23_N" LOC = K26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA24_P" LOC = P23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA24_N" LOC = N23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA25_P" LOC = N26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA25_N" LOC = M26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA26_P" LOC = T22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA26_N" LOC = T23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA27_P" LOC = V23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA27_N" LOC = V24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA28_P" LOC = M21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA28_N" LOC = M22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA29_P" LOC = N19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA29_N" LOC = M20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA30_P" LOC = P24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA30_N" LOC = N24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA31_P" LOC = M24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA31_N" LOC = L24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA32_P" LOC = T20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA32_N" LOC = R20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA33_P" LOC = P19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA33_N" LOC = P20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#FMC SIGNALS HPC
#NET "FMC_HA02_P" LOC = J18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA02_N" LOC = J19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA03_P" LOC = G19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA03_N" LOC = F20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA04_P" LOC = F19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA04_N" LOC = E20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA05_P" LOC = H17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA05_N" LOC = H18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA06_P" LOC = K16 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA06_N" LOC = K17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA07_P" LOC = M17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA07_N" LOC = L18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA08_P" LOC = R16 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA08_N" LOC = R17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA09_P" LOC = R18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA09_N" LOC = P18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA10_P" LOC = T18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA10_N" LOC = T19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA11_P" LOC = U17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA11_N" LOC = T17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA12_P" LOC = AB21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA12_N" LOC = AC21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA13_P" LOC = AD21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA13_N" LOC = AE21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA14_P" LOC = V21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA14_N" LOC = W21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA15_P" LOC = U22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA15_N" LOC = V22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA16_P" LOC = T24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA16_N" LOC = T25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA18_P" LOC = W25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA18_N" LOC = W26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA19_P" LOC = AD26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA19_N" LOC = AE26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA20_P" LOC = AD25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA20_N" LOC = AE25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA21_P" LOC = Y25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA21_N" LOC = Y26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA22_P" LOC = AB22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA22_N" LOC = AC22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA23_P" LOC = L17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA23_N" LOC = K18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#OCTOPUS SMALL
#NET "IIC1_SDA" LOC = J13 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "IIC1_SCL" LOC = H13 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "EN_SCLK" LOC = H12 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "PMT_P[0]" LOC = AD16 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[0]" LOC = AE16 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[1]" LOC = Y17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[1]" LOC = Y18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[2]" LOC = W18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[2]" LOC = W19 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[3]" LOC = AD15 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[3]" LOC = AE15 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[4]" LOC = AA17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[4]" LOC = AA18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[5]" LOC = AA19 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[5]" LOC = AA20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[6]" LOC = AC14 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[6]" LOC = AD14 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[7]" LOC = AC18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[7]" LOC = AD18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[8]" LOC = AB19 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[8]" LOC = AB20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[9]" LOC = AF14 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[9]" LOC = AF15 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[10]" LOC = AB17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[10]" LOC = AC17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[11]" LOC = AD20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[11]" LOC = AE20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA0P" LOC = AE17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA0N" LOC = AF17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA1P" LOC = AE18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA1N" LOC = AF18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA2P" LOC = AF19 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA2N" LOC = AF20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#OCTOPUS LARGE
#NET "IIC2_SDA" LOC = H14 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "IIC2_SCL" LOC = G14 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "EN_LCLK" LOC = H11 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "PMT_P[12]" LOC = AE7 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_N[12]" LOC = AF7 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_P[13]" LOC = AF5 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[13]" LOC = AF4 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[14]" LOC = AD1 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[14]" LOC = AE1 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[15]" LOC = AE8 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_N[15]" LOC = AF8 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_P[16]" LOC = AE6 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[16]" LOC = AE5 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[17]" LOC = AF3 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[17]" LOC = AF2 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[18]" LOC = AC8 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_N[18]" LOC = AD8 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_P[19]" LOC = AD4 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[19]" LOC = AD3 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[20]" LOC = AE3 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[20]" LOC = AE2 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[21]" LOC = AB7 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_N[21]" LOC = AC7 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_P[22]" LOC = AD6 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[22]" LOC = AD5 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[23]" LOC = AB1 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[23]" LOC = AC1 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[24]" LOC = AF10 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_N[24]" LOC = AF9 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_P[25]" LOC = AC4 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[25]" LOC = AC3 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[26]" LOC = AB2 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[26]" LOC = AC2 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[27]" LOC = AC9 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_N[27]" LOC = AD9 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_P[28]" LOC = AA4 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[28]" LOC = AB4 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[29]" LOC = AA3 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[29]" LOC = AA2 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[30]" LOC = AD10 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_N[30]" LOC = AE10 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
\ No newline at end of file
top/clbv2_ref_design/clbv2_wr_ref_top.vhd 0 → 100644
View file @ d2f24245
-------------------------------------------------------------------------------
-- Title : WRPC reference design for KM3NeT Central Logic Board (CLBv2)
-- : based on kintex-7
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : clbv2_wr_ref_top.vhd
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Company : Nikhef
-- Created : 2017-11-08
-- Last update: 2017-11-08
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the CLBv2.
--
-- This is a reference top HDL that instanciates the WR PTP Core together with
-- its peripherals to be run on a CLB card.
--
-- There are two main usecases for this HDL file:
-- * let new users easily synthesize a WR PTP Core bitstream that can be run on
-- reference hardware
-- * provide a reference top HDL file showing how the WRPC can be instantiated
-- in HDL projects.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2017 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_clbv2_pkg.all;
--use work.gn4124_core_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity clbv2_wr_ref_top is
generic (
g_dpram_initf : string := "../../bin/wrpc/wrc_phy16.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_simulation : integer := 0
);
port (
---------------------------------------------------------------------------`
-- Clocks/resets
---------------------------------------------------------------------------
-- Local oscillators
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_gtx_n_i : in std_logic; -- 125 MHz GTX reference
clk_125m_gtx_p_i : in std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_b : inout std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- No Flash memory SPI interface
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Miscellanous CLBv2 pins
---------------------------------------------------------------------------
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
reset_i : in std_logic;
---------------------------------------------------------------------------
-- Digital I/O FMC Pins
-- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
-- 10MHz & 1-PPS from external reference (in GrandMaster mode).
---------------------------------------------------------------------------
-- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
-- external reference input.
dio_clk_p_i : in std_logic;
dio_clk_n_i : in std_logic;
-- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
-- the mezzanine front panel.
dio_n_i : in std_logic_vector(4 downto 0);
dio_p_i : in std_logic_vector(4 downto 0);
-- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
-- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
-- of I/O (N+1) on the front panel of the mezzanine
dio_n_o : out std_logic_vector(4 downto 0);
dio_p_o : out std_logic_vector(4 downto 0);
-- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
-- panel is configured as an output.
dio_oe_n_o : out std_logic_vector(4 downto 0);
-- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
-- panel is 50-ohm terminated
dio_term_en_o : out std_logic_vector(4 downto 0);
-- Two LEDs on the mezzanine panel. Only Top one is currently used - to
-- blink 1-PPS.
dio_led_top_o : out std_logic;
dio_led_bot_o : out std_logic;
-- I2C interface for accessing FMC EEPROM. Deprecated, was used in
-- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
dio_scl_b : inout std_logic;
dio_sda_b : inout std_logic
);
end entity clbv2_wr_ref_top;
architecture top of clbv2_wr_ref_top is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- Number of masters on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 2;
-- Number of slaves on the primary wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
-- Primary Wishbone master(s) offsets
constant c_WB_MASTER_PCIE : integer := 0;
constant c_WB_MASTER_ETHBONE : integer := 1;
-- Primary Wishbone slave(s) offsets
constant c_WB_SLAVE_WRC : integer := 0;
-- sdb header address on primary crossbar
constant c_SDB_ADDRESS : t_wishbone_address := x"00040000";
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_wrc_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00000000"));
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- clock and reset
signal reset_n : std_logic;
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal rst_ref_62m5_n : std_logic;
signal clk_ref_62m5 : std_logic;
signal clk_ref_div2 : std_logic;
signal clk_ext_10m : std_logic;
-- I2C EEPROM
signal eeprom_sda_in : std_logic;
signal eeprom_sda_out : std_logic;
signal eeprom_scl_in : std_logic;
signal eeprom_scl_out : std_logic;
-- SFP
signal sfp_sda_in : std_logic;
signal sfp_sda_out : std_logic;
signal sfp_scl_in : std_logic;
signal sfp_scl_out : std_logic;
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
-- LEDs and GPIO
signal wrc_abscal_txts_out : std_logic;
signal wrc_abscal_rxts_out : std_logic;
signal wrc_pps_out : std_logic;
signal wrc_pps_led : std_logic;
signal wrc_pps_in : std_logic;
signal svec_led : std_logic_vector(15 downto 0);
-- DIO Mezzanine
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
begin -- architecture top
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master)
-----------------------------------------------------------------------------
reset_n <= not reset_i; -- Reset = high active on CLB
cmp_xwrc_board_clbv2 : xwrc_board_clbv2
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => TRUE,
g_dpram_initf => g_dpram_initf,
g_fabric_iface => PLAIN)
port map (
areset_n_i => reset_n,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtx_n_i,
clk_125m_gtp_p_i => clk_125m_gtx_p_i,
clk_10m_ext_i => clk_ext_10m,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_62m5_o => clk_ref_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_62m5_n_o => rst_ref_62m5_n,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
eeprom_sda_i => eeprom_sda_in,
eeprom_sda_o => eeprom_sda_out,
eeprom_scl_i => eeprom_scl_in,
eeprom_scl_o => eeprom_scl_out,
onewire_i => onewire_data,
onewire_oen_o => onewire_oe,
-- Uart
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
abscal_txts_o => wrc_abscal_txts_out,
abscal_rxts_o => wrc_abscal_rxts_out,
pps_ext_i => wrc_pps_in,
pps_p_o => wrc_pps_out,
pps_led_o => wrc_pps_led,
led_link_o => led_link_o,
led_act_o => led_act_o);
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- tri-state onewire access
onewire_b <= '0' when (onewire_oe = '1') else 'Z';
onewire_data <= onewire_b;
------------------------------------------------------------------------------
-- Digital I/O FMC Mezzanine connections
------------------------------------------------------------------------------
gen_dio_iobufs: for I in 0 to 4 generate
U_ibuf: IBUFDS
generic map (
DIFF_TERM => true)
port map (
O => dio_in(i),
I => dio_p_i(i),
IB => dio_n_i(i));
U_obuf : OBUFDS
port map (
I => dio_out(i),
O => dio_p_o(i),
OB => dio_n_o(i));
end generate;
-- Configure Digital I/Os 0 to 3 as outputs
dio_oe_n_o(2 downto 0) <= (others => '0');
-- Configure Digital I/Os 3 and 4 as inputs for external reference
dio_oe_n_o(3) <= '1'; -- for external 1-PPS
dio_oe_n_o(4) <= '1'; -- for external 10MHz clock
-- All DIO connectors are not terminated
dio_term_en_o <= (others => '0');
-- EEPROM I2C tri-states
dio_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
eeprom_sda_in <= dio_sda_b;
dio_scl_b <= '0' when (eeprom_scl_out = '0') else 'Z';
eeprom_scl_in <= dio_scl_b;
-- Div by 2 reference clock to LEMO connector
process(clk_ref_62m5)
begin
if rising_edge(clk_ref_62m5) then
clk_ref_div2 <= not clk_ref_div2;
end if;
end process;
cmp_ibugds_extref: IBUFGDS
generic map (
DIFF_TERM => true)
port map (
O => clk_ext_10m,
I => dio_clk_p_i,
IB => dio_clk_n_i);
wrc_pps_in <= dio_in(3);
dio_out(0) <= wrc_pps_out;
dio_out(1) <= wrc_abscal_rxts_out;
dio_out(2) <= wrc_abscal_txts_out;
-- LEDs
U_Extend_PPS : gc_extend_pulse
generic map (
g_width => 10000000)
port map (
clk_i => clk_ref_62m5,
rst_n_i => rst_ref_62m5_n,
pulse_i => wrc_pps_led,
extended_o => dio_led_top_o);
dio_led_bot_o <= '0';
end architecture top;
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