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White Rabbit core collection
Commit d2f24245 authored by Peter Jansweijer's avatar Peter Jansweijer Committed by Grzegorz Daniluk
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clbv2 reference design files 

added clbv2_ref_design files
added initial clbv2_ref_design ucf file
removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization
removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization, phy16
Merge branch 'peter_clbv2_ref_design' of ohwr.org:hdl-core-lib/wr-cores into peter_clbv2_ref_design
clk_20m_vcxo_i free running clock for reset gen. (thus no need for separate 125 MHz fpga input; remove clk_125m_pllref_p/n_i)
updates kintex7 phy name to reflect new peter_xilinx_phys convention
last commit also needs artix7 support in xwrc_platform_xilinx.vhd
CLBv2: reference clock is 62.5 MHz for 16 bit PHYs. Changed naming convention accordingly.
CLBv2: point proper bram file
CLBv2: implementation (including bmm)
CLBv2 reference design cleaned
CLBv2: updated (hdlmake made) Xilinx ISE project file
parent 6b8136ef
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board/clbv2/Manifest.py 0 → 100644
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files = [
"wr_clbv2_pkg.vhd",
"xwrc_board_clbv2.vhd",
"wrc_board_clbv2.vhd",
]
modules = {
"local" : [
"../common",
]
}
board/clbv2/wr_clbv2_pkg.vhd 0 → 100644
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board/clbv2/wrc_board_clbv2.vhd 0 → 100644
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board/clbv2/xwrc_board_clbv2.vhd 0 → 100644
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platform/xilinx/wr_xilinx_pkg.vhd
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......@@ -99,7 +99,7 @@ package wr_xilinx_pkg is
pad_rxp1_i : in std_logic := '0');
end component;
component wr_gtx_phy_kintex7 is
component wr_gtx_phy_family7 is
generic (
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation : integer := 0);
......@@ -126,4 +126,31 @@ package wr_xilinx_pkg is
rdy_o : out std_logic);
end component;
component wr_gtp_phy_family7 is
generic (
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation : integer := 0);
port (
clk_gtp_i : in std_logic;
tx_out_clk_o : out std_logic;
tx_locked_o : out std_logic;
tx_data_i : in std_logic_vector(15 downto 0);
tx_k_i : in std_logic_vector(1 downto 0);
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_data_o : out std_logic_vector(15 downto 0);
rx_k_o : out std_logic_vector(1 downto 0);
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(4 downto 0);
rst_i : in std_logic;
loopen_i : in std_logic_vector(2 downto 0);
tx_prbs_sel_i : in std_logic_vector(2 downto 0);
pad_txn_o : out std_logic;
pad_txp_o : out std_logic;
pad_rxn_i : in std_logic := '0';
pad_rxp_i : in std_logic := '0';
rdy_o : out std_logic);
end component;
end wr_xilinx_pkg;
platform/xilinx/xwrc_platform_xilinx.vhd
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syn/clbv2_ref_design/Manifest.py 0 → 100644
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target = "xilinx"
action = "synthesis"
syn_device = "xc7k160t"
syn_grade = "-2"
syn_package = "fbg676"
syn_top = "clbv2_wr_ref_top"
syn_project = "clbv2_wr_ref.xise"
syn_tool = "ise"
modules = { "local" : "../../top/clbv2_ref_design/"}
syn/clbv2_ref_design/clbv2_wr_ref.xise 0 → 100644
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top/clbv2_ref_design/Manifest.py 0 → 100644
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fetchto = "../../ip_cores"
files = [
"clbv2_wr_ref_top.vhd",
"clbv2_wr_ref_top.ucf",
"clbv2_wr_ref_top.bmm",
]
modules = {
"local" : [
"../../",
"../../board/clbv2",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
}
top/clbv2_ref_design/clbv2_wr_ref_top.bmm 0 → 100644
View file @ d2f24245
/* FILE : clbv2_wr_ref_top.bmm
* Define a BRAM map for the LM32 memory.
* Run ISE Translate -> "Floorplan Area/IO/Logic (PlanAhead)" once (without this BMM file
* attached to the ISE Project) to find out that there are 16 ramloops and each RAMB36E1
* Note: *THE RAMLOOP ORDER WITHIN A BUS_BLOCK IS VERY IMPORTANT!!!*
* Define ramloop 15 downto 0 and databits 31 downto 0 !!! Otherwise the memory
* content will be swapped and the program fails to execute. Aperently the ramloop
* number and bit definitions are not read by data2mem.
*
*
* Address space LM32 memory
* g_dpram_size = 90112/4 = 22528
* This size is in 32 bit words => byte size = 4 * 22528 = 90112 bytes
*
* ATTENTION PARITY!
* Although the memory is implemented in RAMB36E1 the address same MUST be defined as
* RAMB32 (insetad of RAMB36) since we are NOT using parity! If the address space is
* defined as RAMB36 then data2mem is expecting an extra nibble for each 32 bit instruction
* in the ".elf" file and since this nibble is not provided, the ramblocks will be filled
* such that a nibble shift is accumulating in the data.
* Note that this can be examined using the command
* "data2mem -bm clbv2_wr_ref_top_bd.bmm -bt clbv2_wr_ref_top_elf.bit -d > dump.txt"
*
* ATTENTION Xilinx Synthesis
* XST implements the 22K * 32 bit as:
* 22 blocks of 1K * 32 bits
*
****************************************************************************************/
ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF]
ADDRESS_RANGE RAMB32
BUS_BLOCK
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram38 [31];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram37 [30];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram36 [29];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram35 [28];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram34 [27];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram33 [26];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram32 [25];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram31 [24];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram28 [23];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram27 [22];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram26 [21];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram25 [20];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram24 [19];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram23 [18];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram22 [17];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram21 [16];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram18 [15];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram17 [14];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram16 [13];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram15 [12];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram14 [11];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram13 [10];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram12 [9];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram11 [8];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram08 [7];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram07 [6];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram06 [5];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram05 [4];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram04 [3];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram03 [2];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram02 [1];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram01 [0];
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
\ No newline at end of file
top/clbv2_ref_design/clbv2_wr_ref_top.ucf 0 → 100644
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top/clbv2_ref_design/clbv2_wr_ref_top.vhd 0 → 100644
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