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White Rabbit core collection
Commit d4b42139 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: Eradicate INT from wishbone records and peripheral ports.

parent 1e01c22d
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Showing with 45 additions and 46 deletions
etherbone-core @ 79a60811
Subproject commit 8489445985ff2afe6c72712014a92a271869f20a
Subproject commit 79a6081166043ee24d835cbe7c5e5632dacad1f6
general-cores @ 61ca3f49
Subproject commit 5205d9754b1e0887df5914a47f8aa745e4f3c2fe
Subproject commit 61ca3f49b61233e922f4c2c034e1b62728c124bf
gn4124-core @ e7cd73db
Subproject commit 9b9625bb4270114266cd357f199d649f3d799f04
Subproject commit e7cd73db41ba056ed4b27731c21a3b2aa53eaa51
vme64x-core @ a120e226
Subproject commit fa34d06e35ca0bfad8eac24aa51713e81639da64
Subproject commit a120e2262e1cb23fa611dddb7fa3727b520a125c
modules/fabric/xwrf_loopback/xwrf_loopback.vhd
View file @ d4b42139
......@@ -120,7 +120,7 @@ begin
regs_o => regs_fromwb);
wb_out.rty <= '0';
wb_out.err <= '0';
wb_out.int <= '0';
-------------------------------------------
FRAME_FIFO: generic_sync_fifo
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ d4b42139
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-26
-- Last update: 2017-02-20
-- Last update: 2018-03-08
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -773,7 +773,6 @@ begin
wb_out.stall <= '0';
wb_out.rty <= '0';
wb_out.err <= '0';
wb_out.int <= '0';
regs_towb <= regs_towb_ep or regs_towb_tsu or regs_towb_rpath or regs_towb_tpath or regs_towb_dmtd;
......
modules/wr_endpoint/xwr_endpoint.vhd
View file @ d4b42139
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-26
-- Last update: 2017-02-20
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -433,7 +433,6 @@ begin
wb_o.err <= '0';
wb_o.rty <= '0';
wb_o.int <= '0';
-- Record-based PHY connections, depending on 8/16-bit PCS
......
modules/wr_mini_nic/wr_mini_nic.vhd
View file @ d4b42139
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk, Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-07-26
-- Last update: 2017-02-03
-- Last update: 2018-03-19
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -119,7 +119,12 @@ entity wr_mini_nic is
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic
-------------------------------------------------------------------------------
-- Interrupt output
-------------------------------------------------------------------------------
int_o : out std_logic
);
end wr_mini_nic;
......@@ -772,7 +777,7 @@ begin -- behavioral
wb_we_i => wb_out.we,
wb_ack_o => wb_in.ack,
wb_stall_o => wb_in.stall,
wb_int_o => wb_int_o,
wb_int_o => int_o,
regs_i => regs_in,
regs_o => regs_out,
tx_ts_read_ack_o => open,
......@@ -785,7 +790,6 @@ begin -- behavioral
wb_in.err <= '0';
wb_in.rty <= '0';
wb_in.int <= '0';
--TRIG0(0) <= regs_out.mcr_rx_en_o;
--TRIG0(1) <= rx_fifo_empty;
......
modules/wr_mini_nic/xwr_mini_nic.vhd
View file @ d4b42139
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk, Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-07-26
-- Last update: 2017-02-03
-- Last update: 2018-03-19
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -78,7 +78,13 @@ entity xwr_mini_nic is
-------------------------------------------------------------------------------
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out
wb_o : out t_wishbone_slave_out;
-------------------------------------------------------------------------------
-- Interrupt output
-------------------------------------------------------------------------------
int_o : out std_logic
);
end xwr_mini_nic;
......@@ -127,7 +133,7 @@ architecture wrapper of xwr_mini_nic is
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic);
int_o : out std_logic);
end component;
begin -- wrapper
......@@ -175,7 +181,7 @@ begin -- wrapper
wb_dat_o => wb_o.dat,
wb_ack_o => wb_o.ack,
wb_stall_o => wb_o.stall,
wb_int_o => wb_o.int);
int_o => int_o);
wb_o.err <= '0';
......
modules/wr_pps_gen/wr_pps_gen.vhd
View file @ d4b42139
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN (BE-CO-HT)
-- Created : 2010-09-02
-- Last update: 2017-02-20
-- Last update: 2018-03-08
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -500,7 +500,6 @@ begin -- behavioral
-- drive unused signals
wb_out.rty <= '0';
wb_out.stall <= '0';
wb_out.int <= '0';
wb_out.err <= '0';
-- start the adjustment upon write of 1 to CNT_ADJ bit
......
modules/wr_pps_gen/xwr_pps_gen.vhd
View file @ d4b42139
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN (BE-CO-HT)
-- Created : 2010-09-02
-- Last update: 2017-02-20
-- Last update: 2018-03-08
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -157,6 +157,5 @@ begin -- behavioral
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.int <= '0';
end behavioral;
modules/wr_softpll_ng/wr_softpll_ng.vhd
View file @ d4b42139
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-29
-- Last update: 2017-02-20
-- Last update: 2018-03-19
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -149,7 +149,7 @@ entity wr_softpll_ng is
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
irq_o : out std_logic;
debug_o : out std_logic_vector(5 downto 0);
-- Debug FIFO readout interrupt
......@@ -296,8 +296,6 @@ architecture rtl of wr_softpll_ng is
signal rcer_int : std_logic_vector(g_num_ref_inputs-1 downto 0);
signal ocer_int : std_logic_vector(g_num_outputs-1 downto 0);
signal wb_irq_out : std_logic;
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
signal regs_in : t_SPLL_out_registers;
......@@ -581,7 +579,7 @@ begin -- rtl
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_int_o => wb_irq_out,
wb_int_o => irq_o,
wb_stall_o => open,
regs_o => regs_in,
......@@ -593,7 +591,6 @@ begin -- rtl
wb_out.err <= '0';
wb_out.rty <= '0';
wb_out.stall <= '0';
wb_out.int <= '0';
p_ocer_rcer_regs : process(clk_sys_i)
begin
......@@ -797,8 +794,6 @@ begin -- rtl
dac_out_sel_o <= regs_in.dac_main_dac_sel_o;
dac_out_load_o <= regs_in.dac_main_value_wr_o;
wb_irq_o <= wb_irq_out;
regs_out.al_cr_required_i <= (others => '0');
regs_out.csr_dbg_supported_i <= '0';
regs_out.f_dmtd_valid_i <= '0';
......
modules/wr_softpll_ng/xwr_softpll_ng.vhd
View file @ d4b42139
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-29
-- Last update: 2017-02-20
-- Last update: 2018-03-19
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -128,6 +128,8 @@ entity xwr_softpll_ng is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o: out std_logic;
debug_o : out std_logic_vector(5 downto 0);
dbg_fifo_irq_o : out std_logic
);
......@@ -181,7 +183,7 @@ architecture wrapper of xwr_softpll_ng is
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
irq_o : out std_logic;
debug_o : out std_logic_vector(5 downto 0);
dbg_fifo_irq_o : out std_logic);
end component;
......@@ -234,7 +236,7 @@ begin -- behavioral
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
wb_irq_o => slave_o.int,
irq_o => int_o,
debug_o => debug_o,
dbg_fifo_irq_o => dbg_fifo_irq_o);
......
modules/wr_tlu/tlu.vhd
View file @ d4b42139
......@@ -351,7 +351,6 @@ begin -- behavioral
-----------------------------------------------------------------------------
-- WB Interface
-----------------------------------------------------------------------------
ctrl_slave_o.int <= '0';
ctrl_slave_o.rty <= '0';
ctrl_slave_o.stall <= r_c_stall;
ctrl_slave_o.ack <= r_c_ack;
......
modules/wrc_core/wr_core.vhd
View file @ d4b42139
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-02
-- Last update: 2017-05-29
-- Last update: 2018-03-19
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -677,6 +677,8 @@ begin
slave_i => spll_wb_in,
slave_o => spll_wb_out,
int_o => softpll_irq,
debug_o => open);
clk_fb(0) <= clk_ref_i;
......@@ -704,8 +706,6 @@ begin
tm_clk_aux_locked_o <= spll_out_locked(g_aux_clks downto 1);
end generate;
softpll_irq <= spll_wb_out.int;
-----------------------------------------------------------------------------
-- Endpoint
-----------------------------------------------------------------------------
......@@ -1073,7 +1073,6 @@ begin
secbar_master_i(7).stall <= aux_stall_i;
secbar_master_i(7).err <= '0';
secbar_master_i(7).rty <= '0';
secbar_master_i(7).int <= '0';
--secbar_master_i(6).err <= '0';
--secbar_master_i(5).err <= '0';
......
modules/wrc_core/wrc_periph.vhd
View file @ d4b42139
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-04-04
-- Last update: 2017-04-25
-- Last update: 2018-03-08
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -414,7 +414,6 @@ begin
slave_o(0).err <= '0';
slave_o(0).rty <= '0';
slave_o(0).int <= '0';
--------------------------------------
-- UART
......
modules/wrc_core/wrcore_pkg.vhd
View file @ d4b42139
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-05-11
-- Last update: 2017-05-29
-- Last update: 2018-03-19
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -135,7 +135,8 @@ package wrcore_pkg is
txtsu_stb_i : in std_logic;
txtsu_ack_o : out std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
wb_o : out t_wishbone_slave_out;
int_o : out std_logic);
end component;
-----------------------------------------------------------------------------
......@@ -346,12 +347,13 @@ package wrcore_pkg is
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
debug_o : out std_logic_vector(5 downto 0);
dbg_fifo_irq_o : out std_logic);
end component;
constant cc_unused_master_in : t_wishbone_master_in :=
('1', '0', '0', '0', '0', cc_dummy_data);
('1', '0', '0', '0', cc_dummy_data);
-----------------------------------------------------------------------------
-- Public WR component definitions
......
modules/wrc_core/xwr_core.vhd
View file @ d4b42139
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-02
-- Last update: 2017-05-29
-- Last update: 2018-03-08
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -441,8 +441,6 @@ begin
timestamps_o.port_id(5) <= '0';
slave_o.int <= '0';
wrf_snk_o.rty <= '0';
end struct;
modules/wrc_core/xwrc_diags_wb.vhd
View file @ d4b42139
......@@ -124,7 +124,6 @@ begin
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.int <= '0';
end syn;
......
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