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White Rabbit core collection
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White Rabbit core collection
Commits
d7e0019f
Commit
d7e0019f
authored
Mar 11, 2019
by
Grzegorz Daniluk
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rename wrsw_txtsu to wr_txtsu after importing from wr-switch-hdl repo
parent
ad0b15e7
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6 changed files
with
12 additions
and
12 deletions
+12
-12
Manifest.py
modules/wr_txtsu/Manifest.py
+3
-0
wr_txtsu.wb
modules/wr_txtsu/wr_txtsu.wb
+2
-2
wr_txtsu_pkg.vhd
modules/wr_txtsu/wr_txtsu_pkg.vhd
+2
-2
wr_txtsu_wb.vhd
modules/wr_txtsu/wr_txtsu_wb.vhd
+0
-0
xwr_txtsu.vhd
modules/wr_txtsu/xwr_txtsu.vhd
+5
-5
Manifest.py
modules/wrsw_txtsu/Manifest.py
+0
-3
No files found.
modules/wr_txtsu/Manifest.py
0 → 100644
View file @
d7e0019f
files
=
[
"xwr_txtsu.vhd"
,
"wr_txtsu_wb.vhd"
,
"wr_txtsu_pkg.vhd"
]
modules/wr
sw_txtsu/wrsw
_txtsu.wb
→
modules/wr
_txtsu/wr
_txtsu.wb
View file @
d7e0019f
...
...
@@ -4,7 +4,7 @@ peripheral {
name = "Shared TX Timestamping Unit (TXTSU)";
prefix="txtsu";
hdl_entity="wr
sw
_txtsu_wb";
hdl_entity="wr_txtsu_wb";
-- TXTSU shared FIFO
...
...
@@ -78,4 +78,4 @@ peripheral {
trigger = LEVEL_1;
};
};
\ No newline at end of file
};
modules/wr
sw_txtsu/wrsw
_txtsu_pkg.vhd
→
modules/wr
_txtsu/wr
_txtsu_pkg.vhd
View file @
d7e0019f
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
package
wr
sw
_txtsu_pkg
is
package
wr_txtsu_pkg
is
-- t_txtsu_timestamp was here, but now it's moved to wr_endpoint_pkg.
end
wr
sw
_txtsu_pkg
;
end
wr_txtsu_pkg
;
modules/wr
sw_txtsu/wrsw
_txtsu_wb.vhd
→
modules/wr
_txtsu/wr
_txtsu_wb.vhd
View file @
d7e0019f
File moved
modules/wr
sw_txtsu/xwrsw
_txtsu.vhd
→
modules/wr
_txtsu/xwr
_txtsu.vhd
View file @
d7e0019f
...
...
@@ -2,7 +2,7 @@
-- Title : TX Timestamping Unit
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : xwr
sw
_txtsu.vhd
-- File : xwr_txtsu.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
...
...
@@ -57,9 +57,9 @@ library work;
use
work
.
wishbone_pkg
.
all
;
use
work
.
endpoint_pkg
.
all
;
use
work
.
wr
sw
_txtsu_pkg
.
all
;
use
work
.
wr_txtsu_pkg
.
all
;
entity
xwr
sw
_tx_tsu
is
entity
xwr_tx_tsu
is
generic
(
g_num_ports
:
integer
:
=
10
;
...
...
@@ -92,10 +92,10 @@ entity xwrsw_tx_tsu is
end
xwr
sw
_tx_tsu
;
end
xwr_tx_tsu
;
architecture
syn
of
xwr
sw
_tx_tsu
is
architecture
syn
of
xwr_tx_tsu
is
component
wrsw_txtsu_wb
...
...
modules/wrsw_txtsu/Manifest.py
deleted
100644 → 0
View file @
ad0b15e7
files
=
[
"xwrsw_txtsu.vhd"
,
"wrsw_txtsu_wb.vhd"
,
"wrsw_txtsu_pkg.vhd"
]
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