Skip to content

W
White Rabbit core collection
Commit d82c02f0 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
Browse files
Options

modules: regenerate wishbone Slave interfaces with updated wbgen 

Sometimes *.wb file had to be updated to produce the same result as used till
now. Earlier wbgen2 had a problem accepting _align_ for the first field in a
register. The bug was fixed, but we want to keep the alignment the old way
(already used in the software). Hence I had to delete some of the _align_
directives.
parent 9297c275
Hide whitespace changes
Inline Side-by-side
Showing with 48 additions and 53 deletions
modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
View file @ d82c02f0
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_pcs_tbi_mdio_wb.vhd
-- Author : auto-generated by wbgen2 from pcs_regs.wb
-- Created : Tue Aug 4 10:01:08 2015
-- Created : Tue Aug 4 12:12:43 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
......
modules/wr_endpoint/ep_registers_pkg.vhd
View file @ d82c02f0
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Fri Jan 31 09:58:14 2014
-- Created : Thu Aug 6 15:57:28 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -214,20 +214,20 @@ end package;
package body ep_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
if x = '1' then
return '1';
else
return x;
end if;
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):=x(i);
tmp(i):= '0';
end if;
end loop;
return tmp;
......
modules/wr_endpoint/ep_wishbone_controller.vhd
View file @ d82c02f0
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Fri Jan 31 09:58:14 2014
-- Created : Thu Aug 6 15:57:28 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -218,7 +218,7 @@ begin
ep_ecr_rx_en_int <= wrdata_reg(7);
end if;
rddata_reg(4 downto 0) <= ep_ecr_portid_int;
rddata_reg(5) <= 'X';
rddata_reg(5) <= '0';
rddata_reg(6) <= ep_ecr_tx_en_int;
rddata_reg(7) <= ep_ecr_rx_en_int;
rddata_reg(24) <= regs_i.ecr_feat_vlan_i;
......@@ -258,9 +258,9 @@ begin
end if;
rddata_reg(0) <= ep_tscr_en_txts_int;
rddata_reg(1) <= ep_tscr_en_rxts_int;
rddata_reg(2) <= 'X';
rddata_reg(2) <= '0';
rddata_reg(3) <= ep_tscr_cs_done_sync1;
rddata_reg(4) <= 'X';
rddata_reg(4) <= '0';
rddata_reg(5) <= regs_i.tscr_rx_cal_result_i;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
......
modules/wr_endpoint/ep_wishbone_controller.wb
View file @ d82c02f0
......@@ -276,7 +276,6 @@ peripheral {
11: unqualified port - passes all traffic regardless of VLAN configuration";
type = SLV;
size = 2;
align = 2;
prefix = "Qmode";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
......
modules/wr_mini_nic/mini_nic.wb
View file @ d82c02f0
......@@ -94,7 +94,6 @@ peripheral {
field {
name = "TX DMA buffer address";
size = 24;
align = 2;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
......@@ -112,7 +111,6 @@ peripheral {
field {
name = "RX DMA buffer address";
size = 24;
align = 2;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
......@@ -128,7 +126,6 @@ peripheral {
field {
name = "RX available words";
size = 24;
align = 2;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
......@@ -146,7 +143,6 @@ peripheral {
field {
name = "RX available words";
size = 24;
align = 2;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
......
modules/wr_mini_nic/minic_wb_slave.vhd
View file @ d82c02f0
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wb_slave.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Thu Mar 7 14:45:52 2013
-- Created : Thu Aug 6 16:03:26 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......
modules/wr_mini_nic/minic_wbgen2_pkg.vhd
View file @ d82c02f0
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Thu Mar 7 14:45:52 2013
-- Created : Thu Aug 6 16:03:26 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -97,20 +97,20 @@ end package;
package body minic_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
if x = '1' then
return '1';
else
return x;
end if;
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):=x(i);
tmp(i):= '0';
end if;
end loop;
return tmp;
......
modules/wr_pps_gen/pps_gen_regs.h
View file @ d82c02f0
......@@ -3,7 +3,7 @@
* File : pps_gen_regs.h
* Author : auto-generated by wbgen2 from pps_gen_wb.wb
* Created : Fri Jul 26 15:09:09 2013
* Created : Thu Aug 6 16:03:49 2015
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
......
modules/wr_pps_gen/pps_gen_wb.vhd
View file @ d82c02f0
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : pps_gen_wb.vhd
-- Author : auto-generated by wbgen2 from pps_gen_wb.wb
-- Created : Mon Aug 5 12:04:01 2013
-- Created : Thu Aug 6 16:03:49 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
......
modules/wr_si57x_interface/si570_if_wb.vhd
View file @ d82c02f0
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : si570_if_wb.vhd
-- Author : auto-generated by wbgen2 from si570_if_wb.wb
-- Created : Tue Mar 19 13:39:45 2013
-- Created : Thu Aug 6 16:04:41 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE si570_if_wb.wb
......
modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
View file @ d82c02f0
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : si570_if_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from si570_if_wb.wb
-- Created : Tue Mar 19 13:39:45 2013
-- Created : Thu Aug 6 16:04:41 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE si570_if_wb.wb
......@@ -60,20 +60,20 @@ end package;
package body si570_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
if x = '1' then
return '1';
else
return x;
end if;
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):=x(i);
tmp(i):= '0';
end if;
end loop;
return tmp;
......
modules/wr_softpll_ng/spll_wb_slave.vhd
View file @ d82c02f0
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wb_slave.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Tue Jul 15 17:31:20 2014
-- Created : Thu Aug 6 16:05:11 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
View file @ d82c02f0
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Tue Jul 15 17:31:20 2014
-- Created : Thu Aug 6 16:05:11 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -161,10 +161,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):=x(i);
tmp(i):= '0';
end if;
end loop;
return tmp;
......
modules/wrc_core/wrc_syscon_pkg.vhd
View file @ d82c02f0
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Wed Sep 25 14:35:39 2013
-- Created : Thu Aug 6 16:05:38 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -128,20 +128,20 @@ end package;
package body sysc_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
if x = '1' then
return '1';
else
return x;
end if;
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):=x(i);
tmp(i):= '0';
end if;
end loop;
return tmp;
......
modules/wrc_core/wrc_syscon_regs.h
View file @ d82c02f0
......@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Wed Sep 25 14:35:39 2013
* Created : Thu Aug 6 16:05:39 2015
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......
modules/wrc_core/wrc_syscon_wb.vhd
View file @ d82c02f0
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_wb.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Wed Sep 25 14:35:39 2013
-- Created : Thu Aug 6 16:05:38 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment