Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
30
Issues
30
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Schedules
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit core collection
Commits
dcf516c0
Commit
dcf516c0
authored
Dec 13, 2017
by
Peter Jansweijer
Committed by
Grzegorz Daniluk
Dec 13, 2017
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
forward family7 gtx and gtp tx_locked_o signal to entity port
parent
1e25970a
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
8 additions
and
2 deletions
+8
-2
wr_xilinx_pkg.vhd
platform/xilinx/wr_xilinx_pkg.vhd
+1
-0
xwrc_platform_xilinx.vhd
platform/xilinx/xwrc_platform_xilinx.vhd
+7
-2
No files found.
platform/xilinx/wr_xilinx_pkg.vhd
View file @
dcf516c0
...
...
@@ -40,6 +40,7 @@ package wr_xilinx_pkg is
sfp_tx_disable_o
:
out
std_logic
;
clk_62m5_sys_o
:
out
std_logic
;
clk_125m_ref_o
:
out
std_logic
;
clk_ref_locked_o
:
out
std_logic
;
clk_62m5_dmtd_o
:
out
std_logic
;
pll_locked_o
:
out
std_logic
;
clk_10m_ext_o
:
out
std_logic
;
...
...
platform/xilinx/xwrc_platform_xilinx.vhd
View file @
dcf516c0
...
...
@@ -122,6 +122,7 @@ entity xwrc_platform_xilinx is
-- PLL outputs
clk_62m5_sys_o
:
out
std_logic
;
clk_125m_ref_o
:
out
std_logic
;
clk_ref_locked_o
:
out
std_logic
;
clk_62m5_dmtd_o
:
out
std_logic
;
pll_locked_o
:
out
std_logic
;
clk_10m_ext_o
:
out
std_logic
;
...
...
@@ -945,6 +946,7 @@ begin -- architecture rtl
signal
clk_ref
:
std_logic
;
signal
clk_125m_gtx_buf
:
std_logic
;
signal
clk_ref_locked
:
std_logic
;
begin
...
...
@@ -992,9 +994,10 @@ begin -- architecture rtl
pad_rxn_i
=>
sfp_rxn_i
,
pad_rxp_i
=>
sfp_rxp_i
,
tx_locked_o
=>
open
);
tx_locked_o
=>
clk_ref_locked
);
clk_125m_ref_o
<=
clk_ref
;
clk_ref_locked_o
<=
clk_ref_locked
;
phy16_o
.
ref_clk
<=
clk_ref
;
phy16_o
.
sfp_tx_fault
<=
sfp_tx_fault_i
;
phy16_o
.
sfp_los
<=
sfp_los_i
;
...
...
@@ -1012,6 +1015,7 @@ begin -- architecture rtl
signal
clk_ref
:
std_logic
;
signal
clk_125m_gtp_buf
:
std_logic
;
signal
clk_ref_locked
:
std_logic
;
begin
...
...
@@ -1059,9 +1063,10 @@ begin -- architecture rtl
pad_rxn_i
=>
sfp_rxn_i
,
pad_rxp_i
=>
sfp_rxp_i
,
tx_locked_o
=>
open
);
tx_locked_o
=>
clk_ref_locked
);
clk_125m_ref_o
<=
clk_ref
;
clk_ref_locked_o
<=
clk_ref_locked
;
phy16_o
.
ref_clk
<=
clk_ref
;
phy16_o
.
sfp_tx_fault
<=
sfp_tx_fault_i
;
phy16_o
.
sfp_los
<=
sfp_los_i
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment