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White Rabbit core collection
Commit dd7afa34 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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Vivado top level & project TCL for SIS8300KU reference design

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top/sis8300ku_ref_design/bitstream.xdc 0 → 100644
View file @ dd7afa34
# SPI Flash Programming
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]
set_property CONFIG_MODE SPIx1 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
set_property CONFIG_VOLTAGE 2.5 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
top/sis8300ku_ref_design/clocks.xdc 0 → 100644
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top/sis8300ku_ref_design/pins.xdc 0 → 100644
View file @ dd7afa34
###################################################
## Clocks
###################################################
set_property PACKAGE_PIN P5 [get_ports clk_mtca_n]
set_property PACKAGE_PIN P6 [get_ports clk_mtca_p]
###################################################
## PCIe
###################################################
set_property PACKAGE_PIN N23 [get_ports pcie_rst_n]
set_property IOSTANDARD LVCMOS25 [get_ports pcie_rst_n]
set_property PULLUP true [get_ports pcie_rst_n]
set_property PACKAGE_PIN F2 [get_ports {pcie_rxp_i[0]}]
set_property PACKAGE_PIN F1 [get_ports {pcie_rxn_i[0]}]
set_property PACKAGE_PIN G4 [get_ports {pcie_txp_o[0]}]
set_property PACKAGE_PIN G3 [get_ports {pcie_txn_o[0]}]
set_property PACKAGE_PIN H2 [get_ports {pcie_rxp_i[1]}]
set_property PACKAGE_PIN H1 [get_ports {pcie_rxn_i[1]}]
set_property PACKAGE_PIN J4 [get_ports {pcie_txp_o[1]}]
set_property PACKAGE_PIN J3 [get_ports {pcie_txn_o[1]}]
set_property PACKAGE_PIN K2 [get_ports {pcie_rxp_i[2]}]
set_property PACKAGE_PIN K1 [get_ports {pcie_rxn_i[2]}]
set_property PACKAGE_PIN L4 [get_ports {pcie_txp_o[2]}]
set_property PACKAGE_PIN L3 [get_ports {pcie_txn_o[2]}]
set_property PACKAGE_PIN M2 [get_ports {pcie_rxp_i[3]}]
set_property PACKAGE_PIN M1 [get_ports {pcie_rxn_i[3]}]
set_property PACKAGE_PIN N4 [get_ports {pcie_txp_o[3]}]
set_property PACKAGE_PIN N3 [get_ports {pcie_txn_o[3]}]
###################################################
## SFF optical links
###################################################
## Optical links (white rabbit)
set_property PACKAGE_PIN AD5 [get_ports mgtclk1_224_n_i]
set_property PACKAGE_PIN AD6 [get_ports mgtclk1_224_p_i]
## I2C + Present sff1
set_property PACKAGE_PIN AF30 [get_ports sfp1_scl_b]
set_property IOSTANDARD LVCMOS18 [get_ports sfp1_scl_b]
set_property PACKAGE_PIN AG30 [get_ports sfp1_sda_b]
set_property IOSTANDARD LVCMOS18 [get_ports sfp1_sda_b]
set_property PACKAGE_PIN AK33 [get_ports sfp1_prsnt_n_i]
set_property IOSTANDARD LVCMOS12 [get_ports sfp1_prsnt_n_i]
set_property PULLUP true [get_ports sfp1_prsnt_n_i]
## Link 1
set_property PACKAGE_PIN AK2 [get_ports sfp1_rxp_i]
set_property PACKAGE_PIN AK1 [get_ports sfp1_rxn_i]
set_property PACKAGE_PIN AL4 [get_ports sfp1_txp_o]
set_property PACKAGE_PIN AL3 [get_ports sfp1_txn_o]
###################################################
## Analog Digital Converter
###################################################
###################################################
## White Rabbit
###################################################
## Bank 64 voltage = 2.5V
set_property PACKAGE_PIN AG11 [get_ports clk_20m_vcxo_i]
set_property IOSTANDARD LVCMOS25 [get_ports clk_20m_vcxo_i]
# Bank 48 voltage = 1.8V
set_property PACKAGE_PIN AA20 [get_ports wr_dac_din_o]
set_property IOSTANDARD LVCMOS18 [get_ports wr_dac_din_o]
# Bank 47 voltage = 1.8v
set_property PACKAGE_PIN AB20 [get_ports wr_dac_sclk_o]
set_property IOSTANDARD LVCMOS18 [get_ports wr_dac_sclk_o]
# Bank 47 voltage = 1.8v
set_property PACKAGE_PIN AB21 [get_ports wr_dac_pll25_sync_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports wr_dac_pll25_sync_n_o]
# Bank 47 voltage = 1.8v
set_property PACKAGE_PIN AC21 [get_ports wr_dac_pll20_sync_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports wr_dac_pll20_sync_n_o]
###################################################
## diverse
###################################################
## LED signals
# Bank 64 voltage = 2.5V
set_property PACKAGE_PIN AM11 [get_ports led_serial_o]
set_property IOSTANDARD LVCMOS25 [get_ports led_serial_o]
#3 WATCHDOG signal
# Bank 47 voltage = 1.8V
set_property PACKAGE_PIN AC22 [get_ports fpga_watchdog_o]
set_property IOSTANDARD LVCMOS18 [get_ports fpga_watchdog_o]
top/sis8300ku_ref_design/project.tcl 0 → 100644
View file @ dd7afa34
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top/sis8300ku_ref_design/sis8300ku_led_interface.vhd 0 → 100644
View file @ dd7afa34
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sis8300ku_led_interface is
generic (
FREQ : integer := 62500000; -- in Hz
BLINK_MS : integer := 400 -- in ms
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
frontpanel_a_i : in std_logic_vector(1 downto 0);
frontpanel_u_i : in std_logic_vector(1 downto 0);
frontpanel_l1_i : in std_logic_vector(1 downto 0);
frontpanel_l2_i : in std_logic_vector(1 downto 0);
smd_ready_i : in std_logic;
smds_i : in std_logic_vector(7 downto 0);
led_serial_o : out std_logic
);
end entity ; -- led_interface
architecture rtl of sis8300ku_led_interface is
component sis8300ku_led_translator is
generic (
FREQ : integer := 62500000; -- in Hz
BLINK_MS : integer := 400 -- in ms
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
led_on_i : in std_logic;
led_blink_i : in std_logic;
led_o : out std_logic
);
end component ; -- led_translator
component sn74lv8153_interface is
generic (
g_clock_freq : integer := 62500000
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
d_i : in std_logic_vector (15 downto 0);
serial_o : out std_logic
);
end component; -- sn74lv8153_interface
type t_leds is array(integer range <>) of std_logic_vector(1 downto 0);
signal rst_n : std_logic := '0';
signal s_leds_fp : t_leds(0 to 3) := (others => (others => '0'));
signal s_leds : std_logic_vector(15 downto 0) := (others => '0');
begin
b_data_smd : s_leds(7 downto 0) <= smds_i;
b_leds_fp_a : s_leds_fp(0) <= frontpanel_a_i;
b_leds_fp_u : s_leds_fp(1) <= frontpanel_u_i;
b_leds_fp_l1 : s_leds_fp(2) <= frontpanel_l1_i;
b_leds_fp_l2 : s_leds_fp(3) <= frontpanel_l2_i;
gen_led_frontpanel : for i in 0 to 3 generate
u_led_translator : sis8300ku_led_translator
generic map (
FREQ => FREQ,
BLINK_MS => BLINK_MS
)
port map (
clk_i => clk_i,
rst_i => rst_i,
led_on_i => s_leds_fp(i)(0),
led_blink_i => s_leds_fp(i)(1),
led_o => s_leds(8 + i)
);
end generate ; -- gen_led_frontpanel
b_data_empty : s_leds(14 downto 12) <= (others => '0');
b_data_ready : s_leds(15) <= smd_ready_i;
p_rst_n : rst_n <= not rst_i;
u_interface : sn74lv8153_interface
generic map (
g_clock_freq => FREQ
)
port map (
clk_i => clk_i,
rst_n_i => rst_n,
d_i => s_leds,
serial_o => led_serial_o
);
end architecture ; -- rtl
top/sis8300ku_ref_design/sis8300ku_led_translator.vhd 0 → 100644
View file @ dd7afa34
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sis8300ku_led_translator is
generic (
FREQ : integer := 62500000; -- in Hz
BLINK_MS : integer := 400 -- in ms
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
led_on_i : in std_logic;
led_blink_i : in std_logic;
led_o : out std_logic
);
end entity ; -- led_translator
architecture rtl of sis8300ku_led_translator is
type t_state is (ST_RESET, ST_OFF, ST_ON);
signal s_state_a, s_state : t_state := ST_RESET;
signal s_rst_cnt : std_logic := '0';
signal cnt_c, cnt_c_a : unsigned(31 downto 0) := (others => '0');
constant c_ZERO : unsigned(cnt_c'range) := (others => '0');
constant c_PERIOD_ON : unsigned(cnt_c'range) := to_unsigned( 6250000, cnt_c'length); -- 1 * FREQ * BLINK_MS / 4000 - 1;
constant c_PERIOD_OFF : unsigned(cnt_c'range) := to_unsigned(18750000, cnt_c'length); -- 3 * FREQ * BLINK_MS / 4000 - 1;
begin
crnt_state : process( clk_i )
begin
if rising_edge(clk_i) then
if rst_i = '1' then
s_state <= ST_RESET;
else
s_state <= s_state_a;
end if;
end if;
end process ; -- crnt_state
next_state : process( s_state, led_blink_i, led_on_i, cnt_c )
begin
s_state_a <= s_state;
s_rst_cnt <= '0';
case s_state is
when ST_RESET =>
s_state_a <= ST_OFF;
s_rst_cnt <= '1';
when ST_OFF =>
if (led_blink_i = '1' or (led_blink_i = '0' and led_on_i = '1')) and cnt_c = c_PERIOD_OFF then
s_state_a <= ST_ON;
s_rst_cnt <= '1';
end if;
when ST_ON =>
if (led_blink_i = '1' or (led_blink_i = '0' and led_on_i = '0')) and cnt_c = c_PERIOD_ON then
s_state_a <= ST_OFF;
s_rst_cnt <= '1';
end if;
end case;
end process ; -- next_state
p_reg : process( clk_i )
begin
if rising_edge(clk_i) then
if rst_i = '1' or s_rst_cnt = '1' then
cnt_c <= c_ZERO;
else
cnt_c <= cnt_c_a;
end if;
end if;
end process ; -- p_nsl
b_cnt : cnt_c_a <= cnt_c + 1 when s_state_a = ST_OFF and cnt_c /= c_PERIOD_OFF else
c_PERIOD_OFF when s_state_a = ST_OFF and cnt_c = c_PERIOD_OFF else
cnt_c + 1 when s_state_a = ST_ON and cnt_c /= c_PERIOD_ON else
c_PERIOD_ON when s_state_a = ST_ON and cnt_c = c_PERIOD_ON else
c_ZERO;
b_led_o : led_o <= '1' when s_state = ST_ON else '0';
end architecture ; -- rtl
top/sis8300ku_ref_design/sn74lv8153_interface.vhd 0 → 100644
View file @ dd7afa34
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sn74lv8153_interface is
generic (
g_clock_freq : integer := 125000000
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
d_i : in std_logic_vector(15 downto 0);
serial_o : out std_logic
);
end entity; -- sn74lv8153_interface
architecture rtl of sn74lv8153_interface is
component sn74lv8153_serializer is
generic (
g_clock_freq : integer
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
req_o : out std_logic;
d_i : in std_logic_vector(6 downto 0);
q_o : out std_logic
);
end component; -- sn74lv8153_serializer
type t_state is (LATCH_DATA, WORD0, WORD1, WORD2, WORD3);
signal state : t_state := LATCH_DATA;
signal dreg : std_logic_vector(15 downto 0) := (others => '0');
signal dout : std_logic_vector(6 downto 0) := (others => '0');
signal req : std_logic := '0';
begin
U_Serializer : sn74lv8153_serializer
generic map (
g_clock_freq => g_clock_freq
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
req_o => req,
d_i => dout,
q_o => serial_o
);
p_fsm : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
state <= LATCH_DATA;
dout <= (others => '0');
else
case state is
when LATCH_DATA =>
dreg <= d_i;
state <= WORD0;
-- first chip (address "000")
when WORD0 =>
if(req = '1') then
dout <= "000" & dreg(3 downto 0);
state <= WORD1;
end if;
when WORD1 =>
if(req = '1') then
dout <= "000" & dreg(7 downto 4);
state <= WORD2;
end if;
-- second chip (address "001")
when WORD2 =>
if(req = '1') then
dout <= "001" & dreg(11 downto 8);
state <= WORD3;
end if;
when WORD3 =>
if(req = '1') then
dout <= "001" & dreg(15 downto 12);
state <= LATCH_DATA;
end if;
end case;
end if;
end if;
end process;
end rtl;
top/sis8300ku_ref_design/sn74lv8153_serializer.vhd 0 → 100644
View file @ dd7afa34
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sn74lv8153_serializer is
generic (
g_clock_freq : integer := 125000000
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
req_o : out std_logic;
d_i : in std_logic_vector(6 downto 0);
q_o : out std_logic
);
end entity; -- sn74lv8153_serializer
architecture rtl of sn74lv8153_serializer is
constant c_bit_time : unsigned(15 downto 0) := to_unsigned(g_clock_freq / 10000, 16);
signal div_cnt : unsigned(15 downto 0) := (others => '0');
signal bit_cnt : unsigned(3 downto 0) := (others => '0');
signal div_pulse : std_logic := '0';
signal req, req_d : std_logic := '0';
signal dreg : std_logic_vector(6 downto 0) := (others => '0');
begin
p_gen_div_clock : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
div_pulse <= '0';
div_cnt <= (others => '0');
else
if div_cnt = c_bit_time then
div_pulse <= '1';
div_cnt <= (others => '0');
else
div_pulse <= '0';
div_cnt <= div_cnt + 1;
end if;
end if;
end if;
end process;
p_serializer : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
bit_cnt <= (others => '0');
req <= '0';
req_d <= '0';
dreg <= (others => '0');
q_o <= '1';
else
req_d <= req;
if (req_d = '1') then
dreg <= d_i;
end if;
if(div_pulse = '1') then
if bit_cnt = 9 then
bit_cnt <= (others => '0');
req <= '1';
else
bit_cnt <= bit_cnt + 1;
req <= '0';
end if;
else
req <= '0';
end if;
case bit_cnt is
when "0000" => q_o <= '0';
when "0001" => q_o <= '1';
-- Address Bit A0 to A2
when "0010" => q_o <= dreg(4);
when "0011" => q_o <= dreg(5);
when "0100" => q_o <= dreg(6);
-- Data Bits D0 to D3 / D4 to D7
when "0101" => q_o <= dreg(0);
when "0110" => q_o <= dreg(1);
when "0111" => q_o <= dreg(2);
when "1000" => q_o <= dreg(3);
when "1001" => q_o <= '1';
when others => null;
end case;
end if;
end if;
end process;
req_o <= req;
end architecture; -- rtl
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