Commit dd7b44e2 authored by li hongming's avatar li hongming

add cute core project file.

parent f1b7521d
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<file xil_pn:name="../../modules/wr_si57x_interface/xwr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../modules/fabric/xwrf_loopback/wrf_loopback.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../modules/wr_eca/eca_tlu_fsm.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../modules/wr_endpoint/ep_tx_path.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/vme_irq_controller.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../board/cute/wr_cute_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../modules/timing/multi_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
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