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White Rabbit core collection
Commit deee26ae authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wr_endpoint: add WB bit to generate preamble shrinkage

parent a03c66f9
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Showing with 30 additions and 14 deletions
modules/wr_endpoint/endpoint_pkg.vhd
View file @ deee26ae
......@@ -414,8 +414,7 @@ package endpoint_pkg is
stop_traffic_i : in std_logic := '0';
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep;
preamble_shrinkage : in std_logic := '0');
nice_dbg_o : out t_dbg_ep);
end component;
constant c_xwr_endpoint_sdb : t_sdb_device := (
......
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ deee26ae
......@@ -162,10 +162,10 @@ package endpoint_private_pkg is
mdio_stb_i : in std_logic;
mdio_rw_i : in std_logic;
mdio_ready_o : out std_logic;
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep_pcs;
preamble_shrinkage : in std_logic);
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep_pcs;
preamble_shrinkage : in std_logic);
end component;
component ep_tx_pcs_8bit
......
modules/wr_endpoint/ep_registers_pkg.vhd
View file @ deee26ae
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Wed Aug 16 22:43:41 2017
-- Created : Mon Nov 12 15:47:03 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -74,6 +74,7 @@ package ep_wbgen2_pkg is
ecr_rst_cnt_o : std_logic;
ecr_tx_en_o : std_logic;
ecr_rx_en_o : std_logic;
ecr_txshrin_en_o : std_logic;
tscr_en_txts_o : std_logic;
tscr_en_rxts_o : std_logic;
tscr_cs_start_o : std_logic;
......@@ -143,6 +144,7 @@ package ep_wbgen2_pkg is
ecr_rst_cnt_o => '0',
ecr_tx_en_o => '0',
ecr_rx_en_o => '0',
ecr_txshrin_en_o => '0',
tscr_en_txts_o => '0',
tscr_en_rxts_o => '0',
tscr_cs_start_o => '0',
......
modules/wr_endpoint/ep_tx_pcs_8bit.vhd
View file @ deee26ae
......@@ -164,9 +164,7 @@ architecture behavioral of ep_tx_pcs_8bit is
signal mdio_mcr_pdown_synced : std_logic;
signal an_tx_en_synced : std_logic;
signal s_one : std_logic := '1';
signal sh_preamble_sent : std_logic;
begin
U_sync_pcs_busy_o : gc_sync_ffs
......
modules/wr_endpoint/ep_wishbone_controller.vhd
View file @ deee26ae
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Wed Aug 16 22:43:41 2017
-- Created : Mon Nov 12 15:47:03 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -44,6 +44,7 @@ signal ep_ecr_rst_cnt_dly0 : std_logic ;
signal ep_ecr_rst_cnt_int : std_logic ;
signal ep_ecr_tx_en_int : std_logic ;
signal ep_ecr_rx_en_int : std_logic ;
signal ep_ecr_txshrin_en_int : std_logic ;
signal ep_tscr_en_txts_int : std_logic ;
signal ep_tscr_en_rxts_int : std_logic ;
signal ep_tscr_cs_start_int : std_logic ;
......@@ -101,6 +102,7 @@ begin
ep_ecr_rst_cnt_int <= '0';
ep_ecr_tx_en_int <= '0';
ep_ecr_rx_en_int <= '0';
ep_ecr_txshrin_en_int <= '0';
ep_tscr_en_txts_int <= '0';
ep_tscr_en_rxts_int <= '0';
ep_tscr_cs_start_int <= '0';
......@@ -206,16 +208,17 @@ begin
ep_ecr_rst_cnt_int <= wrdata_reg(5);
ep_ecr_tx_en_int <= wrdata_reg(6);
ep_ecr_rx_en_int <= wrdata_reg(7);
ep_ecr_txshrin_en_int <= wrdata_reg(8);
end if;
rddata_reg(4 downto 0) <= ep_ecr_portid_int;
rddata_reg(5) <= '0';
rddata_reg(6) <= ep_ecr_tx_en_int;
rddata_reg(7) <= ep_ecr_rx_en_int;
rddata_reg(8) <= ep_ecr_txshrin_en_int;
rddata_reg(24) <= regs_i.ecr_feat_vlan_i;
rddata_reg(25) <= regs_i.ecr_feat_dmtd_i;
rddata_reg(26) <= regs_i.ecr_feat_ptp_i;
rddata_reg(27) <= regs_i.ecr_feat_dpi_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
......@@ -706,6 +709,8 @@ begin
regs_o.ecr_tx_en_o <= ep_ecr_tx_en_int;
-- Receive path enable
regs_o.ecr_rx_en_o <= ep_ecr_rx_en_int;
-- Generate preamble shrinkage
regs_o.ecr_txshrin_en_o <= ep_ecr_txshrin_en_int;
-- Feature present: VLAN tagging
-- Feature present: DDMTD phase measurement
-- Feature present: IEEE1588 timestamper
......
modules/wr_endpoint/ep_wishbone_controller.wb
View file @ deee26ae
......@@ -86,6 +86,17 @@ peripheral {
type = BIT;
};
field {
name = "Generate preamble shrinkage";
prefix = "TXSHRIN_en";
description = "1: TX preamble shrinkage enabled\
0: TX preamble shrinkage disabled";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Feature present: VLAN tagging";
description = "1: this implementation of WR Endpoint supports VLAN processing \
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ deee26ae
......@@ -304,8 +304,7 @@ entity wr_endpoint is
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep;
preamble_shrinkage : in std_logic
nice_dbg_o : out t_dbg_ep
);
end wr_endpoint;
......@@ -548,7 +547,7 @@ begin
dbg_tx_pcs_wr_count_o => dbg_tx_pcs_wr_count_o,
dbg_tx_pcs_rd_count_o => dbg_tx_pcs_rd_count_o,
nice_dbg_o => nice_dbg_o.pcs,
preamble_shrinkage => preamble_shrinkage);
preamble_shrinkage => regs_fromwb.ecr_txshrin_en_o);
-------------------------------------------------------------------------------
......
sim/endpoint_regs.v
View file @ deee26ae
......@@ -7,6 +7,8 @@
`define EP_ECR_TX_EN 32'h00000040
`define EP_ECR_RX_EN_OFFSET 7
`define EP_ECR_RX_EN 32'h00000080
`define EP_ECR_TXSHRIN_EN_OFFSET 8
`define EP_ECR_TXSHRIN_EN 32'h00000100
`define EP_ECR_FEAT_VLAN_OFFSET 24
`define EP_ECR_FEAT_VLAN 32'h01000000
`define EP_ECR_FEAT_DMTD_OFFSET 25
......
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