Commit e4dbd438 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

remove legacy kintex7 ref design, we now have better examples

parent 2d55ee1d
-- -- file: ext_pll_10_to_62_5m.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____62.500______0.000______50.0______659.593____883.386
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________10.000____________0.005
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity ext_pll_10_to_62_5m is
port
(-- Clock in ports
clk_ext_i : in std_logic;
-- Clock out ports
clk_ext_mul_o : out std_logic;
-- Status and control signals
rst_a_i : in std_logic;
locked_o : out std_logic
);
end ext_pll_10_to_62_5m;
architecture xilinx of ext_pll_10_to_62_5m is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "ext_pll_10_to_62_5m,clk_wiz_v3_6,{component_name=ext_pll_10_to_62_5m,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=100.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
-- signal clkfbout : std_logic;
-- signal locked_internal : std_logic;
-- signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1 <= clk_ext_i;
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 62.500,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 10.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 100.000,
REF_JITTER1 => 0.005)
port map
-- Output clocks
(CLKFBOUT => clkfb,
CLKFBOUTB => open,
CLKOUT0 => clk0,
CLKOUT0B => open,
CLKOUT1 => open,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => clkfb,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_o,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => rst_a_i);
clkout1_buf : BUFG
port map
(O => clk_ext_mul_o,
I => clk0);
end xilinx;
#CLOCK & RESET
NET "clk_20m_vcxo_i" LOC = F22 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "button1_i" LOC = E11 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
#TEST & DEBUG
# Signal USB_TX is an output in the design and must be connected to pin 20/12 (RXD_I) of U34 (CP2105GM)
# Signal USB_RX is an input in the design and must be connected to pin 21/13 (TXD_O) of U34 (CP2105GM)
# Rx signals are pulled down so the USB on the CLB and the USB on the G-Board can be OR-ed
NET "uart_rxd_i" LOC = D19 | IOSTANDARD = LVCMOS25 | PULLDOWN; #Bank 15 VCCO - 2.5 V
NET "uart_txd_o" LOC = D20 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[0]" LOC = C16 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[1]" LOC = B16 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[2]" LOC = B17 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[3]" LOC = A17 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[4]" LOC = A18 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[5]" LOC = A19 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "LED_LINK" LOC = A19 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
########## To be assigned ###########
#NET "dio_led_top_o"
#NET "dio_led_bot_o"
#NET "LED_ACT"
#NET "DIP_SWITCH[1]" LOC = J15 | IOSTANDARD = LVCMOS25 | PULLDOWN; #Bank 15 VCCO - 2.5 V
#NET "DIP_SWITCH[2]" LOC = J16 | IOSTANDARD = LVCMOS25 | PULLDOWN; #Bank 15 VCCO - 2.5 V
#NET "DIP_SWITCH[3]" LOC = H16 | IOSTANDARD = LVCMOS25 | PULLDOWN; #Bank 15 VCCO - 2.5 V
#NET "DIP_SWITCH[4]" LOC = G16 | IOSTANDARD = LVCMOS25 | PULLDOWN; #Bank 15 VCCO - 2.5 V
#SOFT PLL (WHITE RABBIT)
NET "sfp_mod_def2_b" LOC = D23 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_mod_def1_b" LOC = D24 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "dio_onewire_b" LOC = L23 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
# Note LVDS_25 and VCCO 3.3V conflict for PPS_P/N!
# Therefor made a special CLBv2 Proto implementation (generic g_use_clbv2_1 true) with two single
# ended but complementary signals
NET "pps_p_o" LOC = C17 | IOSTANDARD = LVDS_25; #Bank 15 VCCO - 2.5 V
NET "pps_n_o" LOC = C18 | IOSTANDARD = LVDS_25; #Bank 15 VCCO - 2.5 V
NET "PLL_OE_OUT_B" LOC = B11 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_cs1_n_o" LOC = A14 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_cs2_n_o" LOC = A15 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_din_o" LOC = A13 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_sclk_o" LOC = A12 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#SFP
NET "sfp_mod_def0_b" LOC = E26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V (mod_def_0)
NET "sfp_los_i" LOC = F25 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_tx_fault_i" LOC = C26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_tx_disable_o" LOC = D26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_rate_select_b" LOC = G26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_mod_def2_b" LOC = H26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V (mod_def_2)
NET "sfp_mod_def1_b" LOC = J26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V (mod_def_1)
#GIGABIT TRANSCEIVER (SFP)
NET "fpga_pll_ref_clk_101_p_i" LOC = D6 | IOSTANDARD = "LVDS_25"; #Bank 116
NET "fpga_pll_ref_clk_101_n_i" LOC = D5 | IOSTANDARD = "LVDS_25"; #Bank 116
NET "fpga_pll_ref_clk_101_p_i" TNM_NET = fpga_pll_ref_clk_101_p_i;
TIMESPEC TS_fpga_pll_ref_clk_101_p_i = PERIOD "fpga_pll_ref_clk_101_p_i" 8 ns HIGH 50%;
NET "fpga_pll_ref_clk_101_n_i" TNM_NET = fpga_pll_ref_clk_101_n_i;
TIMESPEC TS_fpga_pll_ref_clk_101_n_i = PERIOD "fpga_pll_ref_clk_101_n_i" 8 ns HIGH 50%;
NET "sfp_txp_o" LOC = A4; #Bank 116
NET "sfp_txn_o" LOC = A3; #Bank 116
NET "sfp_rxp_i" LOC = B6; #Bank 116
NET "sfp_rxn_i" LOC = B5; #Bank 116
########################################################
## Pin definitions for FmcDio5chttl + CLB V2.2.1 ##
########################################################
# DIO outputs
NET "dio_p_o[4]" LOC = N18 | IOSTANDARD=LVDS_25;
NET "dio_n_o[4]" LOC = M19 | IOSTANDARD=LVDS_25;
NET "dio_p_o[3]" LOC = U19 | IOSTANDARD=LVDS_25;
NET "dio_n_o[3]" LOC = U20 | IOSTANDARD=LVDS_25;
NET "dio_p_o[2]" LOC = W20 | IOSTANDARD=LVDS_25;
NET "dio_n_o[2]" LOC = Y21 | IOSTANDARD=LVDS_25;
NET "dio_p_o[1]" LOC = M21 | IOSTANDARD=LVDS_25;
NET "dio_n_o[1]" LOC = M22 | IOSTANDARD=LVDS_25;
NET "dio_p_o[0]" LOC = N19 | IOSTANDARD=LVDS_25;
NET "dio_n_o[0]" LOC = M20 | IOSTANDARD=LVDS_25;
NET "dio_sdn_n_o" LOC = AA25 | IOSTANDARD=LVCMOS25;
NET "dio_sdn_ck_n_o" LOC = AF24 | IOSTANDARD=LVCMOS25;
# DIO output enable/termination enable
NET "dio_oe_n_o[4]" LOC = AE22 | IOSTANDARD=LVCMOS25;
NET "dio_oe_n_o[3]" LOC = U26 | IOSTANDARD=LVCMOS25;
NET "dio_oe_n_o[2]" LOC = AB25 | IOSTANDARD=LVCMOS25;
NET "dio_oe_n_o[1]" LOC = N23 | IOSTANDARD=LVCMOS25;
NET "dio_oe_n_o[0]" LOC = P24 | IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[4]" LOC = P25 | IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[3]" LOC = R25 | IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[2]" LOC = AF22 | IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[1]" LOC = AF25 | IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[0]" LOC = N24 | IOSTANDARD=LVCMOS25;
NET "dio_onewire_b" LOC = K26 | IOSTANDARD=LVCMOS25;
# DIO inputs
NET "dio_clk_p_i" LOC = Y22 | IOSTANDARD=LVDS_25;
NET "dio_clk_n_i" LOC = AA22 | IOSTANDARD=LVDS_25;
NET "dio_p_i[4]" LOC = N21 | IOSTANDARD=LVDS_25;
NET "dio_n_i[4]" LOC = N22 | IOSTANDARD=LVDS_25;
NET "dio_p_i[3]" LOC = P16 | IOSTANDARD=LVDS_25;
NET "dio_n_i[3]" LOC = N17 | IOSTANDARD=LVDS_25;
NET "dio_p_i[2]" LOC = AB26 | IOSTANDARD=LVDS_25;
NET "dio_n_i[2]" LOC = AC26 | IOSTANDARD=LVDS_25;
NET "dio_p_i[1]" LOC = K20 | IOSTANDARD=LVDS_25;
NET "dio_n_i[1]" LOC = J20 | IOSTANDARD=LVDS_25;
NET "dio_p_i[0]" LOC = P19 | IOSTANDARD=LVDS_25;
NET "dio_n_i[0]" LOC = P20 | IOSTANDARD=LVDS_25;
NET "dio_led_top_o" LOC = R21 | IOSTANDARD=LVCMOS25;
NET "dio_led_bot_o" LOC = P21 | IOSTANDARD=LVCMOS25;
########################################################
####################################
# Note that the phy_rst_o originates from the clk_sys domain. Synchronization is not needed
# when the clk_sys is phase locked with clk_gtx_i (which is usually the case) but is a safety
# measure. Add a false path for U_EdgeDet_rst_i_reg_sync0 to remove non-existing timing errors.
# Comment iether one or the other line since for Precision or XST usage
NET "clk_sys" TNM_NET = FFS "FFS_pllout_clk_sys";
#INST "u0_U_GTP/U_EdgeDet_rst_i_reg_sync0" TNM = FFS_U_EdgeDet_rst_i_reg_sync0; # Precision
#INST "u0/U_GTP/U_EdgeDet_rst_i/sync0" TNM = FFS_U_EdgeDet_rst_i_reg_sync0; # XST
TIMESPEC TS_IgnoreAsyncGTP_Rst = FROM "FFS_pllout_clk_sys" TO "FFS_U_EdgeDet_rst_i_reg_sync0" TIG;
#INST "u11/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/jtag_cores/jtag_tap/bscan" JTAG_CHAIN = 1; # XST; Better add these as generic assignments in the do_input_file_list.cmd
#INST "u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/jtag_cores/jtag_tap/bscan" JTAG_CHAIN = 2; # XST; Better add these as generic assignments in the do_input_file_list.cmd
This diff is collapsed.
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
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