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White Rabbit core collection
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e50ffe01
Commit
e50ffe01
authored
Feb 28, 2019
by
Grzegorz Daniluk
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fabric: add doc html with register description
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e50ffe01
<HTML>
<HEAD>
<TITLE>
lbk_wishbone_controller
</TITLE>
<STYLE
TYPE=
"text/css"
MEDIA=
"all"
>
<!--
BODY { background: white; color: black;
font-family: Arial,Helvetica; font-size:12; }
h1 { font-family: Trebuchet MS,Arial,Helvetica; font-size:30; color:#404040; }
h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22; color:#404040; }
h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16; color:#404040; }
.td_arrow_left { padding:0px; background: #ffffff; text-align: right; font-size:12;}
.td_arrow_right { padding:0px; background: #ffffff; text-align: left; font-size:12;}
.td_code { font-family:Courier New,Courier; padding: 3px; }
.td_desc { padding: 3px; }
.td_sym_center { background: #e0e0f0; padding: 3px; }
.td_port_name { font-family:Courier New,Courier; background: #e0e0f0; text-align: right; font-weight:bold;padding: 3px; width:200px; }
.td_pblock_left { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: left; }
.td_pblock_right { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: right; }
.td_bit { background: #ffffff; color:#404040; font-size:10; width: 70px; font-family:Courier New,Courier; padding: 3px; text-align:center; }
.td_field { background: #e0e0f0; padding: 3px; text-align:center; }
.td_unused { background: #a0a0a0; padding: 3px; text-align:center; }
th { font-weight:bold; color:#ffffff; background: #202080; padding:3px; }
.tr_even { background: #f0eff0; }
.tr_odd { background: #e0e0f0; }
-->
</STYLE>
</HEAD>
<BODY>
<h1
class=
"heading"
>
lbk_wishbone_controller
</h1>
<h3>
WRF Loopback
</h3>
<p></p>
<h3>
Contents:
</h3>
<span
style=
"margin-left: 0px; "
>
1.
<A
href=
"#sect_1_0"
>
Memory map summary
</a></span><br/>
<span
style=
"margin-left: 0px; "
>
2.
<A
href=
"#sect_2_0"
>
HDL symbol
</a></span><br/>
<span
style=
"margin-left: 0px; "
>
3.
<A
href=
"#sect_3_0"
>
Register description
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.1.
<A
href=
"#sect_3_1"
>
Main Control Register
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.2.
<A
href=
"#sect_3_2"
>
Forced Destination MAC [3:0]
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.3.
<A
href=
"#sect_3_3"
>
Forced Destination MAC [5:4]
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.4.
<A
href=
"#sect_3_4"
>
Received frames counter
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.5.
<A
href=
"#sect_3_5"
>
Dropped frames counter
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.6.
<A
href=
"#sect_3_6"
>
Forwarded frames counter
</a></span><br/>
<h3><a
name=
"sect_1_0"
>
1. Memory map summary
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<th
>
H/W Address
</th>
<th
>
Type
</th>
<th
>
Name
</th>
<th
>
VHDL/Verilog prefix
</th>
<th
>
C prefix
</th>
</tr>
<tr
class=
"tr_odd"
>
<td
class=
"td_code"
>
0x0
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#MCR"
>
Main Control Register
</a>
</td>
<td
class=
"td_code"
>
lbk_mcr
</td>
<td
class=
"td_code"
>
MCR
</td>
</tr>
<tr
class=
"tr_even"
>
<td
class=
"td_code"
>
0x1
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#DMAC_L"
>
Forced Destination MAC [3:0]
</a>
</td>
<td
class=
"td_code"
>
lbk_dmac_l
</td>
<td
class=
"td_code"
>
DMAC_L
</td>
</tr>
<tr
class=
"tr_odd"
>
<td
class=
"td_code"
>
0x2
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#DMAC_H"
>
Forced Destination MAC [5:4]
</a>
</td>
<td
class=
"td_code"
>
lbk_dmac_h
</td>
<td
class=
"td_code"
>
DMAC_H
</td>
</tr>
<tr
class=
"tr_even"
>
<td
class=
"td_code"
>
0x3
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#RCV_CNT"
>
Received frames counter
</a>
</td>
<td
class=
"td_code"
>
lbk_rcv_cnt
</td>
<td
class=
"td_code"
>
RCV_CNT
</td>
</tr>
<tr
class=
"tr_odd"
>
<td
class=
"td_code"
>
0x4
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#DRP_CNT"
>
Dropped frames counter
</a>
</td>
<td
class=
"td_code"
>
lbk_drp_cnt
</td>
<td
class=
"td_code"
>
DRP_CNT
</td>
</tr>
<tr
class=
"tr_even"
>
<td
class=
"td_code"
>
0x5
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#FWD_CNT"
>
Forwarded frames counter
</a>
</td>
<td
class=
"td_code"
>
lbk_fwd_cnt
</td>
<td
class=
"td_code"
>
FWD_CNT
</td>
</tr>
</table>
<h3><a
name=
"sect_2_0"
>
2. HDL symbol
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_arrow_left"
>
→
</td>
<td
class=
"td_pblock_left"
>
rst_n_i
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Main Control Register:
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
→
</td>
<td
class=
"td_pblock_left"
>
clk_sys_i
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_mcr_ena_o
</td>
<td
class=
"td_arrow_right"
>
→
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
⇒
</td>
<td
class=
"td_pblock_left"
>
wb_adr_i[2:0]
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_mcr_clr_o
</td>
<td
class=
"td_arrow_right"
>
→
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
⇒
</td>
<td
class=
"td_pblock_left"
>
wb_dat_i[31:0]
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_mcr_fdmac_o
</td>
<td
class=
"td_arrow_right"
>
→
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
⇐
</td>
<td
class=
"td_pblock_left"
>
wb_dat_o[31:0]
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
→
</td>
<td
class=
"td_pblock_left"
>
wb_cyc_i
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Forced Destination MAC [3:0]:
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
⇒
</td>
<td
class=
"td_pblock_left"
>
wb_sel_i[3:0]
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_dmac_l_o[31:0]
</td>
<td
class=
"td_arrow_right"
>
⇒
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
→
</td>
<td
class=
"td_pblock_left"
>
wb_stb_i
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_dmac_l_i[31:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
→
</td>
<td
class=
"td_pblock_left"
>
wb_we_i
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_dmac_l_load_o
</td>
<td
class=
"td_arrow_right"
>
→
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
←
</td>
<td
class=
"td_pblock_left"
>
wb_ack_o
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
←
</td>
<td
class=
"td_pblock_left"
>
wb_stall_o
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Forced Destination MAC [5:4]:
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_dmac_h_o[15:0]
</td>
<td
class=
"td_arrow_right"
>
⇒
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_dmac_h_i[15:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_dmac_h_load_o
</td>
<td
class=
"td_arrow_right"
>
→
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Received frames counter:
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_rcv_cnt_o[31:0]
</td>
<td
class=
"td_arrow_right"
>
⇒
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_rcv_cnt_i[31:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_rcv_cnt_load_o
</td>
<td
class=
"td_arrow_right"
>
→
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Dropped frames counter:
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_drp_cnt_o[31:0]
</td>
<td
class=
"td_arrow_right"
>
⇒
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_drp_cnt_i[31:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_drp_cnt_load_o
</td>
<td
class=
"td_arrow_right"
>
→
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Forwarded frames counter:
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_fwd_cnt_o[31:0]
</td>
<td
class=
"td_arrow_right"
>
⇒
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_fwd_cnt_i[31:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
lbk_fwd_cnt_load_o
</td>
<td
class=
"td_arrow_right"
>
→
</td>
</tr>
</table>
<h3><a
name=
"sect_3_0"
>
3. Register description
</a></h3>
<a
name=
"MCR"
></a>
<h3><a
name=
"sect_3_1"
>
3.1. Main Control Register
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
lbk_mcr
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x0
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
MCR
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x0
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
style=
"border: solid 1px black;"
colspan=
1
class=
"td_field"
>
FDMAC
</td>
<td
style=
"border: solid 1px black;"
colspan=
1
class=
"td_field"
>
CLR
</td>
<td
style=
"border: solid 1px black;"
colspan=
1
class=
"td_field"
>
ENA
</td>
</tr>
</table>
<ul>
<li><b>
ENA
</b>
[
<i>
read/write
</i>
]: Enable Loopback
<li><b>
CLR
</b>
[
<i>
write-only
</i>
]: Clear counters
<li><b>
FDMAC
</b>
[
<i>
read/write
</i>
]: Force DMAC
</ul>
<a
name=
"DMAC_L"
></a>
<h3><a
name=
"sect_3_2"
>
3.2. Forced Destination MAC [3:0]
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
lbk_dmac_l
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x1
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
DMAC_L
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x4
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
DMAC_L[31:24]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
DMAC_L[23:16]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
DMAC_L[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
DMAC_L[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
DMAC_L
</b>
[
<i>
read/write
</i>
]: MAC
</ul>
<a
name=
"DMAC_H"
></a>
<h3><a
name=
"sect_3_3"
>
3.3. Forced Destination MAC [5:4]
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
lbk_dmac_h
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x2
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
DMAC_H
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x8
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
DMAC_H[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
DMAC_H[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
DMAC_H
</b>
[
<i>
read/write
</i>
]: MAC
</ul>
<a
name=
"RCV_CNT"
></a>
<h3><a
name=
"sect_3_4"
>
3.4. Received frames counter
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
lbk_rcv_cnt
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x3
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
RCV_CNT
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0xc
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
RCV_CNT[31:24]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
RCV_CNT[23:16]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
RCV_CNT[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
RCV_CNT[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
RCV_CNT
</b>
[
<i>
read/write
</i>
]: Value
</ul>
<a
name=
"DRP_CNT"
></a>
<h3><a
name=
"sect_3_5"
>
3.5. Dropped frames counter
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
lbk_drp_cnt
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x4
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
DRP_CNT
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x10
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
DRP_CNT[31:24]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
DRP_CNT[23:16]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
DRP_CNT[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
DRP_CNT[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
DRP_CNT
</b>
[
<i>
read/write
</i>
]: Value
</ul>
<a
name=
"FWD_CNT"
></a>
<h3><a
name=
"sect_3_6"
>
3.6. Forwarded frames counter
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
lbk_fwd_cnt
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x5
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
FWD_CNT
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x14
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
FWD_CNT[31:24]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
FWD_CNT[23:16]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
FWD_CNT[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
FWD_CNT[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
FWD_CNT
</b>
[
<i>
read/write
</i>
]: Value
</ul>
</BODY>
</HTML>
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