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White Rabbit core collection
Commit ede5e434 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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Merge branch 'preamble_shrinkage' into proposed_master

parents b6dfc740 613b5640
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Showing with 286 additions and 91 deletions
board/common/wr_board_pkg.vhd
View file @ ede5e434
......@@ -42,7 +42,7 @@ use work.streamers_pkg.all;
package wr_board_pkg is
type t_board_fabric_iface is (PLAIN, STREAMERS, ETHERBONE, always_last_invalid);
type t_board_fabric_iface is (PLAIN, STREAMERS, ETHERBONE, LOOPBACK, always_last_invalid);
-- TODO: using these default paths requires absolute path. If relative path is used,
-- they work only for reference designs by chance. Once we figure out how to
......
board/common/xwrc_board_common.vhd
View file @ ede5e434
......@@ -566,6 +566,23 @@ begin -- architecture struct
end generate gen_etherbone;
gen_loopback : if (g_fabric_iface = LOOPBACK) generate
cmp_wrf_loopback : xwrf_loopback
generic map(
g_interface_mode => PIPELINED,
g_address_granularity => WORD)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
wrf_snk_i => wrf_src_out,
wrf_snk_o => wrf_src_in,
wrf_src_o => wrf_snk_in,
wrf_src_i => wrf_snk_out,
wb_i => aux_master_out,
wb_o => aux_master_in);
end generate gen_loopback;
gen_wr_fabric : if (g_fabric_iface = PLAIN) generate
wrf_src_o <= wrf_src_out;
......
modules/wr_endpoint/endpoint_pkg.vhd
View file @ ede5e434
......@@ -148,6 +148,14 @@ package endpoint_pkg is
rx : t_dbg_ep_rxpcs;
end record;
type t_dbg_rtu_extract is record
in_packet : std_logic;
in_header : std_logic;
rtu_rq_valid_basic : std_logic;
rtu_rq_valid_tagged : std_logic;
rtu_rq_abort : std_logic;
end record;
type t_dbg_ep_rxpath is record
fab_pipe : t_fab_pipe(9 downto 0);
dreq_pipe : std_logic_vector(9 downto 0);
......@@ -155,6 +163,7 @@ package endpoint_pkg is
pcs_fifo_empty : std_logic;
pcs_fifo_full : std_logic;
rxbuf_full : std_logic;
rtu_extract : t_dbg_rtu_extract;
end record;
type t_dbg_ep is record
......@@ -186,7 +195,8 @@ package endpoint_pkg is
g_with_packet_injection : boolean := false;
g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false);
g_with_stop_traffic : boolean := false;
g_ep_idx : integer := 0);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
......@@ -297,7 +307,8 @@ package endpoint_pkg is
g_with_packet_injection : boolean := false;
g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false);
g_with_stop_traffic : boolean := false;
g_ep_idx : integer := 0);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
......@@ -403,7 +414,7 @@ package endpoint_pkg is
stop_traffic_i : in std_logic := '0';
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep);
nice_dbg_o : out t_dbg_ep);
end component;
constant c_xwr_endpoint_sdb : t_sdb_device := (
......
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ ede5e434
......@@ -116,7 +116,8 @@ package endpoint_private_pkg is
component ep_1000basex_pcs
generic (
g_simulation : boolean;
g_16bit : boolean);
g_16bit : boolean;
g_ep_idx : integer);
port (
rst_sys_n_i : in std_logic;
rst_txclk_n_i : in std_logic;
......@@ -161,9 +162,10 @@ package endpoint_private_pkg is
mdio_stb_i : in std_logic;
mdio_rw_i : in std_logic;
mdio_ready_o : out std_logic;
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep_pcs);
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep_pcs;
preamble_shrinkage : in std_logic);
end component;
component ep_tx_pcs_8bit
......@@ -186,7 +188,8 @@ package endpoint_private_pkg is
phy_tx_data_o : out std_logic_vector(7 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic);
phy_tx_enc_err_i : in std_logic;
preamble_shrinkage : in std_logic := '0');
end component;
component ep_tx_pcs_16bit
......@@ -250,7 +253,8 @@ package endpoint_private_pkg is
component ep_rx_pcs_16bit
generic (
g_simulation : boolean);
g_simulation : boolean;
g_ep_idx : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -517,7 +521,8 @@ package endpoint_private_pkg is
rtu_full_i : in std_logic;
rtu_rq_abort_o : out std_logic;
rtu_rq_valid_o : out std_logic;
rxbuf_full_i : in std_logic);
rxbuf_full_i : in std_logic;
nice_dbg_o : out t_dbg_rtu_extract);
end component;
component ep_rx_early_address_match
......@@ -620,6 +625,7 @@ package endpoint_private_pkg is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
stop_traffic_i : in std_logic := '0';
snk_fab_i : in t_ep_internal_fabric;
snk_dreq_o : out std_logic;
src_wb_i : in t_wrf_source_in;
......@@ -675,6 +681,7 @@ package endpoint_private_pkg is
clk_rx_i : in std_logic;
rst_n_sys_i : in std_logic;
rst_n_rx_i : in std_logic;
stop_traffic_i : in std_logic;
pcs_fab_i : in t_ep_internal_fabric;
pcs_fifo_almostfull_o : out std_logic;
pcs_busy_i : in std_logic;
......
modules/wr_endpoint/ep_1000basex_pcs.vhd
View file @ ede5e434
......@@ -63,7 +63,8 @@ entity ep_1000basex_pcs is
g_simulation : boolean;
-- PCS datapath width selection: true = 16-bit (Virtex-6), false = 8-bit
-- (Spartan-6 or TBI).
g_16bit : boolean);
g_16bit : boolean;
g_ep_idx : integer);
port (
......@@ -195,7 +196,8 @@ entity ep_1000basex_pcs is
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep_pcs);
nice_dbg_o : out t_dbg_ep_pcs;
preamble_shrinkage : in std_logic);
end ep_1000basex_pcs;
......@@ -295,7 +297,8 @@ begin -- rtl
U_RX_PCS : ep_rx_pcs_16bit
generic map (
g_simulation => g_simulation)
g_simulation => g_simulation,
g_ep_idx => g_ep_idx)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => pcs_reset_n,
......@@ -366,7 +369,8 @@ begin -- rtl
phy_tx_data_o => serdes_tx_data_o(7 downto 0),
phy_tx_k_o => serdes_tx_k_o(0),
phy_tx_disparity_i => serdes_tx_disparity_i,
phy_tx_enc_err_i => serdes_tx_enc_err_i
phy_tx_enc_err_i => serdes_tx_enc_err_i,
preamble_shrinkage => preamble_shrinkage
);
U_RX_PCS : ep_rx_pcs_8bit
......
modules/wr_endpoint/ep_registers_pkg.vhd
View file @ ede5e434
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Wed Aug 16 22:43:41 2017
-- Created : Mon Nov 12 15:47:03 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -74,6 +74,7 @@ package ep_wbgen2_pkg is
ecr_rst_cnt_o : std_logic;
ecr_tx_en_o : std_logic;
ecr_rx_en_o : std_logic;
ecr_txshrin_en_o : std_logic;
tscr_en_txts_o : std_logic;
tscr_en_rxts_o : std_logic;
tscr_cs_start_o : std_logic;
......@@ -143,6 +144,7 @@ package ep_wbgen2_pkg is
ecr_rst_cnt_o => '0',
ecr_tx_en_o => '0',
ecr_rx_en_o => '0',
ecr_txshrin_en_o => '0',
tscr_en_txts_o => '0',
tscr_en_rxts_o => '0',
tscr_cs_start_o => '0',
......
modules/wr_endpoint/ep_rtu_header_extract.vhd
View file @ ede5e434
......@@ -61,7 +61,8 @@ entity ep_rtu_header_extract is
rtu_full_i : in std_logic;
rtu_rq_abort_o : out std_logic;
rtu_rq_valid_o : out std_logic;
rxbuf_full_i : in std_logic
rxbuf_full_i : in std_logic;
nice_dbg_o : out t_dbg_rtu_extract
);
end ep_rtu_header_extract;
......@@ -201,5 +202,11 @@ begin -- rtl
rtu_rq_o.has_prio <= vlan_is_tagged_i;
rtu_rq_valid_o <= rtu_rq_valid_out and not snk_fab_i.ERROR;
rtu_rq_o.hash <= (others => '0');
nice_dbg_o.in_packet <= in_packet;
nice_dbg_o.in_header <= in_header;
nice_dbg_o.rtu_rq_valid_basic <= rtu_rq_valid_basic;
nice_dbg_o.rtu_rq_valid_tagged <= rtu_rq_valid_tagged;
nice_dbg_o.rtu_rq_abort <= rtu_rq_abort;
end rtl;
modules/wr_endpoint/ep_rx_path.vhd
View file @ ede5e434
......@@ -75,6 +75,8 @@ entity ep_rx_path is
rst_n_sys_i : in std_logic;
rst_n_rx_i : in std_logic;
stop_traffic_i : in std_logic;
-- physical coding sublayer (PCS) interface
pcs_fab_i : in t_ep_internal_fabric;
pcs_fifo_almostfull_o : out std_logic;
......@@ -394,7 +396,8 @@ begin -- behavioral
rtu_full_i => rtu_full_i,
rtu_rq_abort_o => rtu_rq_abort_o,
rtu_rq_valid_o => rtu_rq_valid,
rxbuf_full_i => rxbuf_full);
rxbuf_full_i => rxbuf_full,
nice_dbg_o => nice_dbg_o.rtu_extract);
gen_with_rx_buffer : if g_with_rx_buffer generate
U_Rx_Buffer : ep_rx_buffer
......@@ -445,6 +448,7 @@ begin -- behavioral
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
stop_traffic_i => stop_traffic_i,
snk_fab_i => fab_pipe(9),
snk_dreq_o => dreq_pipe(9),
src_wb_i => src_wb_i,
......
modules/wr_endpoint/ep_rx_pcs_16bit.vhd
View file @ ede5e434
This diff is collapsed.
modules/wr_endpoint/ep_rx_wb_master.vhd
View file @ ede5e434
......@@ -56,6 +56,7 @@ entity ep_rx_wb_master is
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
stop_traffic_i : in std_logic := '0';
-- physical coding sublayer (PCS) interface
snk_fab_i : in t_ep_internal_fabric;
snk_dreq_o : out std_logic;
......@@ -157,7 +158,7 @@ begin -- behavioral
state <= FLUSH_STALL;
end if;
if(snk_fab_i.eof = '1')then
if(snk_fab_i.eof = '1' or stop_traffic_i = '1')then
state <= FINISH_CYCLE;
end if;
......
modules/wr_endpoint/ep_tx_pcs_8bit.vhd
View file @ ede5e434
......@@ -119,7 +119,9 @@ entity ep_tx_pcs_8bit is
phy_tx_data_o : out std_logic_vector(7 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic
phy_tx_enc_err_i : in std_logic;
preamble_shrinkage : in std_logic := '0'
);
end ep_tx_pcs_8bit;
......@@ -162,6 +164,7 @@ architecture behavioral of ep_tx_pcs_8bit is
signal mdio_mcr_pdown_synced : std_logic;
signal an_tx_en_synced : std_logic;
signal sh_preamble_sent : std_logic;
begin
U_sync_pcs_busy_o : gc_sync_ffs
......@@ -280,7 +283,7 @@ begin
tx_odd_length <= '0';
tx_rdreq_toggle <= '0';
rmon_tx_underrun <= '0';
sh_preamble_sent <= '0';
else
case tx_state is
......@@ -294,6 +297,7 @@ begin
tx_state <= TX_IDLE;
fifo_rd <= '0';
fifo_ready <= fifo_rd;
sh_preamble_sent <= '0';
-------------------------------------------------------------------------------
-- State IDLE: sends the second code of the /I/ sequence with proper disparity\
......@@ -304,6 +308,7 @@ begin
-- make sure is't long enough to trigger the event counter
rmon_tx_underrun <= '0';
tx_error <= '0';
sh_preamble_sent <= '0';
-- endpoint wants to send Config_Reg
if(an_tx_en_synced = '1') then
......@@ -315,7 +320,12 @@ begin
elsif (fifo_fab.sof = '1' and fifo_ready = '1' and tx_cntr = "0000")then
fifo_rd <= '1';
tx_state <= TX_SPD;
tx_cntr <= "0101";
if (preamble_shrinkage = '0') then -- generate preamble shrinkage
tx_cntr <= "0101";
else
sh_preamble_sent <= '1';
tx_cntr <= "0100";
end if;
-- host requested a calibration pattern
elsif(mdio_wr_spec_tx_cal_i = '1') then
......@@ -453,8 +463,13 @@ begin
tx_rdreq_toggle <= not tx_rdreq_toggle;
-- handle the end of frame both for even- and odd-length frames
tx_odd_length <= fifo_fab.bytesel;
-- handle the end of frame both for even- and odd-length frames,
-- including preamble shrinkage
if (sh_preamble_sent = '0') then
tx_odd_length <= fifo_fab.bytesel;
else
tx_odd_length <= not fifo_fab.bytesel;
end if;
if (fifo_fab.eof = '1' and (tx_rdreq_toggle = '0' or (tx_rdreq_toggle = '1' and fifo_fab.bytesel = '1'))) then
tx_state <= TX_EPD;
......
modules/wr_endpoint/ep_wishbone_controller.vhd
View file @ ede5e434
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Wed Aug 16 22:43:41 2017
-- Created : Mon Nov 12 15:47:03 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -44,6 +44,7 @@ signal ep_ecr_rst_cnt_dly0 : std_logic ;
signal ep_ecr_rst_cnt_int : std_logic ;
signal ep_ecr_tx_en_int : std_logic ;
signal ep_ecr_rx_en_int : std_logic ;
signal ep_ecr_txshrin_en_int : std_logic ;
signal ep_tscr_en_txts_int : std_logic ;
signal ep_tscr_en_rxts_int : std_logic ;
signal ep_tscr_cs_start_int : std_logic ;
......@@ -101,6 +102,7 @@ begin
ep_ecr_rst_cnt_int <= '0';
ep_ecr_tx_en_int <= '0';
ep_ecr_rx_en_int <= '0';
ep_ecr_txshrin_en_int <= '0';
ep_tscr_en_txts_int <= '0';
ep_tscr_en_rxts_int <= '0';
ep_tscr_cs_start_int <= '0';
......@@ -206,16 +208,17 @@ begin
ep_ecr_rst_cnt_int <= wrdata_reg(5);
ep_ecr_tx_en_int <= wrdata_reg(6);
ep_ecr_rx_en_int <= wrdata_reg(7);
ep_ecr_txshrin_en_int <= wrdata_reg(8);
end if;
rddata_reg(4 downto 0) <= ep_ecr_portid_int;
rddata_reg(5) <= '0';
rddata_reg(6) <= ep_ecr_tx_en_int;
rddata_reg(7) <= ep_ecr_rx_en_int;
rddata_reg(8) <= ep_ecr_txshrin_en_int;
rddata_reg(24) <= regs_i.ecr_feat_vlan_i;
rddata_reg(25) <= regs_i.ecr_feat_dmtd_i;
rddata_reg(26) <= regs_i.ecr_feat_ptp_i;
rddata_reg(27) <= regs_i.ecr_feat_dpi_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
......@@ -706,6 +709,8 @@ begin
regs_o.ecr_tx_en_o <= ep_ecr_tx_en_int;
-- Receive path enable
regs_o.ecr_rx_en_o <= ep_ecr_rx_en_int;
-- Generate preamble shrinkage
regs_o.ecr_txshrin_en_o <= ep_ecr_txshrin_en_int;
-- Feature present: VLAN tagging
-- Feature present: DDMTD phase measurement
-- Feature present: IEEE1588 timestamper
......
modules/wr_endpoint/ep_wishbone_controller.wb
View file @ ede5e434
......@@ -86,6 +86,17 @@ peripheral {
type = BIT;
};
field {
name = "Generate preamble shrinkage";
prefix = "TXSHRIN_en";
description = "1: TX preamble shrinkage enabled\
0: TX preamble shrinkage disabled";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Feature present: VLAN tagging";
description = "1: this implementation of WR Endpoint supports VLAN processing \
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ ede5e434
......@@ -74,7 +74,8 @@ entity wr_endpoint is
g_with_packet_injection : boolean := false;
g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false
g_with_stop_traffic : boolean := false;
g_ep_idx : integer := 0
);
port (
......@@ -303,7 +304,7 @@ entity wr_endpoint is
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep
nice_dbg_o : out t_dbg_ep
);
end wr_endpoint;
......@@ -488,7 +489,8 @@ begin
U_PCS_1000BASEX : ep_1000basex_pcs
generic map (
g_simulation => g_simulation,
g_16bit => g_pcs_16bit)
g_16bit => g_pcs_16bit,
g_ep_idx => g_ep_idx)
port map (
rst_sys_n_i => rst_sys_n_i,
rst_rxclk_n_i => rst_rxclk_n_i,
......@@ -544,7 +546,8 @@ begin
mdio_ready_o => regs_towb_ep.mdio_asr_ready_i,
dbg_tx_pcs_wr_count_o => dbg_tx_pcs_wr_count_o,
dbg_tx_pcs_rd_count_o => dbg_tx_pcs_rd_count_o,
nice_dbg_o => nice_dbg_o.pcs);
nice_dbg_o => nice_dbg_o.pcs,
preamble_shrinkage => regs_fromwb.ecr_txshrin_en_o);
-------------------------------------------------------------------------------
......@@ -629,6 +632,8 @@ begin
rst_n_sys_i => rst_n_rx_resync_sys,
rst_n_rx_i => rst_n_rx,
stop_traffic_i => stop_traffic_i,
pcs_fab_i => rxpath_fab,
pcs_fifo_almostfull_o => rxpcs_fifo_almostfull,
pcs_busy_i => rxpcs_busy,
......
modules/wr_endpoint/xwr_endpoint.vhd
View file @ ede5e434
......@@ -65,7 +65,8 @@ entity xwr_endpoint is
g_with_packet_injection : boolean := false;
g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false
g_with_stop_traffic : boolean := false;
g_ep_idx : integer
);
port (
......@@ -319,7 +320,8 @@ begin
g_with_packet_injection => g_with_packet_injection,
g_use_new_rxcrc => g_use_new_rxcrc,
g_use_new_txcrc => g_use_new_txcrc,
g_with_stop_traffic => g_with_stop_traffic)
g_with_stop_traffic => g_with_stop_traffic,
g_ep_idx => g_ep_idx)
port map (
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
......
sim/endpoint_regs.v
View file @ ede5e434
......@@ -7,6 +7,8 @@
`define EP_ECR_TX_EN 32'h00000040
`define EP_ECR_RX_EN_OFFSET 7
`define EP_ECR_RX_EN 32'h00000080
`define EP_ECR_TXSHRIN_EN_OFFSET 8
`define EP_ECR_TXSHRIN_EN 32'h00000100
`define EP_ECR_FEAT_VLAN_OFFSET 24
`define EP_ECR_FEAT_VLAN 32'h01000000
`define EP_ECR_FEAT_DMTD_OFFSET 25
......
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