Commit ee41b569 authored by Maciej Lipinski's avatar Maciej Lipinski

board_common: provide g_clk_ref_rate to wr streamers based on g_pcs_16bit

Provide the rate of the WR Reference Clock based on the information
about the width of the PCS word. It is assumed to be related:
* 16bit word with 62.5MHz clock
*  8bit word with  125MHz clock
parent 9a9fb3b6
......@@ -75,6 +75,10 @@ package wr_board_pkg is
application_size : integer
) return integer;
function f_pick_clk_ref_rate (
pcs_16bit_in : boolean
) return integer;
function f_vectorize_diag (
diag_in : t_generic_word_array;
diag_vector_size : integer)
......@@ -288,6 +292,18 @@ package body wr_board_pkg is
end if;
end f_pick_diag_size;
-- guess clk_ref (WR reference Clock) rate based on PCS word width
function f_pick_clk_ref_rate (
pcs_16bit_in : boolean
) return integer is
begin
if(pcs_16bit_in = TRUE) then
return 62500000;
else
return 125000000;
end if;
end f_pick_clk_ref_rate;
function f_vectorize_diag (
diag_in : t_generic_word_array;
diag_vector_size : integer)
......
......@@ -491,7 +491,8 @@ begin -- architecture struct
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
g_simulation => g_simulation)
g_simulation => g_simulation,
g_clk_ref_rate => f_pick_clk_ref_rate(g_pcs_16bit))
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......
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