Commit f1530b6b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

wr_pps_gen: naming convention fixes, pps_valid rerouted to disable/enable the PPS output

parent 49c340a6
files = ["pps_gen_wb.vhd",
"wrsw_pps_gen.vhd",
"xwb_pps_gen.vhd"];
"wr_pps_gen.vhd",
"xwr_pps_gen.vhd"];
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/pps_gen.html -V pps_gen_wb.vhd -C pps_gen_regs.h --cstyle defines --lang vhdl -K ../../sim/pps_gen_regs.v pps_gen_wb.wb
......@@ -2,11 +2,11 @@
-- Title : Wishbone slave core for WR Switch PPS generator and RTC
---------------------------------------------------------------------------------------
-- File : pps_gen_wb.vhd
-- Author : auto-generated by wbgen2 from wrsw_pps_gen.wb
-- Created : Thu Oct 27 21:29:19 2011
-- Author : auto-generated by wbgen2 from pps_gen_wb.wb
-- Created : Thu Oct 27 23:53:31 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_pps_gen.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......
......@@ -29,7 +29,7 @@ library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity wrsw_pps_gen is
entity wr_pps_gen is
generic(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
......@@ -40,9 +40,9 @@ entity wrsw_pps_gen is
rst_n_i : in std_logic;
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
......@@ -56,14 +56,13 @@ entity wrsw_pps_gen is
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
pps_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic
);
end wrsw_pps_gen;
end wr_pps_gen;
architecture behavioral of wrsw_pps_gen is
architecture behavioral of wr_pps_gen is
constant c_PERIOD : integer := 125000000;
......@@ -160,7 +159,7 @@ architecture behavioral of wrsw_pps_gen is
begin -- behavioral
resized_addr(4 downto 0) <= wb_addr_i;
resized_addr(4 downto 0) <= wb_adr_i;
resized_addr(c_wishbone_address_width-1 downto 5) <= (others => '0');
U_Adapter : wb_slave_adapter
......@@ -177,12 +176,12 @@ begin -- behavioral
master_i => wb_out,
master_o => wb_in,
sl_adr_i => resized_addr,
sl_dat_i => wb_data_i,
sl_dat_i => wb_dat_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
sl_stb_i => wb_stb_i,
sl_we_i => wb_we_i,
sl_dat_o => wb_data_o,
sl_dat_o => wb_dat_o,
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o);
......@@ -333,7 +332,7 @@ begin -- behavioral
else
if(ns_overflow = '1') then
pps_out_o <= '1';
pps_out_o <= ppsg_escr_pps_valid;
width_cntr <= unsigned(ppsg_cr_pwidth);
else
if(width_cntr = to_unsigned(0, width_cntr'length)) then
......@@ -427,6 +426,5 @@ begin -- behavioral
tm_utc_o <= std_logic_vector(cntr_utc);
tm_cycles_o <= std_logic_vector(cntr_nsec);
tm_time_valid_o <= ppsg_escr_tm_valid;
pps_valid_o <= ppsg_escr_pps_valid;
end behavioral;
......@@ -29,7 +29,7 @@ library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity xwb_pps_gen is
entity xwr_pps_gen is
generic(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
......@@ -49,17 +49,16 @@ entity xwb_pps_gen is
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
pps_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic
);
end xwb_pps_gen;
end xwr_pps_gen;
architecture behavioral of xwb_pps_gen is
architecture behavioral of xwr_pps_gen is
component wrsw_pps_gen is
component wr_pps_gen is
generic(
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity
......@@ -68,9 +67,9 @@ architecture behavioral of xwb_pps_gen is
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
......@@ -80,7 +79,6 @@ architecture behavioral of xwb_pps_gen is
pps_in_i : in std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
pps_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic
......@@ -89,7 +87,7 @@ architecture behavioral of xwb_pps_gen is
begin -- behavioral
WRAPPED_PPSGEN : wrsw_pps_gen
WRAPPED_PPSGEN : wr_pps_gen
generic map(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity
......@@ -98,9 +96,9 @@ begin -- behavioral
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
wb_addr_i => slave_i.adr(4 downto 0),
wb_data_i => slave_i.dat,
wb_data_o => slave_o.dat,
wb_adr_i => slave_i.adr(4 downto 0),
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
......@@ -110,7 +108,6 @@ begin -- behavioral
pps_in_i => pps_in_i,
pps_csync_o => pps_csync_o,
pps_out_o => pps_out_o,
pps_valid_o => pps_valid_o,
tm_utc_o => tm_utc_o,
tm_cycles_o => tm_cycles_o,
tm_time_valid_o => tm_time_valid_o
......
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/pps_gen.html -V pps_gen_wb.vhd -C ../../../software/include/hw/pps_gen_regs.h --cstyle defines --lang vhdl -K ../../sim/pps_gen_regs.v wrsw_pps_gen.wb
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