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White Rabbit core collection
Commits
f1530b6b
Commit
f1530b6b
authored
Oct 27, 2011
by
Tomasz Wlostowski
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wr_pps_gen: naming convention fixes, pps_valid rerouted to disable/enable the PPS output
parent
49c340a6
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8 changed files
with
31 additions
and
33 deletions
+31
-33
Manifest.py
modules/wr_pps_gen/Manifest.py
+3
-0
build_wb.sh
modules/wr_pps_gen/build_wb.sh
+4
-0
pps_gen_regs.h
modules/wr_pps_gen/pps_gen_regs.h
+0
-0
pps_gen_wb.vhd
modules/wr_pps_gen/pps_gen_wb.vhd
+3
-3
pps_gen_wb.wb
modules/wr_pps_gen/pps_gen_wb.wb
+0
-0
wr_pps_gen.vhd
modules/wr_pps_gen/wr_pps_gen.vhd
+10
-12
xwr_pps_gen.vhd
modules/wr_pps_gen/xwr_pps_gen.vhd
+11
-14
build_wb.sh
modules/wrsw_pps_gen/build_wb.sh
+0
-4
No files found.
modules/wr
sw
_pps_gen/Manifest.py
→
modules/wr_pps_gen/Manifest.py
View file @
f1530b6b
files
=
[
"pps_gen_wb.vhd"
,
"wr
sw
_pps_gen.vhd"
,
"xw
b
_pps_gen.vhd"
];
"wr_pps_gen.vhd"
,
"xw
r
_pps_gen.vhd"
];
modules/wr_pps_gen/build_wb.sh
0 → 100755
View file @
f1530b6b
#!/bin/bash
mkdir
-p
doc
wbgen2
-D
./doc/pps_gen.html
-V
pps_gen_wb.vhd
-C
pps_gen_regs.h
--cstyle
defines
--lang
vhdl
-K
../../sim/pps_gen_regs.v pps_gen_wb.wb
modules/wr
sw
_pps_gen/pps_gen_regs.h
→
modules/wr_pps_gen/pps_gen_regs.h
View file @
f1530b6b
File moved
modules/wr
sw
_pps_gen/pps_gen_wb.vhd
→
modules/wr_pps_gen/pps_gen_wb.vhd
View file @
f1530b6b
...
...
@@ -2,11 +2,11 @@
-- Title : Wishbone slave core for WR Switch PPS generator and RTC
---------------------------------------------------------------------------------------
-- File : pps_gen_wb.vhd
-- Author : auto-generated by wbgen2 from
wrsw_pps_gen
.wb
-- Created : Thu Oct 27 2
1:29:19
2011
-- Author : auto-generated by wbgen2 from
pps_gen_wb
.wb
-- Created : Thu Oct 27 2
3:53:31
2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE
wrsw_pps_gen
.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE
pps_gen_wb
.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
...
...
modules/wr
sw_pps_gen/wrsw_pps_gen
.wb
→
modules/wr
_pps_gen/pps_gen_wb
.wb
View file @
f1530b6b
File moved
modules/wr
sw_pps_gen/wrsw
_pps_gen.vhd
→
modules/wr
_pps_gen/wr
_pps_gen.vhd
View file @
f1530b6b
...
...
@@ -29,7 +29,7 @@ library work;
use
work
.
gencores_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
entity
wr
sw
_pps_gen
is
entity
wr_pps_gen
is
generic
(
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
...
...
@@ -40,9 +40,9 @@ entity wrsw_pps_gen is
rst_n_i
:
in
std_logic
;
wb_ad
d
r_i
:
in
std_logic_vector
(
4
downto
0
);
wb_dat
a
_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat
a
_o
:
out
std_logic_vector
(
31
downto
0
);
wb_adr_i
:
in
std_logic_vector
(
4
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
...
...
@@ -56,14 +56,13 @@ entity wrsw_pps_gen is
pps_csync_o
:
out
std_logic
;
pps_out_o
:
out
std_logic
;
pps_valid_o
:
out
std_logic
;
tm_utc_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
tm_time_valid_o
:
out
std_logic
);
end
wr
sw
_pps_gen
;
end
wr_pps_gen
;
architecture
behavioral
of
wr
sw
_pps_gen
is
architecture
behavioral
of
wr_pps_gen
is
constant
c_PERIOD
:
integer
:
=
125000000
;
...
...
@@ -160,7 +159,7 @@ architecture behavioral of wrsw_pps_gen is
begin
-- behavioral
resized_addr
(
4
downto
0
)
<=
wb_ad
d
r_i
;
resized_addr
(
4
downto
0
)
<=
wb_adr_i
;
resized_addr
(
c_wishbone_address_width
-1
downto
5
)
<=
(
others
=>
'0'
);
U_Adapter
:
wb_slave_adapter
...
...
@@ -177,12 +176,12 @@ begin -- behavioral
master_i
=>
wb_out
,
master_o
=>
wb_in
,
sl_adr_i
=>
resized_addr
,
sl_dat_i
=>
wb_dat
a
_i
,
sl_dat_i
=>
wb_dat_i
,
sl_sel_i
=>
wb_sel_i
,
sl_cyc_i
=>
wb_cyc_i
,
sl_stb_i
=>
wb_stb_i
,
sl_we_i
=>
wb_we_i
,
sl_dat_o
=>
wb_dat
a
_o
,
sl_dat_o
=>
wb_dat_o
,
sl_ack_o
=>
wb_ack_o
,
sl_stall_o
=>
wb_stall_o
);
...
...
@@ -333,7 +332,7 @@ begin -- behavioral
else
if
(
ns_overflow
=
'1'
)
then
pps_out_o
<=
'1'
;
pps_out_o
<=
ppsg_escr_pps_valid
;
width_cntr
<=
unsigned
(
ppsg_cr_pwidth
);
else
if
(
width_cntr
=
to_unsigned
(
0
,
width_cntr
'length
))
then
...
...
@@ -427,6 +426,5 @@ begin -- behavioral
tm_utc_o
<=
std_logic_vector
(
cntr_utc
);
tm_cycles_o
<=
std_logic_vector
(
cntr_nsec
);
tm_time_valid_o
<=
ppsg_escr_tm_valid
;
pps_valid_o
<=
ppsg_escr_pps_valid
;
end
behavioral
;
modules/wr
sw_pps_gen/xwb
_pps_gen.vhd
→
modules/wr
_pps_gen/xwr
_pps_gen.vhd
View file @
f1530b6b
...
...
@@ -29,7 +29,7 @@ library work;
use
work
.
gencores_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
entity
xw
b
_pps_gen
is
entity
xw
r
_pps_gen
is
generic
(
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
...
...
@@ -49,17 +49,16 @@ entity xwb_pps_gen is
pps_csync_o
:
out
std_logic
;
pps_out_o
:
out
std_logic
;
pps_valid_o
:
out
std_logic
;
tm_utc_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
tm_time_valid_o
:
out
std_logic
);
end
xw
b
_pps_gen
;
end
xw
r
_pps_gen
;
architecture
behavioral
of
xw
b
_pps_gen
is
architecture
behavioral
of
xw
r
_pps_gen
is
component
wr
sw
_pps_gen
is
component
wr_pps_gen
is
generic
(
g_interface_mode
:
t_wishbone_interface_mode
;
g_address_granularity
:
t_wishbone_address_granularity
...
...
@@ -68,9 +67,9 @@ architecture behavioral of xwb_pps_gen is
clk_ref_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
wb_ad
d
r_i
:
in
std_logic_vector
(
4
downto
0
);
wb_dat
a
_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat
a
_o
:
out
std_logic_vector
(
31
downto
0
);
wb_adr_i
:
in
std_logic_vector
(
4
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
...
...
@@ -80,7 +79,6 @@ architecture behavioral of xwb_pps_gen is
pps_in_i
:
in
std_logic
;
pps_csync_o
:
out
std_logic
;
pps_out_o
:
out
std_logic
;
pps_valid_o
:
out
std_logic
;
tm_utc_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
tm_time_valid_o
:
out
std_logic
...
...
@@ -89,7 +87,7 @@ architecture behavioral of xwb_pps_gen is
begin
-- behavioral
WRAPPED_PPSGEN
:
wr
sw
_pps_gen
WRAPPED_PPSGEN
:
wr_pps_gen
generic
map
(
g_interface_mode
=>
g_interface_mode
,
g_address_granularity
=>
g_address_granularity
...
...
@@ -98,9 +96,9 @@ begin -- behavioral
clk_ref_i
=>
clk_ref_i
,
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
wb_ad
d
r_i
=>
slave_i
.
adr
(
4
downto
0
),
wb_dat
a
_i
=>
slave_i
.
dat
,
wb_dat
a
_o
=>
slave_o
.
dat
,
wb_adr_i
=>
slave_i
.
adr
(
4
downto
0
),
wb_dat_i
=>
slave_i
.
dat
,
wb_dat_o
=>
slave_o
.
dat
,
wb_cyc_i
=>
slave_i
.
cyc
,
wb_sel_i
=>
slave_i
.
sel
,
wb_stb_i
=>
slave_i
.
stb
,
...
...
@@ -110,7 +108,6 @@ begin -- behavioral
pps_in_i
=>
pps_in_i
,
pps_csync_o
=>
pps_csync_o
,
pps_out_o
=>
pps_out_o
,
pps_valid_o
=>
pps_valid_o
,
tm_utc_o
=>
tm_utc_o
,
tm_cycles_o
=>
tm_cycles_o
,
tm_time_valid_o
=>
tm_time_valid_o
...
...
modules/wrsw_pps_gen/build_wb.sh
deleted
100755 → 0
View file @
49c340a6
#!/bin/bash
mkdir
-p
doc
wbgen2
-D
./doc/pps_gen.html
-V
pps_gen_wb.vhd
-C
../../../software/include/hw/pps_gen_regs.h
--cstyle
defines
--lang
vhdl
-K
../../sim/pps_gen_regs.v wrsw_pps_gen.wb
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