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White Rabbit core collection
Commit f1b7521d authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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Merge branch 'greg-cute-1p' into proposed_master

parents 9347bd38 edd3bd31
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board/cute/Manifest.py 0 → 100644
View file @ f1b7521d
files = [
"wr_cute_pkg.vhd",
"xwrc_board_cute.vhd",
]
modules = {
"local" : [
"../common",
]
}
board/cute/wr_cute_pkg.vhd 0 → 100644
View file @ f1b7521d
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for CUTE package
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_cute_pkg.vhd
-- Author(s) : Hongming Li <lihm.thu@foxmail.com>
-- Company : Tsinghua Univ. (DEP)
-- Created : 2018-07-14
-- Last update: 2018-07-14
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wr_board_pkg.all;
use work.streamers_pkg.all;
package wr_cute_pkg is
component xwrc_board_cute is
generic(
g_simulation : integer := 0;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 0;
g_fabric_iface : t_board_fabric_iface := plain;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_dpram_initf : string := "default_xilinx";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0;
-- CUTE special
g_cute_version : string := "2.2";
g_sfp0_enable : integer := 1;
g_sfp1_enable : integer := 0;
g_phy_refclk_sel : integer := 0;
g_multiboot_enable : boolean := false);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
clk_20m_vcxo_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp0_p_i : in std_logic :='0';
clk_125m_gtp0_n_i : in std_logic :='0';
clk_125m_gtp1_p_i : in std_logic :='0';
clk_125m_gtp1_n_i : in std_logic :='0';
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
clk_10m_ext_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
plldac_clr_n_o : out std_logic;
plldac_load_n_o : out std_logic;
plldac_sync_n_o : out std_logic;
sfp0_txp_o : out std_logic;
sfp0_txn_o : out std_logic;
sfp0_rxp_i : in std_logic := '0';
sfp0_rxn_i : in std_logic := '0';
sfp0_det_i : in std_logic := '0';
sfp0_sda_i : in std_logic := '1';
sfp0_sda_o : out std_logic;
sfp0_scl_i : in std_logic := '1';
sfp0_scl_o : out std_logic;
sfp0_rate_select_o : out std_logic;
sfp0_tx_fault_i : in std_logic := '0';
sfp0_tx_disable_o : out std_logic;
sfp0_los_i : in std_logic := '0';
sfp1_txp_o : out std_logic;
sfp1_txn_o : out std_logic;
sfp1_rxp_i : in std_logic := '0';
sfp1_rxn_i : in std_logic := '0';
sfp1_det_i : in std_logic := '0';
sfp1_sda_i : in std_logic := '1';
sfp1_sda_o : out std_logic;
sfp1_scl_i : in std_logic := '1';
sfp1_scl_o : out std_logic;
sfp1_rate_select_o : out std_logic;
sfp1_tx_fault_i : in std_logic := '0';
sfp1_tx_disable_o : out std_logic;
sfp1_los_i : in std_logic := '0';
eeprom_sda_i : in std_logic := '1';
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic := '1';
eeprom_scl_o : out std_logic;
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic := '1';
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_i : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
pps_csync_o : out std_logic;
link_ok_o : out std_logic);
end component xwrc_board_cute;
constant c_xwb_tcpip_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000001103", -- thu
device_id => x"c0413599",
version => x"00000001",
date => x"20160424",
name => "wr-tcp-ip-stack ")));
end wr_cute_pkg;
board/cute/xwrc_board_cute.vhd 0 → 100644
View file @ f1b7521d
This diff is collapsed.
modules/timing/Manifest.py
View file @ f1b7521d
......@@ -3,5 +3,6 @@ files = ["dmtd_phase_meas.vhd",
"multi_dmtd_with_deglitcher.vhd",
"hpll_period_detect.vhd",
"pulse_gen.vhd",
"oserdes_4_to_1.vhd",
"pulse_stamper.vhd" ]
modules/timing/oserdes_4_to_1.vhd 0 → 100644
View file @ f1b7521d
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity oserdes_4_to_1 is
generic
(-- width of the data for the system
sys_w : integer := 1;
-- width of the data for the device
dev_w : integer := 4);
port
(
-- from the device out to the system
data_out_from_device : in std_logic_vector(dev_w-1 downto 0);
data_out_to_pins : out std_logic_vector(sys_w-1 downto 0);
-- input, output delay control signals
delay_reset : in std_logic; -- active high synchronous reset for input delay
-- clock and reset signals
clk_in : in std_logic;
pll_locked : in std_logic;
clk_div_in : in std_logic;
io_reset : in std_logic); -- reset signal for io circuit
end oserdes_4_to_1;
architecture xilinx of oserdes_4_to_1 is
constant num_serial_bits : integer := dev_w/sys_w;
signal ioclk : std_logic;
type serdarr is array (0 to 3) of std_logic_vector(sys_w-1 downto 0);
-- array to use intermediately from the serdes to the internal
-- devices. bus "0" is the leftmost bus
-- * fills in from higher order
signal oserdes_d : serdarr := (( others => (others => '0')));
signal serdesstrobe : std_logic;
-- delay ctrl
signal data_out_to_pins_predelay : std_logic_vector(sys_w-1 downto 0);
signal data_delay : std_logic_vector(sys_w-1 downto 0);
type loadarr is array (0 to 15) of std_logic_vector(4 downto 0);
signal intap : loadarr := (( others => (others => '0')));
signal outtap : loadarr := (( others => (others => '0')));
begin
bufpll_inst : bufpll
generic map (
divide => 4, -- divclk divider (1-8)
enable_sync => true -- enable synchrnonization between pll and gclk (true/false)
)
port map (
ioclk => ioclk, -- 1-bit output: output i/o clock
lock => open, -- 1-bit output: synchronized lock output
serdesstrobe => serdesstrobe, -- 1-bit output: output serdes strobe (connect to iserdes2/oserdes2)
gclk => clk_div_in, -- 1-bit input: bufg clock input
locked => pll_locked, -- 1-bit input: locked input from pll
pllin => clk_in -- 1-bit input: clock input from pll
);
-- we have multiple bits- step over every bit, instantiating the required elements
pins: for pin_count in 0 to sys_w-1 generate
begin
data_out_to_pins(pin_count) <= data_delay(pin_count);
iodelay2_inst : iodelay2
generic map (
counter_wraparound => "wraparound", -- "stay_at_limit" or "wraparound"
data_rate => "sdr", -- "sdr" or "ddr"
delay_src => "odatain", -- "io", "odatain" or "idatain"
idelay2_value => 0, -- delay value when idelay_mode="pci" (0-255)
idelay_mode => "normal", -- "normal" or "pci"
idelay_type => "default", -- "fixed", "default", "variable_from_zero", "variable_from_half_max"
-- or "diff_phase_detector"
idelay_value => 0, -- amount of taps for fixed input delay (0-255)
odelay_value => 33, -- amount of taps fixed output delay (0-255)
serdes_mode => "none", -- "none", "master" or "slave"
sim_tapdelay_value => 75 -- per tap delay used for simulation in ps
)
port map (
busy => open, -- 1-bit output: busy output after cal
dataout => open, -- 1-bit output: delayed data output to iserdes/input register
dataout2 => open, -- 1-bit output: delayed data output to general fpga fabric
dout => data_delay(pin_count), -- 1-bit output: delayed data output
tout => open, -- 1-bit output: delayed 3-state output
cal => '0', -- 1-bit input: initiate calibration input
ce => '0', -- 1-bit input: enable inc input
clk => clk_div_in, -- 1-bit input: clock input
idatain => '0', -- 1-bit input: data input (connect to top-level port or i/o buffer)
inc => '0', -- 1-bit input: increment / decrement input
ioclk0 => ioclk, -- 1-bit input: input from the i/o clock network
ioclk1 => '0', -- 1-bit input: input from the i/o clock network
odatain => data_out_to_pins_predelay(pin_count), -- 1-bit input: output data input from output register or oserdes2.
rst => delay_reset, -- 1-bit input: reset to zero or 1/2 of total delay period
t => '0' -- 1-bit input: 3-state input signal
);
-- instantiate the serdes primitive
-- declare the oserdes
oserdes2_inst : oserdes2
generic map (
bypass_gclk_ff => false, -- bypass clkdiv syncronization registers (true/false)
data_rate_oq => "sdr", -- output data rate ("sdr" or "ddr")
data_rate_ot => "sdr", -- 3-state data rate ("sdr" or "ddr")
data_width => 4, -- parallel data width (2-8)
output_mode => "single_ended", -- "single_ended" or "differential"
serdes_mode => "none", -- "none", "master" or "slave"
train_pattern => 0 -- training pattern (0-15)
)
port map (
oq => data_out_to_pins_predelay(pin_count), -- 1-bit output: data output to pad or iodelay2
shiftout1 => open, -- 1-bit output: cascade data output
shiftout2 => open, -- 1-bit output: cascade 3-state output
shiftout3 => open, -- 1-bit output: cascade differential data output
shiftout4 => open, -- 1-bit output: cascade differential 3-state output
tq => open, -- 1-bit output: 3-state output to pad or iodelay2
clk0 => ioclk, -- 1-bit input: i/o clock input
clk1 => '0', -- 1-bit input: secondary i/o clock input
clkdiv => clk_div_in, -- 1-bit input: logic domain clock input
-- d1 - d4: 1-bit (each) input: parallel data inputs
d1 => oserdes_d(3)(pin_count),
d2 => oserdes_d(2)(pin_count),
d3 => oserdes_d(1)(pin_count),
d4 => oserdes_d(0)(pin_count),
ioce => serdesstrobe, -- 1-bit input: data strobe input
oce => '1', -- 1-bit input: clock enable input
rst => io_reset, -- 1-bit input: asynchrnous reset input
shiftin1 => '1', -- 1-bit input: cascade data input
shiftin2 => '1', -- 1-bit input: cascade 3-state input
shiftin3 => '1', -- 1-bit input: cascade differential data input
shiftin4 => '1', -- 1-bit input: cascade differential 3-state input
-- t1 - t4: 1-bit (each) input: 3-state control inputs
t1 => '0',
t2 => '0',
t3 => '0',
t4 => '0',
tce => '0', -- 1-bit input: 3-state clock enable input
train => '0' -- 1-bit input: training pattern enable input
);
out_slices: for slice_count in 0 to num_serial_bits-1 generate begin
-- this places the first data in time on the right
oserdes_d(4-slice_count-1)(pin_count) <=
data_out_from_device(slice_count);
-- to place the first data in time on the left, use the
-- following code, instead
-- oserdes_d(slice_count) <=
-- data_out_from_device(slice_count);
end generate out_slices;
end generate pins;
end xilinx;
modules/wr_dacs/Manifest.py
View file @ f1b7521d
files = [
"spec_serial_dac_arb.vhd",
"spec_serial_dac.vhd"
"spec_serial_dac.vhd",
"cute_serial_dac_arb.vhd",
"cute_serial_dac.vhd"
]
modules/wr_dacs/cute_serial_dac.vhd 0 → 100644
View file @ f1b7521d
-------------------------------------------------------------------------------
-- Title : Serial DAC interface
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : serial_dac.vhd
-- Author : paas, slayer
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2011-05-10
-- Platform : fpga-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: The dac unit provides an interface to a 16 bit serial Digita to
-- Analogue converter (max5441, SPI?/QSPI?/MICROWIRE? compatible)
--
-------------------------------------------------------------------------------
-- Copyright (c) 2010 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :1
-- Date Version Author Description
-- 2009-01-24 1.0 paas Created
-- 2010-02-25 1.1 slayer Modified for rev 1.1 switch
-- 2012-10-15 2.0 pwb Modified for AD5663R of CUTE-WR
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cute_serial_dac is
generic (
g_num_data_bits : integer := 16;
g_num_extra_bits : integer := 8
);
port (
-- clock & reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- channel 1 value and value load strobe
cmd_i : in std_logic_vector(g_num_extra_bits-1 downto 0);
value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
load_i : in std_logic;
-- SCLK divider: 000 = clk_i/8 ... 111 = clk_i/1024
sclk_divsel_i : in std_logic_vector(2 downto 0);
-- DAC I/F
dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic;
dac_sync_n_o : out std_logic;
xdone_o : out std_logic
);
end cute_serial_dac;
architecture syn of cute_serial_dac is
signal divider : unsigned(11 downto 0);
signal dataSh : std_logic_vector(g_num_data_bits + g_num_extra_bits-1 downto 0);
signal bitCounter : std_logic_vector(g_num_data_bits + g_num_extra_bits+1 downto 0);
signal endSendingData : std_logic;
signal sendingData : std_logic;
signal iDacClk : std_logic;
signal iValidValue : std_logic;
signal divider_muxed : std_logic;
begin
-- Modified by Weibin
select_divider : process (divider, sclk_divsel_i)
begin -- process
case sclk_divsel_i is
when "000" => divider_muxed <= divider(2); -- sclk = clk_i/8
when "001" => divider_muxed <= divider(3); -- sclk = clk_i/16
when "010" => divider_muxed <= divider(4); -- sclk = clk_i/32
when "011" => divider_muxed <= divider(5); -- sclk = clk_i/64
when "100" => divider_muxed <= divider(6); -- sclk = clk_i/128
when "101" => divider_muxed <= divider(7); -- sclk = clk_i/256
when "110" => divider_muxed <= divider(8); -- sclk = clk_i/512
when "111" => divider_muxed <= divider(9); -- sclk = clk_i/1024
when others => null;
end case;
end process;
iValidValue <= load_i;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
sendingData <= '0';
else
if iValidValue = '1' and sendingData = '0' then
sendingData <= '1';
elsif endSendingData = '1' then
sendingData <= '0';
end if;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if iValidValue = '1' then
divider <= (divider'high downto 1 => '0') & '1';
elsif sendingData = '1' then
if(divider_muxed = '1') then
divider <= (divider'high downto 1 => '0') & '1';
else
divider <= divider + 1;
end if;
elsif endSendingData = '1' then
divider <= (divider'high downto 1 => '0') & '1';
end if;
end if;
end process;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
iDacClk <= '1'; -- 0
else
if iValidValue = '1' then
iDacClk <= '1'; -- 0
elsif divider_muxed = '1' then
iDacClk <= not(iDacClk);
elsif endSendingData = '1' then
iDacClk <= '1'; -- 0
end if;
end if;
end if;
end process;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
dataSh <= (others => '0');
else
if iValidValue = '1' and sendingData = '0' then
dataSh(g_num_data_bits-1 downto 0) <= value_i;
dataSh(dataSh'left downto g_num_data_bits) <= cmd_i;
elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then
dataSh(0) <= dataSh(dataSh'left);
dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0);
end if;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if iValidValue = '1' and sendingData = '0' then
bitCounter(0) <= '1';
bitCounter(bitCounter'left downto 1) <= (others => '0');
elsif sendingData = '1' and to_integer(divider) = 1 and iDacClk = '1' then
bitCounter(0) <= '0';
bitCounter(bitCounter'left downto 1) <= bitCounter(bitCounter'left - 1 downto 0);
end if;
end if;
end process;
endSendingData <= bitCounter(bitCounter'left);
xdone_o <= not SendingData;
dac_sdata_o <= dataSh(dataSh'left);
dac_sync_n_o <= not sendingData;
dac_sclk_o <= iDacClk;
end syn;
modules/wr_dacs/cute_serial_dac_arb.vhd 0 → 100644
View file @ f1b7521d
-------------------------------------------------------------------------------
-- Title : CUTE serial DAC interface with arbiter
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : cute_serial_dac.vhd
-- Author : Pan Weibin
-- Company : Tsinghua Univ.
-- Platform : fpga-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
--
-- Copyright (c) 2018 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cute_serial_dac_arb is
generic(
g_invert_sclk : boolean;
g_num_extra_bits : integer
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
val1_i : in std_logic_vector(15 downto 0);
load1_i : in std_logic;
val2_i : in std_logic_vector(15 downto 0);
load2_i : in std_logic;
dac_ldac_n_o : out std_logic;
dac_clr_n_o : out std_logic;
dac_sync_n_o : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic);
end cute_serial_dac_arb;
architecture behavioral of cute_serial_dac_arb is
component cute_serial_dac
generic (
g_num_data_bits : integer;
g_num_extra_bits : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
cmd_i : in std_logic_vector(g_num_extra_bits-1 downto 0);
load_i : in std_logic;
sclk_divsel_i : in std_logic_vector(2 downto 0);
dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic;
dac_sync_n_o : out std_logic;
xdone_o : out std_logic);
end component;
signal d1, d2 : std_logic_vector(15 downto 0);
signal d1_ready, d2_ready : std_logic;
signal dac_data : std_logic_vector(15 downto 0);
signal dac_load : std_logic;
signal dac_cs_sel : std_logic_vector(1 downto 0);
signal dac_done : std_logic;
signal dac_sclk_int : std_logic;
signal dac_cmd : std_logic_vector(g_num_extra_bits-1 downto 0);
signal init_cnt : unsigned(7 downto 0);
type t_state is (INIT, ENABLE_INT_REF, WAIT_DONE, LOAD_DAC, WAIT_DATA);
signal state : t_state;
signal trig0 : std_logic_vector(31 downto 0);
signal trig1 : std_logic_vector(31 downto 0);
signal trig2 : std_logic_vector(31 downto 0);
signal trig3 : std_logic_vector(31 downto 0);
signal CONTROL0 : std_logic_vector(35 downto 0);
begin -- behavioral
dac_clr_n_o <= '1';
dac_ldac_n_o <= '0';
U_DAC : cute_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => g_num_extra_bits)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
value_i => dac_data,
cmd_i => dac_cmd,
load_i => dac_load,
sclk_divsel_i => "001",
dac_sclk_o => dac_sclk_int,
dac_sdata_o => dac_din_o,
dac_sync_n_o => dac_sync_n_o,
xdone_o => dac_done);
p_drive_sclk: process(dac_sclk_int)
begin
if(g_invert_sclk) then
dac_sclk_o <= not dac_sclk_int;
else
dac_sclk_o <= dac_sclk_int;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
d1 <= (others => '0');
d1_ready <= '0';
d2 <= (others => '0');
d2_ready <= '0';
dac_load <= '0';
init_cnt <= (others => '0');
state <= INIT;
else
if(load1_i = '1' or load2_i = '1') then
if(load1_i = '1') then
d1_ready <= '1';
d1 <= val1_i;
end if;
if(load2_i = '1') then
d2_ready <= '1';
d2 <= val2_i;
end if;
else
case state is
when INIT =>
if init_cnt(6) = '1' then
state <= ENABLE_INT_REF;
else
init_cnt <= init_cnt +1;
end if;
when ENABLE_INT_REF =>
dac_cmd <= "00111000";
dac_data <= (dac_data'high downto 1 => '0') & '0'; -- internal reference setup
dac_load <= '1';
state <= LOAD_DAC;
when WAIT_DATA =>
if(d1_ready = '1') then
dac_data <= d1;
dac_cmd <= "00011001"; -- write and update DAC B
dac_load <= '1';
d1_ready <= '0';
state <= LOAD_DAC;
elsif(d2_ready = '1') then
dac_data <= d2;
dac_cmd <= "00011000"; -- write and update DAC A
dac_load <= '1';
d2_ready <= '0';
state <= LOAD_DAC;
end if;
when LOAD_DAC=>
dac_load <= '0';
state <= WAIT_DONE;
when WAIT_DONE =>
if(dac_done = '1') then
state <= WAIT_DATA;
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
end behavioral;
platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd
View file @ f1b7521d
......@@ -37,6 +37,8 @@ entity WHITERABBITGTP_WRAPPER_TILE_SPARTAN6 is
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
REFSELDYPLL0 : in std_logic_vector(2 downto 0):=(others=>'0');
REFSELDYPLL1 : in std_logic_vector(2 downto 0):=(others=>'0');
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT : out std_logic;
RXCHARISK1_OUT : out std_logic;
......@@ -483,8 +485,8 @@ begin
REFCLKPLL1 => open,
REFCLKPWRDNB0 => tied_to_vcc_i,
REFCLKPWRDNB1 => tied_to_vcc_i,
REFSELDYPLL0 => tied_to_ground_vec_i(2 downto 0),
REFSELDYPLL1 => tied_to_ground_vec_i(2 downto 0),
REFSELDYPLL0 => REFSELDYPLL0,
REFSELDYPLL1 => REFSELDYPLL1,
RESETDONE0 => RESETDONE0_OUT,
RESETDONE1 => RESETDONE1_OUT,
TSTCLK0 => tied_to_ground_i,
......
platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd
View file @ f1b7521d
......@@ -66,7 +66,7 @@ entity wr_gtp_phy_spartan6 is
-- Port 0
-- dedicated GTP clock input
gtp_clk_i : in std_logic;
gtp0_clk_i : in std_logic;
-- TX path, synchronous to ch0_ref_clk_i
ch0_ref_clk_i : in std_logic;
......@@ -118,6 +118,9 @@ entity wr_gtp_phy_spartan6 is
ch0_rdy_o : out std_logic;
-- Port 1
-- dedicated GTP clock input
gtp1_clk_i : in std_logic;
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
......@@ -137,6 +140,10 @@ entity wr_gtp_phy_spartan6 is
ch1_tx_prbs_sel_i: in std_logic_vector(2 downto 0) := (others=>'0');
ch1_rdy_o : out std_logic;
-- PLL source
ch0_ref_sel_pll : in std_logic_vector(2 downto 0);
ch1_ref_sel_pll : in std_logic_vector(2 downto 0);
-- Serial I/O
pad_txn0_o : out std_logic;
......@@ -183,6 +190,8 @@ architecture rtl of wr_gtp_phy_spartan6 is
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
REFSELDYPLL0 : in std_logic_vector(2 downto 0):=(others=>'0');
REFSELDYPLL1 : in std_logic_vector(2 downto 0):=(others=>'0');
RXCHARISK0_OUT : out std_logic;
RXCHARISK1_OUT : out std_logic;
RXDISPERR0_OUT : out std_logic;
......@@ -387,8 +396,8 @@ begin -- rtl
ch0_gtp_reset <= ch0_rst_synced or std_logic(not ch0_reset_counter(ch0_reset_counter'left));
ch0_rx_rec_clk_pad <= ch0_gtp_clkout_int(1);
ch0_ref_clk_in(0) <= gtp_clk_i;
ch0_ref_clk_in(1) <= '0';
ch0_ref_clk_in(0) <= gtp0_clk_i;
ch0_ref_clk_in(1) <= gtp1_clk_i;
-- Near-end PMA loopback or loopback selected with ch1_loopen_vec_i
ch0_gtp_loopback <= "010" when(ch0_loopen_i = '1') else
ch0_loopen_vec_i;
......@@ -554,8 +563,8 @@ begin -- rtl
ch1_gtp_reset <= ch1_rst_synced or std_logic(not ch1_reset_counter(ch1_reset_counter'left));
ch1_rx_rec_clk_pad <= ch1_gtp_clkout_int(1);
ch1_ref_clk_in(0) <= gtp_clk_i;
ch1_ref_clk_in(1) <= '0';
ch1_ref_clk_in(0) <= gtp0_clk_i;
ch1_ref_clk_in(1) <= gtp1_clk_i;
-- Near-end PMA loopback or loopback selected with ch1_loopen_vec_i
ch1_gtp_loopback <= "010" when(ch1_loopen_i = '1') else
ch1_loopen_vec_i;
......@@ -740,7 +749,8 @@ begin -- rtl
PLLLKDET1_OUT => ch1_gtp_pll_lockdet,
RESETDONE0_OUT => ch0_gtp_reset_done,
RESETDONE1_OUT => ch1_gtp_reset_done,
REFSELDYPLL0 => ch0_ref_sel_pll,
REFSELDYPLL1 => ch1_ref_sel_pll,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT => ch0_rx_k_int,
RXCHARISK1_OUT => ch1_rx_k_int,
......
platform/xilinx/wr_xilinx_pkg.vhd
View file @ f1b7521d
......@@ -41,11 +41,12 @@ package wr_xilinx_pkg is
-- Configuration of used-defined aux PLL clocks
type t_auxpll_cfg is record
enabled : boolean;
bufg_en : boolean;
divide : integer;
end record t_auxpll_cfg;
type t_auxpll_cfg_array is array (0 to 3) of t_auxpll_cfg;
constant c_AUXPLL_CFG_DEFAULT : t_auxpll_cfg := (FALSE, 1);
constant c_AUXPLL_CFG_DEFAULT : t_auxpll_cfg := (FALSE, FALSE, 1);
constant c_AUXPLL_CFG_ARRAY_DEFAULT : t_auxpll_cfg_array := (others=>c_AUXPLL_CFG_DEFAULT);
component xwrc_platform_xilinx is
......@@ -57,6 +58,7 @@ package wr_xilinx_pkg is
g_gtp_enable_ch0 : integer := 0;
g_gtp_enable_ch1 : integer := 1;
g_gtp_mux_enable : boolean := FALSE;
g_phy_refclk_sel : integer range 0 to 7 := 0;
g_simulation : integer := 0
);
port (
......@@ -96,6 +98,7 @@ package wr_xilinx_pkg is
pll_aux_locked_o : out std_logic;
clk_62m5_sys_o : out std_logic;
clk_125m_ref_o : out std_logic;
clk_20m_o : out std_logic;
clk_ref_locked_o : out std_logic;
clk_62m5_dmtd_o : out std_logic;
pll_locked_o : out std_logic;
......@@ -116,7 +119,7 @@ package wr_xilinx_pkg is
g_enable_ch1 : integer := 1;
g_simulation : integer := 0);
port (
gtp_clk_i : in std_logic;
gtp0_clk_i : in std_logic;
ch0_ref_clk_i : in std_logic := '0';
ch0_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch0_tx_k_i : in std_logic := '0';
......@@ -132,6 +135,7 @@ package wr_xilinx_pkg is
ch0_loopen_vec_i : in std_logic_vector(2 downto 0) := (others => '0');
ch0_tx_prbs_sel_i : in std_logic_vector(2 downto 0) := (others => '0');
ch0_rdy_o : out std_logic;
gtp1_clk_i : in std_logic;
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
......@@ -147,6 +151,8 @@ package wr_xilinx_pkg is
ch1_loopen_vec_i : in std_logic_vector(2 downto 0) := (others => '0');
ch1_tx_prbs_sel_i : in std_logic_vector(2 downto 0) := (others => '0');
ch1_rdy_o : out std_logic;
ch0_ref_sel_pll : in std_logic_vector(2 downto 0) := (others => '0');
ch1_ref_sel_pll : in std_logic_vector(2 downto 0) := (others => '0');
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
......
platform/xilinx/xwrc_platform_xilinx.vhd
View file @ f1b7521d
......@@ -41,6 +41,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.endpoint_pkg.all;
......@@ -65,6 +66,8 @@ entity xwrc_platform_xilinx is
-- Select GTP channel to use
g_gtp_enable_ch0 : integer := 0;
g_gtp_enable_ch1 : integer := 1;
-- Select PHY reference clock
g_phy_refclk_sel : integer range 0 to 7 := 0;
g_gtp_mux_enable : boolean := FALSE;
-- Set to TRUE will speed up some initialization processes
g_simulation : integer := 0);
......@@ -147,6 +150,7 @@ entity xwrc_platform_xilinx is
-- PLL outputs
clk_62m5_sys_o : out std_logic;
clk_125m_ref_o : out std_logic;
clk_20m_o : out std_logic;
clk_ref_locked_o : out std_logic;
clk_62m5_dmtd_o : out std_logic;
pll_locked_o : out std_logic;
......@@ -235,6 +239,7 @@ begin -- architecture rtl
-- 125MHz reference clock
gen_spartan6_default_plls : if (g_fpga_family = "spartan6") generate
signal clk_20m : std_logic;
signal clk_sys : std_logic;
signal clk_sys_out : std_logic;
signal clk_sys_fb : std_logic;
......@@ -262,13 +267,14 @@ begin -- architecture rtl
CLKOUT0_DIVIDE => 16,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8,
-- 1st aux user clock parameters
CLKOUT1_DIVIDE => g_aux_pll_cfg(0).divide,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
-- Aux user clocks parameters
CLKOUT2_DIVIDE => g_aux_pll_cfg(0).divide,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
-- The rest of aux user clocks parameters
CLKOUT3_DIVIDE => g_aux_pll_cfg(1).divide,
CLKOUT3_PHASE => 0.000,
CLKOUT3_DUTY_CYCLE => 0.500,
......@@ -284,8 +290,10 @@ begin -- architecture rtl
port map (
CLKFBOUT => clk_sys_fb,
CLKOUT0 => clk_sys,
CLKOUT1 => clk_125m_pllref_buf_int2,
CLKOUT2 => clk_pll_aux(0),
CLKOUT1 => clk_pll_aux(0), -- required for 500MHz generation for
-- Cute-WR. This is because 500MHz goes then to BUFPLL which can input
-- only CLKOUT0/1 from PLL_BASE.
CLKOUT2 => clk_125m_pllref_buf_int2,
CLKOUT3 => clk_pll_aux(1),
CLKOUT4 => clk_pll_aux(2),
CLKOUT5 => clk_pll_aux(3),
......@@ -300,14 +308,20 @@ begin -- architecture rtl
O => clk_125m_pllref_buf_int1,
I => clk_125m_pllref_i);
-- DDR PLL global clock buffers
-- PLL aux clocks buffers
gen_auxclk_bufs: for I in 0 to 3 generate
gen_auxclk_enabled: if g_aux_pll_cfg(I).enabled = TRUE generate
-- Aux PLL_BASE clocks with BUFG enabled
gen_auxclk_bufg_en: if g_aux_pll_cfg(I).enabled = TRUE and g_aux_pll_cfg(I).bufg_en = TRUE generate
cmp_auxclk_bufg : BUFG
port map (
O => clk_pll_aux_o(I),
I => clk_pll_aux(I));
end generate;
-- Aux PLL_BASE clocks with BUFG disabled
gen_auxclk_no_bufg: if g_aux_pll_cfg(I).enabled = TRUE and g_aux_pll_cfg(I).bufg_en = FALSE generate
clk_pll_aux_o(I) <= clk_pll_aux(I);
end generate;
-- Disabled aux PLL_BASE clocks
gen_auxclk_disabled: if g_aux_pll_cfg(I).enabled = FALSE generate
clk_pll_aux_o(I) <= '0';
end generate;
......@@ -325,6 +339,7 @@ begin -- architecture rtl
O => clk_125m_pllref_buf,
I => clk_125m_pllref_buf_int2);
clk_20m_o <= clk_20m_vcxo_buf;
clk_62m5_sys_o <= clk_sys_out;
clk_125m_ref_o <= clk_125m_pllref_buf;
pll_locked_o <= pll_sys_locked and pll_dmtd_locked;
......@@ -1031,7 +1046,9 @@ begin -- architecture rtl
gen_phy_spartan6 : if(g_fpga_family = "spartan6") generate
signal clk_125m_gtp_buf : std_logic;
signal clk_125m_gtp_buf : std_logic;
signal clk_125m_gtp1_buf : std_logic;
signal clk_125m_gtp0_buf : std_logic;
signal ch0_phy8_out, ch1_phy8_out : t_phy_8bits_to_wrc;
......@@ -1059,7 +1076,7 @@ begin -- architecture rtl
g_enable_ch0 => g_gtp_enable_ch0,
g_enable_ch1 => g_gtp_enable_ch1)
port map (
gtp_clk_i => clk_125m_gtp_buf,
gtp0_clk_i => clk_125m_gtp0_buf,
ch0_ref_clk_i => clk_125m_pllref_buf,
ch0_tx_data_i => phy8_i.tx_data,
ch0_tx_k_i => phy8_i.tx_k(0),
......@@ -1075,6 +1092,8 @@ begin -- architecture rtl
ch0_loopen_vec_i => phy8_i.loopen_vec,
ch0_tx_prbs_sel_i => phy8_i.tx_prbs_sel,
ch0_rdy_o => ch0_phy8_out.rdy,
ch0_ref_sel_pll => std_logic_vector(to_unsigned(g_phy_refclk_sel, 3)),
gtp1_clk_i => clk_125m_gtp1_buf,
ch1_ref_clk_i => clk_125m_pllref_buf,
ch1_tx_data_i => phy8_i.tx_data,
ch1_tx_k_i => phy8_i.tx_k(0),
......@@ -1090,6 +1109,7 @@ begin -- architecture rtl
ch1_loopen_vec_i => phy8_i.loopen_vec,
ch1_tx_prbs_sel_i => phy8_i.tx_prbs_sel,
ch1_rdy_o => ch1_phy8_out.rdy,
ch1_ref_sel_pll => std_logic_vector(to_unsigned(g_phy_refclk_sel, 3)),
pad_txn0_o => ch0_sfp_txn,
pad_txp0_o => ch0_sfp_txp,
pad_rxn0_i => ch0_sfp_rxn,
......@@ -1101,6 +1121,8 @@ begin -- architecture rtl
);
gen_gtp_ch0 : if (g_gtp_enable_ch0 = 1 and g_gtp_enable_ch1 = 0) generate
clk_125m_gtp0_buf <= clk_125m_gtp_buf;
clk_125m_gtp1_buf <= '0';
ch0_phy8_out.ref_clk <= clk_125m_pllref_buf;
ch0_phy8_out.sfp_tx_fault <= sfp_tx_fault_i;
ch0_phy8_out.sfp_los <= sfp_los_i;
......@@ -1112,6 +1134,8 @@ begin -- architecture rtl
end generate gen_gtp_ch0;
gen_gtp_ch1 : if (g_gtp_enable_ch0 = 0 and g_gtp_enable_ch1 = 1) generate
clk_125m_gtp0_buf <= '0';
clk_125m_gtp1_buf <= clk_125m_gtp_buf;
ch1_phy8_out.ref_clk <= clk_125m_pllref_buf;
ch1_phy8_out.sfp_tx_fault <= sfp_tx_fault_i;
ch1_phy8_out.sfp_los <= sfp_los_i;
......
syn/cute_core_ref_design/Manifest.py 0 → 100644
View file @ f1b7521d
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "csg324"
syn_top = "cute_core_ref_top"
syn_project = "cute_core_ref.xise"
syn_tool = "ise"
modules = { "local" : "../../top/cute_ref_design/"}
syn/cute_core_ref_design/README 0 → 100644
View file @ f1b7521d
As there are thousands of nodes in LHAASO project, we merge the WR function with
user module into one FPGA. So they just need the cute_core. The
syn/cute_core_ref is used to generate the ngc for them.
syn/cute_ref_design/Makefile 0 → 100644
View file @ f1b7521d
This diff is collapsed.
syn/cute_ref_design/Manifest.py 0 → 100644
View file @ f1b7521d
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "csg324"
syn_top = "cute_wr_ref_top"
syn_project = "cute_wr_ref.xise"
syn_tool = "ise"
modules = { "local" : "../../top/cute_ref_design/"}
syn/cute_ref_design/cute_wr_ref.xise 0 → 100644
View file @ f1b7521d
This diff is collapsed.
top/cute_ref_design/Manifest.py 0 → 100644
View file @ f1b7521d
fetchto = "../../ip_cores"
files = [
"cute_wr_ref_top.vhd",
"cute_wr_ref_top.ucf",
]
modules = {
"local" : [
"../../",
"../../board/cute",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
}
top/cute_ref_design/cute_core_ref_top.vhd 0 → 100644
View file @ f1b7521d
This diff is collapsed.
top/cute_ref_design/cute_wr_ref_top.ucf 0 → 100644
View file @ f1b7521d
config vccaux = 3.3;
# bank 0
#net "clk1_m2c_p" loc = b3;net "clk1_m2c_p" iostandard = lvds_33;
#net "clk1_m2c_n" loc = a3;net "clk1_m2c_n" iostandard = lvds_33;
#net "la03_p" loc = e6;net "la03_p" iostandard = lvds_33;
#net "la03_n" loc = f7;net "la03_n" iostandard = lvds_33;
#net "la01_cc_p" loc = g8;net "la01_cc_p" iostandard = lvds_33;
#net "la01_cc_n" loc = e8;net "la01_cc_n" iostandard = lvds_33;
#net "la20_p" loc = g9;net "la20_p" iostandard = lvds_33;
#net "la20_n" loc = g11;net "la20_n" iostandard = lvds_33;
#net "la30_p" loc = c15;net "la30_p" iostandard = lvds_33;
#net "la30_n" loc = a15;net "la30_n" iostandard = lvds_33;
#net "la29_p" loc = b16;net "la29_p" iostandard = lvds_33;
#net "la29_n" loc = a16;net "la29_n" iostandard = lvds_33;
#net "la24_p" loc = e14;net "la24_p" iostandard = lvds_33;
#net "la24_n" loc = d15;net "la24_n" iostandard = lvds_33;
net "clk_125m_pllref_p_i" loc = f12;
net "clk_125m_pllref_p_i" iostandard = lvds_33;
net "clk_125m_pllref_n_i" loc = e12;
net "clk_125m_pllref_n_i" iostandard = lvds_33;
# bank 1
net "pps_out" loc = c18;net "pps_out" iostandard = lvcmos33;
net "usr_led1" loc = e18;net "usr_led1" iostandard = lvcmos33;
net "usr_led2" loc = d17;net "usr_led2" iostandard = lvcmos33;
#net "sfp1_tx_los" loc = f18;net "sfp1_tx_los" iostandard = lvcmos33;
#net "sfp1_tx_fault" loc = h16;net "sfp1_tx_fault" iostandard = lvcmos33;
#net "sfp1_det" loc = g16;net "sfp1_det" iostandard = lvcmos33;
#net "sfp1_scl" loc = g18;net "sfp1_scl" iostandard = lvcmos33;
#net "sfp1_sda" loc = h17;net "sfp1_sda" iostandard = lvcmos33;
#net "sfp1_tx_disable" loc = h18;net "sfp1_tx_disable" iostandard = lvcmos33;
net "eeprom_sda" loc = j18;net "eeprom_sda" iostandard = lvcmos33;
net "eeprom_scl" loc = k17;net "eeprom_scl" iostandard = lvcmos33;
#net "la32_p" loc = p17;net "la32_p" iostandard = lvds_33;
#net "la32_n" loc = p18;net "la32_n" iostandard = lvds_33;
#net "la33_p" loc = t17;net "la33_p" iostandard = lvds_33;
#net "la33_n" loc = t18;net "la33_n" iostandard = lvds_33;
#net "la31_p" loc = u17;net "la31_p" iostandard = lvds_33;
#net "la31_n" loc = u18;net "la31_n" iostandard = lvds_33;
# bank 2
net "flash_sclk_o" loc = r15;net "flash_sclk_o" iostandard = lvcmos33;
net "flash_ncs_o" loc = v3;net "flash_ncs_o" iostandard = lvcmos33;
net "flash_mosi_o" loc = t13;net "flash_mosi_o" iostandard = lvcmos33;
net "flash_miso_i" loc = r13;net "flash_miso_i" iostandard = lvcmos33;
#net "la28_p" loc = u16;net "la28_p" iostandard = lvds_33;
#net "la28_n" loc = v16;net "la28_n" iostandard = lvds_33;
#net "la25_p" loc = u15;net "la25_p" iostandard = lvds_33;
#net "la25_n" loc = v15;net "la25_n" iostandard = lvds_33;
#net "la26_p" loc = t14;net "la26_p" iostandard = lvds_33;
#net "la26_n" loc = v14;net "la26_n" iostandard = lvds_33;
#net "la21_p" loc = u13;net "la21_p" iostandard = lvds_33;
#net "la21_n" loc = v13;net "la21_n" iostandard = lvds_33;
#net "la27_p" loc = m11;net "la27_p" iostandard = lvds_33;
#net "la27_n" loc = n11;net "la27_n" iostandard = lvds_33;
#net "la18_cc_p" loc = r11;net "la18_cc_p" iostandard = lvds_33;
#net "la18_cc_n" loc = t11;net "la18_cc_n" iostandard = lvds_33;
#net "la22_p" loc = t12;net "la22_p" iostandard = lvds_33;
#net "la22_n" loc = v12;net "la22_n" iostandard = lvds_33;
#net "la23_p" loc = n10;net "la23_p" iostandard = lvds_33;
#net "la23_n" loc = p11;net "la23_n" iostandard = lvds_33;
#net "la14_p" loc = m10;net "la14_p" iostandard = lvds_33;
#net "la14_n" loc = n9;net "la14_n" iostandard = lvds_33;
#net "la15_p" loc = u11;net "la15_p" iostandard = lvds_33;
#net "la15_n" loc = v11;net "la15_n" iostandard = lvds_33;
#net "la19_p" loc = r10;net "la19_p" iostandard = lvds_33;
#net "la19_n" loc = t10;net "la19_n" iostandard = lvds_33;
#net "la07_p" loc = u10;net "la07_p" iostandard = lvds_33;
#net "la07_n" loc = v10;net "la07_n" iostandard = lvds_33;
#net "la16_p" loc = r8;net "la16_p" iostandard = lvds_33;
#net "la16_n" loc = t8;net "la16_n" iostandard = lvds_33;
#net "la13_p" loc = t9;net "la13_p" iostandard = lvds_33;
#net "la13_n" loc = v9;net "la13_n" iostandard = lvds_33;
#net "la17_cc_p" loc = m8;net "la17_cc_p" iostandard = lvds_33;
#net "la17_cc_n" loc = n8;net "la17_cc_n" iostandard = lvds_33;
#net "la04_p" loc = t8;net "la04_p" iostandard = lvds_33;
#net "la04_n" loc = v8;net "la04_n" iostandard = lvds_33;
#net "la02_p" loc = u7;net "la02_p" iostandard = lvds_33;
#net "la02_n" loc = v7;net "la02_n" iostandard = lvds_33;
#net "la00_cc_p" loc = n7;net "la00_cc_p" iostandard = lvds_33;
#net "la00_cc_n" loc = p8;net "la00_cc_n" iostandard = lvds_33;
#net "la09_p" loc = t6;net "la09_p" iostandard = lvds_33;
#net "la09_n" loc = v6;net "la09_n" iostandard = lvds_33;
#net "la11_p" loc = r7;net "la11_p" iostandard = lvds_33;
#net "la11_n" loc = t7;net "la11_n" iostandard = lvds_33;
#net "la12_p" loc = n6;net "la12_p" iostandard = lvds_33;
#net "la12_n" loc = p7;net "la12_n" iostandard = lvds_33;
#net "la10_p" loc = r5;net "la10_p" iostandard = lvds_33;
#net "la10_n" loc = t5;net "la10_n" iostandard = lvds_33;
#net "clk0_m2c_p" loc = u5;net "clk0_m2c_p" iostandard = lvds_33;
#net "clk0_m2c_n" loc = v5;net "clk0_m2c_n" iostandard = lvds_33;
#net "la08_p" loc = r3;net "la08_p" iostandard = lvds_33;
#net "la08_n" loc = t3;net "la08_n" iostandard = lvds_33;
#net "la06_p" loc = t4;net "la06_p" iostandard = lvds_33;
#net "la06_n" loc = v4;net "la06_n" iostandard = lvds_33;
#net "la05_p" loc = n5;net "la05_p" iostandard = lvds_33;
#net "la05_n" loc = p6;net "la05_n" iostandard = lvds_33;
# bank 3
net "clk20m_vcxo_i" loc = h1;net "clk20m_vcxo_i" iostandard = lvcmos33;
net "usr_button" loc = h3;net "usr_button" iostandard = lvcmos33;
net "one_wire" loc = h2;net "one_wire" iostandard = lvcmos33;
net "uart_rx" loc = j1;net "uart_rx" iostandard = lvcmos33;
net "uart_tx" loc = j3;net "uart_tx" iostandard = lvcmos33;
net "plldac_din" loc = c1;net "plldac_din" iostandard = lvcmos33;
net "plldac_clr_n" loc = e1;net "plldac_clr_n" iostandard = lvcmos33;
net "plldac_sclk" loc = c2;net "plldac_sclk" iostandard = lvcmos33;
net "plldac_sync_n" loc = d1;net "plldac_sync_n" iostandard = lvcmos33;
net "plldac_load_n" loc = d2;net "plldac_load_n" iostandard = lvcmos33;
net "sfp1_led" loc = g3;net "sfp1_led" iostandard = lvcmos33;
net "sfp0_led" loc = k4;net "sfp0_led" iostandard = lvcmos33;
net "sfp0_los" loc = g1;net "sfp0_los" iostandard = lvcmos33;
net "sfp0_det" loc = f3;net "sfp0_det" iostandard = lvcmos33;
net "sfp0_scl" loc = f1;net "sfp0_scl" iostandard = lvcmos33;
net "sfp0_sda" loc = e4;net "sfp0_sda" iostandard = lvcmos33;
net "sfp0_tx_fault" loc = d3;net "sfp0_tx_fault" iostandard = lvcmos33;
net "sfp0_tx_disable" loc = e3;net "sfp0_tx_disable" iostandard = lvcmos33;
# bank gtp
net "sfp0_ref_clk_n" loc = c9;net "sfp0_ref_clk_n" iostandard = lvcmos33;
net "sfp0_ref_clk_p" loc = d9;net "sfp0_ref_clk_p" iostandard = lvcmos33;
net "sfp0_rx_n" loc = c7;
net "sfp0_rx_p" loc = d7;
net "sfp0_tx_n" loc = a6;
net "sfp0_tx_p" loc = b6;
#net "sfp1_ref_clk_n" loc = e10;net "sfp1_ref_clk_n" iostandard = lvcmos33;
#net "sfp1_ref_clk_p" loc = f10;net "sfp1_ref_clk_p" iostandard = lvcmos33;
#net "sfp1_rx_n" loc = c13;
#net "sfp1_rx_p" loc = d13;
#net "sfp1_tx_n" loc = a14;
#net "sfp1_tx_p" loc = b14;
#net "mgtrx0_n" loc = c5;
#net "mgtrx0_p" loc = d5;
#net "mgttx0_n" loc = a4;
#net "mgttx0_p" loc = b4;
#---------------------------------------------------------------------------------------------
# clock period information
#---------------------------------------------------------------------------------------------
NET "clk20m_vcxo_i" TNM_NET = clk20m_vcxo_i;
TIMESPEC TS_clk20m_vcxo_i = PERIOD "clk20m_vcxo_i" 50 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "sfp0_ref_clk_p" TNM_NET = sfp0_ref_clk_p;
TIMESPEC TS_sfp0_ref_clk_p = PERIOD "sfp0_ref_clk_p" 8 ns HIGH 50%;
NET "sfp0_ref_clk_n" TNM_NET = sfp0_ref_clk_n;
TIMESPEC TS_sfp0_ref_clk_n = PERIOD "sfp0_ref_clk_n" 8 ns HIGH 50%;
NET "u_wr_core/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch*_gtp_clkout_int<1>" TNM_NET = u_wr_core/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch*_gtp_clkout_int<1>;
TIMESPEC TS_u_wr_core_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch_gtp_clkout_int_1_ = PERIOD "u_wr_core/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch*_gtp_clkout_int<1>" 8 ns HIGH 50%;
inst "pps_out" iob = force;
net "pps_out" drive = 24 | slew = fast;
#cute-wr-dp V2.1
#net "ext_clk" loc = f2;net "ext_clk" iostandard = lvcmos33;
#cute-wr-dp V2.2
net "ext_clk" loc = k3;net "ext_clk" iostandard = lvcmos33;
net "ext_clk" drive = 24 | slew = fast;
top/cute_ref_design/cute_wr_ref_top.vhd 0 → 100644
View file @ f1b7521d
This diff is collapsed.
top/readme_platforms.txt
View file @ f1b7521d
......@@ -2,4 +2,5 @@ Available device plaftorms (so far):
------------------------------------
gsi_scu - GSI's Scalable Control Unit (SCU), based on Altera ArriaII-GX (EP2AGX125)
spec_1_1 - CERN's Simple PCI-Express Carrier (SPEC), based on Xilinx Spartan-6 (XC6SLX45). Version 1.1 or newer (pin-compatible)
\ No newline at end of file
spec_1_1 - CERN's Simple PCI-Express Carrier (SPEC), based on Xilinx Spartan-6 (XC6SLX45). Version 1.1 or newer (pin-compatible)
cute - TSINGHUA's CUTEDP, based on Xilinx Spartan-6 (XC6SLX45T).
\ No newline at end of file
top/spec_1_1/wr_streamers_demo/spec_top.vhd
View file @ f1b7521d
......@@ -632,7 +632,8 @@ begin
g_enable_ch1 => 1,
g_simulation => g_simulation)
port map (
gtp_clk_i => clk_gtp,
gtp0_clk_i => '0',
gtp1_clk_i => clk_gtp,
ch1_ref_clk_i => clk_ref,
......
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