Commit f402d342 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

wr_softpll_ng: initial version of DMTD-based external reference PLL

parent 4177c4b6
etherbone-core @ b29565ac
Subproject commit b29565ac63ca92987cd9a9a754b6add857fc5351
general-cores @ 45cf9797
Subproject commit 45cf97977fdb5e451491a5a24af408ea6df4858a
gn4124-core @ 5fd1a8b1
Subproject commit 5fd1a8b14063464eef714be14d79d36550080cb4
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2013-07-29
-- Last update: 2014-07-15
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -132,7 +132,6 @@ architecture rtl of dmtd_with_deglitcher is
signal stab_cntr : unsigned(15 downto 0);
signal free_cntr : unsigned(g_counter_bits-1 downto 0);
signal in_d0, in_d1 : std_logic;
signal s_one : std_logic;
signal clk_in : std_logic;
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-09-02
-- Last update: 2013-08-05
-- Last update: 2014-07-15
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -180,49 +180,14 @@ architecture behavioral of wr_pps_gen is
signal retime_counter : unsigned(4 downto 0);
signal pps_valid_int : std_logic;
signal pps_out_int : std_logic;
signal pps_out_int : std_logic;
signal pps_in_refclk : std_logic;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
end component;
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
signal control0 : std_logic_vector(35 downto 0);
signal trig0, trig1, trig2, trig3 : std_logic_vector(31 downto 0);
begin -- behavioral
--CS_ICON : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL0);
--CS_ILA : chipscope_ila
-- port map (
-- CONTROL => CONTROL0,
-- CLK => clk_sys_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
TRIG0(cntr_pps_ext'length-1 downto 0) <= std_logic_vector(cntr_pps_ext);
TRIG1(0) <= pps_ext_retimed;
TRIG1(1) <= pps_in_i;
TRIG1(6 downto 2) <= std_logic_vector(retime_counter);
TRIG1(7) <= pps_ext_d0;
resized_addr(4 downto 0) <= wb_adr_i;
resized_addr(c_wishbone_address_width-1 downto 5) <= (others => '0');
......@@ -250,7 +215,7 @@ begin -- behavioral
sl_stall_o => wb_stall_o);
sync_reset_refclk : gc_sync_ffs
U_Sync_reset_refclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -261,6 +226,15 @@ begin -- behavioral
npulse_o => open,
ppulse_o => open);
U_Sync_pps_refclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_ref_i,
rst_n_i => '1',
data_i => pps_in_i,
ppulse_o => pps_in_refclk);
ppsg_cntr_nsec <= std_logic_vector(cntr_nsec);
ppsg_cntr_utclo <= std_logic_vector(cntr_utc(31 downto 0));
......@@ -290,80 +264,36 @@ begin -- behavioral
end if;
end process;
gen_with_external_clock_input : if(g_with_ext_clock_input) generate
-- retime the external PPS pulse. The output (pps_ext_retimed) is:
-- single clk_ext_i cycle-wide
-- produced one cycle in advance with respect to the original PPS
p_retime_external_pps : process(clk_ext_i)
begin
if rising_edge(clk_ext_i) then
if rst_n_i = '0' then
cntr_pps_ext <= (others => '0');
pps_ext_d0 <= '0';
pps_ext_retimed <= '0';
else
pps_ext_d0 <= pps_in_i;
if(cntr_pps_ext = g_ext_clock_rate-1) then
pps_ext_retimed <= '1';
else
pps_ext_retimed <= '0';
end if;
if(pps_in_i = '1' and pps_ext_d0 = '0') then
cntr_pps_ext <= to_unsigned(1, cntr_pps_ext'length);
elsif(cntr_pps_ext /= g_ext_clock_rate) then
cntr_pps_ext <= cntr_pps_ext + 1;
end if;
end if;
end if;
end process;
p_retime_counter : process(clk_ref_i)
begin
if falling_edge(clk_ref_i) then
if rst_synced_refclk = '0' or sync_in_progress = '0' or pps_ext_retimed = '0' then
retime_counter <= (others => '0');
else
retime_counter <= retime_counter + 1;
end if;
end if;
end process;
gen_without_external_clock_input : if(not g_with_ext_clock_input) generate
ext_sync_p <= '0';
end generate gen_without_external_clock_input;
gen_with_external_clock_input : if(g_with_ext_clock_input) generate
-- Warning! this state machine inputs pps_ext_retimed signal,
-- which is produced in different clock domain than clk_ref_i.
-- Run only when EXT channel of the SoftPLL is LOCKED!
p_external_sync : process(clk_ref_i)
begin
if falling_edge(clk_ref_i) then
if(rst_synced_refclk = '0') then
ext_sync_p <= '0';
sync_in_progress <= '0';
ppsg_escr_sync_in <= '0';
else
if(ppsg_escr_sync_load = '1') then
sync_in_progress <= ppsg_escr_sync_out;
ppsg_escr_sync_in <= '0';
end if;
-- retime counter == last faster clock edge inside the retimed PPS
-- pulse -> we should sync ourselves
if(sync_in_progress = '1' and pps_ext_retimed = '1' and retime_counter = (g_ref_clock_rate / g_ext_clock_rate - 1)) then
ext_sync_p <= '1';
sync_in_progress <= '0';
ppsg_escr_sync_in <= '1';
else
ext_sync_p <= '0';
if(sync_in_progress = '1' and pps_in_refclk = '1')
then
ext_sync_p <= '1';
sync_in_progress <= '0';
ppsg_escr_sync_in <= '1';
else
ext_sync_p <= '0';
end if;
end if;
end if;
end if;
end process;
end generate gen_with_external_clock_input;
-- Nanosecond counter. Counts from 0 to c_PERIOD-1 every clk_ref_i cycle.
......
files = ["spll_period_detect.vhd",
"spll_bangbang_pd.vhd",
# "spll_bangbang_pd.vhd",
"spll_wbgen2_pkg.vhd",
"spll_aligner.vhd",
"wr_softpll_ng.vhd",
"xwr_softpll_ng.vhd",
"softpll_pkg.vhd",
......
......@@ -6,18 +6,24 @@ use ieee.numeric_std.all;
package softpll_pkg is
constant c_softpll_max_aux_clocks : integer := 8;
type t_softpll_phase_detector_type is (CH_DDMTD, CH_BANGBANG);
type t_softpll_channel_config_array is array(0 to c_softpll_max_aux_clocks-1) of t_softpll_phase_detector_type;
constant c_softpll_default_channel_config : t_softpll_channel_config_array := (others => CH_DDMTD);
-- External 10 MHz input divider parameters.
constant c_softpll_ext_div_ref : integer := 8;
constant c_softpll_ext_div_fb : integer := 50;
constant c_softpll_ext_log2_gating : integer := 13;
constant c_softpll_out_status_off : std_logic_vector(3 downto 0) := "0000";
constant c_softpll_out_status_locking : std_logic_vector(3 downto 0) := "0001";
constant c_softpll_out_status_locked : std_logic_vector(3 downto 0) := "0010";
constant c_softpll_out_status_aligning : std_logic_vector(3 downto 0) := "0011";
constant c_softpll_out_status_holdover : std_logic_vector(3 downto 0) := "0100";
end package;
package body softpll_pkg is
......
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity spll_aligner is
generic (
g_counter_width : integer := 28;
g_ref_clock_rate : integer := 125000000;
g_in_clock_rate : integer := 10000000;
g_sample_rate : integer := 100
);
port (
clk_sys_i : in std_logic;
clk_in_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_sys_i : in std_logic;
pps_ext_a_i : in std_logic;
pps_csync_p1_i : in std_logic;
sample_cref_o : out std_logic_vector(g_counter_width-1 downto 0);
sample_cin_o : out std_logic_vector(g_counter_width-1 downto 0);
sample_pps_o : out std_logic;
sample_valid_o : out std_logic;
sample_ack_i : in std_logic
);
end spll_aligner;
architecture rtl of spll_aligner is
constant c_div_ticks : integer := g_ref_clock_rate / g_sample_rate;
signal cnt_ref_bin, cnt_in_bin, cnt_in_bin_x : unsigned(g_counter_width-1 downto 0);
signal cnt_in_gray, cnt_in_gray_x, cnt_in_gray_xd : std_logic_vector(g_counter_width-1 downto 0);
signal cnt_ref_div : unsigned(g_counter_width-1 downto 0);
signal pps_ext_p, pps_ext_d0 : std_logic;
signal rst_n_in, rst_n_ref : std_logic;
signal ref_div_p : std_logic;
signal sample_ready_p : std_logic;
begin
U_Reset_IN : gc_sync_ffs
port map (
clk_i => clk_in_i,
rst_n_i => '1',
data_i => rst_n_sys_i,
synced_o => rst_n_in);
U_Reset_REF : gc_sync_ffs
port map (
clk_i => clk_ref_i,
rst_n_i => '1',
data_i => rst_n_sys_i,
synced_o => rst_n_ref);
p_ref_counter : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if pps_csync_p1_i = '1' or rst_n_ref = '0' then
cnt_ref_bin <= to_unsigned(0, g_counter_width);
elsif(cnt_ref_bin = g_ref_clock_rate - 1) then
cnt_ref_bin <= (others => '0');
else
cnt_ref_bin <= cnt_ref_bin + 1;
end if;
end if;
end process;
p_samplerate_divider : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if pps_csync_p1_i = '1' or rst_n_ref = '0' then
ref_div_p <= '0';
cnt_ref_div <= to_unsigned(0, g_counter_width);
elsif (cnt_ref_div = c_div_ticks - 2) then
ref_div_p <= '1';
cnt_ref_div <= cnt_ref_div + 1;
elsif (cnt_ref_div = c_div_ticks - 1) then
ref_div_p <= '0';
cnt_ref_div <= (others => '0');
else
ref_div_p <= '0';
cnt_ref_div <= cnt_ref_div + 1;
end if;
end if;
end process;
p_delay_ext_pps : process(clk_in_i)
begin
if rising_edge(clk_in_i) then
pps_ext_d0 <= pps_ext_a_i;
end if;
end process;
pps_ext_p <= not pps_ext_d0 and pps_ext_a_i;
p_in_counter : process(clk_in_i)
begin
if rising_edge(clk_in_i) then
if pps_ext_p = '1' or rst_n_in = '0' then
cnt_in_bin <= to_unsigned(2, g_counter_width);
elsif(cnt_in_bin = g_in_clock_rate - 1) then
cnt_in_bin <= (others => '0');
else
cnt_in_bin <= cnt_in_bin + 1;
end if;
end if;
end process;
p_in_bin2gray : process (clk_in_i)
begin
if rising_edge(clk_in_i) then
cnt_in_gray <= f_gray_encode (std_logic_vector(cnt_in_bin));
end if;
end process;
p_sample_difference : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
cnt_in_gray_x <= cnt_in_gray;
cnt_in_gray_xd <= cnt_in_gray_x;
if(ref_div_p = '1') then
sample_cin_o <= f_gray_decode(cnt_in_gray_xd, 1);
sample_cref_o <= std_logic_vector (cnt_ref_bin);
end if;
end if;
end process;
U_sync_sampling : gc_pulse_synchronizer2
port map (
clk_in_i => clk_ref_i,
rst_in_n_i => rst_n_ref,
clk_out_i => clk_sys_i,
rst_out_n_i => rst_n_sys_i,
d_p_i => ref_div_p,
q_p_o => sample_ready_p);
p_gen_sample_valid : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_sys_i = '0' then
sample_valid_o <= '0';
else
if sample_ready_p = '1' then
sample_valid_o <= '1';
elsif sample_ack_i = '1' then
sample_valid_o <= '0';
end if;
end if;
end if;
end process;
end rtl;
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wb_slave.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Thu Jul 25 11:14:53 2013
-- Created : Tue Jul 15 17:31:20 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -24,7 +24,7 @@ entity spll_wb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -43,7 +43,6 @@ end spll_wb_slave;
architecture syn of spll_wb_slave is
signal spll_eccr_ext_en_int : std_logic ;
signal spll_eccr_align_en_int : std_logic ;
signal spll_occr_out_lock_int : std_logic_vector(7 downto 0);
signal spll_deglitch_thr_int : std_logic_vector(15 downto 0);
signal spll_dfr_host_rst_n : std_logic ;
......@@ -74,7 +73,7 @@ signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal rwaddr_reg : std_logic_vector(5 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
......@@ -98,7 +97,10 @@ begin
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
spll_eccr_ext_en_int <= '0';
spll_eccr_align_en_int <= '0';
regs_o.al_cr_valid_load_o <= '0';
regs_o.f_dmtd_valid_load_o <= '0';
regs_o.f_ref_valid_load_o <= '0';
regs_o.f_ext_valid_load_o <= '0';
spll_occr_out_lock_int <= "00000000";
regs_o.rcer_load_o <= '0';
regs_o.ocer_load_o <= '0';
......@@ -108,12 +110,6 @@ begin
spll_deglitch_thr_int <= "0000000000000000";
regs_o.dfr_spll_value_wr_o <= '0';
regs_o.dfr_spll_eos_wr_o <= '0';
regs_o.crr_in_load_o <= '0';
regs_o.crr_out_load_o <= '0';
regs_o.aux_cr_aux_sel_wr_o <= '0';
regs_o.aux_cr_div_ref_wr_o <= '0';
regs_o.aux_cr_div_fb_wr_o <= '0';
regs_o.aux_cr_gate_wr_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -125,6 +121,10 @@ begin
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
regs_o.al_cr_valid_load_o <= '0';
regs_o.f_dmtd_valid_load_o <= '0';
regs_o.f_ref_valid_load_o <= '0';
regs_o.f_ext_valid_load_o <= '0';
regs_o.rcer_load_o <= '0';
regs_o.ocer_load_o <= '0';
regs_o.dac_hpll_wr_o <= '0';
......@@ -132,17 +132,15 @@ begin
regs_o.dac_main_dac_sel_wr_o <= '0';
regs_o.dfr_spll_value_wr_o <= '0';
regs_o.dfr_spll_eos_wr_o <= '0';
regs_o.crr_in_load_o <= '0';
regs_o.crr_out_load_o <= '0';
regs_o.aux_cr_aux_sel_wr_o <= '0';
regs_o.aux_cr_div_ref_wr_o <= '0';
regs_o.aux_cr_div_fb_wr_o <= '0';
regs_o.aux_cr_gate_wr_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
ack_in_progress <= '0';
else
regs_o.al_cr_valid_load_o <= '0';
regs_o.f_dmtd_valid_load_o <= '0';
regs_o.f_ref_valid_load_o <= '0';
regs_o.f_ext_valid_load_o <= '0';
regs_o.rcer_load_o <= '0';
regs_o.ocer_load_o <= '0';
regs_o.dac_hpll_wr_o <= '0';
......@@ -150,51 +148,44 @@ begin
regs_o.dac_main_dac_sel_wr_o <= '0';
regs_o.dfr_spll_value_wr_o <= '0';
regs_o.dfr_spll_eos_wr_o <= '0';
regs_o.crr_in_load_o <= '0';
regs_o.crr_out_load_o <= '0';
regs_o.aux_cr_aux_sel_wr_o <= '0';
regs_o.aux_cr_div_ref_wr_o <= '0';
regs_o.aux_cr_div_fb_wr_o <= '0';
regs_o.aux_cr_gate_wr_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(4 downto 0) is
when "00000" =>
case rwaddr_reg(5 downto 0) is
when "000000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(5 downto 0) <= "000000";
rddata_reg(13 downto 8) <= regs_i.csr_n_ref_i;
rddata_reg(18 downto 16) <= regs_i.csr_n_out_i;
rddata_reg(19) <= regs_i.csr_dbg_supported_i;
rddata_reg(13 downto 8) <= "000000";
rddata_reg(21 downto 16) <= regs_i.csr_n_ref_i;
rddata_reg(26 downto 24) <= regs_i.csr_n_out_i;
rddata_reg(27) <= regs_i.csr_dbg_supported_i;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001" =>
when "000001" =>
if (wb_we_i = '1') then
spll_eccr_ext_en_int <= wrdata_reg(0);
spll_eccr_align_en_int <= wrdata_reg(2);
end if;
rddata_reg(0) <= spll_eccr_ext_en_int;
rddata_reg(1) <= regs_i.eccr_ext_supported_i;
rddata_reg(2) <= spll_eccr_align_en_int;
rddata_reg(3) <= regs_i.eccr_align_done_i;
rddata_reg(4) <= regs_i.eccr_ext_ref_present_i;
rddata_reg(2) <= regs_i.eccr_ext_ref_present_i;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
......@@ -224,13 +215,18 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
when "000010" =>
if (wb_we_i = '1') then
spll_occr_out_lock_int <= wrdata_reg(15 downto 8);
regs_o.al_cr_valid_load_o <= '1';
end if;
rddata_reg(7 downto 0) <= regs_i.occr_out_en_i;
rddata_reg(15 downto 8) <= spll_occr_out_lock_int;
rddata_reg(23 downto 16) <= regs_i.occr_out_det_type_i;
rddata_reg(8 downto 0) <= regs_i.al_cr_valid_i;
rddata_reg(17 downto 9) <= regs_i.al_cr_required_i;
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
......@@ -241,48 +237,57 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101" =>
when "000011" =>
if (wb_we_i = '1') then
regs_o.rcer_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.rcer_i;
rddata_reg(31 downto 0) <= regs_i.al_cref_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
when "000100" =>
if (wb_we_i = '1') then
regs_o.ocer_load_o <= '1';
end if;
rddata_reg(7 downto 0) <= regs_i.ocer_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(31 downto 0) <= regs_i.al_cin_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000101" =>
if (wb_we_i = '1') then
regs_o.f_dmtd_valid_load_o <= '1';
end if;
rddata_reg(27 downto 0) <= regs_i.f_dmtd_freq_i;
rddata_reg(28) <= regs_i.f_dmtd_valid_i;
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000" =>
when "000110" =>
if (wb_we_i = '1') then
regs_o.dac_hpll_wr_o <= '1';
regs_o.f_ref_valid_load_o <= '1';
end if;
rddata_reg(27 downto 0) <= regs_i.f_ref_freq_i;
rddata_reg(28) <= regs_i.f_ref_valid_i;
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000111" =>
if (wb_we_i = '1') then
regs_o.f_ext_valid_load_o <= '1';
end if;
rddata_reg(27 downto 0) <= regs_i.f_ext_freq_i;
rddata_reg(28) <= regs_i.f_ext_valid_i;
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001000" =>
if (wb_we_i = '1') then
spll_occr_out_lock_int <= wrdata_reg(23 downto 16);
end if;
rddata_reg(15 downto 8) <= regs_i.occr_out_en_i;
rddata_reg(23 downto 16) <= spll_occr_out_lock_int;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -291,6 +296,28 @@ begin
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001001" =>
if (wb_we_i = '1') then
regs_o.rcer_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.rcer_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001010" =>
if (wb_we_i = '1') then
regs_o.ocer_load_o <= '1';
end if;
rddata_reg(7 downto 0) <= regs_i.ocer_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
......@@ -317,10 +344,9 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
when "010000" =>
if (wb_we_i = '1') then
regs_o.dac_main_value_wr_o <= '1';
regs_o.dac_main_dac_sel_wr_o <= '1';
regs_o.dac_hpll_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
......@@ -356,33 +382,10 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
if (wb_we_i = '1') then
spll_deglitch_thr_int <= wrdata_reg(15 downto 0);
end if;
rddata_reg(15 downto 0) <= spll_deglitch_thr_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
when "010001" =>
if (wb_we_i = '1') then
regs_o.dfr_spll_value_wr_o <= '1';
regs_o.dfr_spll_eos_wr_o <= '1';
regs_o.dac_main_value_wr_o <= '1';
regs_o.dac_main_dac_sel_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
......@@ -418,18 +421,11 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
when "010010" =>
if (wb_we_i = '1') then
regs_o.crr_in_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.crr_in_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101" =>
if (wb_we_i = '1') then
regs_o.crr_out_load_o <= '1';
spll_deglitch_thr_int <= wrdata_reg(15 downto 0);
end if;
rddata_reg(15 downto 0) <= regs_i.crr_out_i;
rddata_reg(15 downto 0) <= spll_deglitch_thr_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
......@@ -448,12 +444,10 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
when "010011" =>
if (wb_we_i = '1') then
regs_o.aux_cr_aux_sel_wr_o <= '1';
regs_o.aux_cr_div_ref_wr_o <= '1';
regs_o.aux_cr_div_fb_wr_o <= '1';
regs_o.aux_cr_gate_wr_o <= '1';
regs_o.dfr_spll_value_wr_o <= '1';
regs_o.dfr_spll_eos_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
......@@ -489,7 +483,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
when "011000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
end if;
......@@ -527,7 +521,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001" =>
when "011001" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
end if;
......@@ -565,7 +559,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010" =>
when "011010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= eic_imr_int(0);
......@@ -602,7 +596,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011" =>
when "011011" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
......@@ -640,7 +634,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10100" =>
when "011100" =>
if (wb_we_i = '1') then
end if;
if (spll_dfr_host_rdreq_int_d0 = '0') then
......@@ -650,7 +644,7 @@ begin
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "10101" =>
when "011101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= spll_dfr_host_out_int(47 downto 32);
......@@ -672,7 +666,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10110" =>
when "011110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= spll_dfr_host_full_int;
......@@ -697,7 +691,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10111" =>
when "011111" =>
if (wb_we_i = '1') then
end if;
if (spll_trr_rdreq_int_d0 = '0') then
......@@ -709,7 +703,7 @@ begin
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "11000" =>
when "100000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(17) <= spll_trr_empty_int;
......@@ -762,17 +756,27 @@ begin
-- Number of reference channels (max: 32)
-- Number of output channels (max: 8)
-- Debug queue supported
-- Enable External Clock BB Detector
-- Enable External Clock PLL
regs_o.eccr_ext_en_o <= spll_eccr_ext_en_int;
-- External Clock Input Available
-- Enable PPS/phase alignment
regs_o.eccr_align_en_o <= spll_eccr_align_en_int;
-- PPS/phase alignment done
-- External Clock Reference Present
-- Aligner sample valid/select on channel
regs_o.al_cr_valid_o <= wrdata_reg(8 downto 0);
-- Aligner required on channel
-- Aligner reference counter
-- Aligner reference counter
-- FREQ
-- VALID
regs_o.f_dmtd_valid_o <= wrdata_reg(28);
-- FREQ
-- VALID
regs_o.f_ref_valid_o <= wrdata_reg(28);
-- FREQ
-- VALID
regs_o.f_ext_valid_o <= wrdata_reg(28);
-- Output Channel HW enable flag
-- Output Channel locked flag
regs_o.occr_out_lock_o <= spll_occr_out_lock_int;
-- Output Channel Phase Detector Type
-- Reference Channel Enable
regs_o.rcer_o <= wrdata_reg(31 downto 0);
-- Output Channel Enable
......@@ -794,10 +798,6 @@ begin
-- End-of-Sample
-- pass-through field: End-of-Sample in register: Debug FIFO Register - SPLL side
regs_o.dfr_spll_eos_o <= wrdata_reg(31);
-- Counter Resync
regs_o.crr_in_o <= wrdata_reg(31 downto 0);
-- Counter Resync
regs_o.crr_out_o <= wrdata_reg(15 downto 0);
genblock_0: if (not (g_with_debug_fifo = 0)) generate
-- extra code for reg/fifo/mem: Debug FIFO Register - Host side
spll_dfr_host_in_int(31 downto 0) <= regs_i.dfr_host_value_i;
......@@ -848,18 +848,6 @@ begin
rd_data_o => spll_trr_out_int
);
-- Aux output select
-- pass-through field: Aux output select in register: Aux clock configuration register
regs_o.aux_cr_aux_sel_o <= wrdata_reg(2 downto 0);
-- BB reference divider
-- pass-through field: BB reference divider in register: Aux clock configuration register
regs_o.aux_cr_div_ref_o <= wrdata_reg(8 downto 3);
-- BB feedback divider
-- pass-through field: BB feedback divider in register: Aux clock configuration register
regs_o.aux_cr_div_fb_o <= wrdata_reg(14 downto 9);
-- BB gating frequency select
-- pass-through field: BB gating frequency select in register: Aux clock configuration register
regs_o.aux_cr_gate_o <= wrdata_reg(18 downto 15);
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: Interrupt enable register
......
......@@ -54,17 +54,15 @@ peripheral {
reg {
name = "External Clock Control Register";
prefix = "ECCR";
prefix = "ECCR";
field {
name = "Enable External Clock BB Detector";
field {
name = "Enable External Clock PLL";
prefix = "EXT_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "External Clock Input Available";
description = "1: This instance of wr_softpll_ng supports external 10MHz clock input\
......@@ -75,28 +73,6 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "Enable PPS/phase alignment";
description = "write 1: starts aligning the external and local oscillator clock edges to be in phase\
right after the pulse on SYNC (PPS) input.\
write 0: no effect.";
prefix = "ALIGN_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PPS/phase alignment done";
description = "1: phase alignment triggered by writing to ALIGN_EN done.\
0: phase alignment in progress.";
prefix = "ALIGN_DONE";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "External Clock Reference Present";
description = "1: Reference clock present on the input\
......@@ -106,54 +82,121 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Aligner Control Register";
prefix = "AL_CR";
field {
name = "Aligner sample valid/select on channel";
prefix = "VALID";
type = SLV;
size = 9;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Aligner required on channel";
prefix = "REQUIRED";
type = SLV;
size = 9;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Aligner Counter REF register";
prefix = "AL_CREF";
field {
name = "Aligner reference counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Aligner Counter IN register";
prefix = "AL_CIN";
field {
name = "Aligner reference counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
align = 4;
name = "Output Channel Control Register";
prefix = "OCCR";
name = "DMTD VCO Frequency";
prefix = "F_DMTD";
field {
align = 8;
name = "Output Channel HW enable flag";
prefix = "OUT_EN";
name = "FREQ";
prefix = "FREQ";
type = SLV;
size = 8;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Output Channel locked flag";
prefix = "OUT_LOCK";
type = SLV;
size = 8;
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
field {
name = "Output Channel Phase Detector Type";
description = "Phase detector type used by corresponding output: 0 = DDMTD, 1 = BangBang";
prefix = "OUT_DET_TYPE";
reg {
name = "REF VCO Frequency";
prefix = "F_REF";
field {
name = "FREQ";
prefix = "FREQ";
type = SLV;
size = 8;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Reference Channel Tagging Enable Register";
prefix = "RCER";
name = "EXT VCO Frequency";
prefix = "F_EXT";
field {
name = "Reference Channel Enable";
description = "write 1: enables tag generation on the input channel corresponding to the written bit\
write 0: disables tag generation";
name = "FREQ";
prefix = "FREQ";
type = SLV;
size = 32;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
......@@ -161,21 +204,62 @@ peripheral {
};
reg {
name = "Output Channel Tagging Enable Register";
prefix = "OCER";
align = 4;
name = "Output Channel Control Register";
prefix = "OCCR";
field {
name = "Output Channel Enable";
description = "write 1: enables tag generation on the output channel corresponding to the written bit\
write 0: disables tag generation";
align = 8;
name = "Output Channel HW enable flag";
prefix = "OUT_EN";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Output Channel locked flag";
prefix = "OUT_LOCK";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
access_dev = READ_ONLY;
};
};
reg {
name = "Reference Channel Tagging Enable Register";
prefix = "RCER";
field {
name = "Reference Channel Enable";
description = "write 1: enables tag generation on the input channel corresponding to the written bit\
write 0: disables tag generation";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Output Channel Tagging Enable Register";
prefix = "OCER";
field {
name = "Output Channel Enable";
description = "write 1: enables tag generation on the output channel corresponding to the written bit\
write 0: disables tag generation";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
align = 8;
name = "Helper DAC Output";
......@@ -240,41 +324,8 @@ peripheral {
};
};
reg {
name = "Counter Resync Register - input channels";
prefix = "CRR_IN";
field {
name = "Counter Resync";
description = "write 1: triggers resynchronization of this channel's DDMTD free-running counter with Out Clock 0\
write 0: no effect\
read 1: resync in progress\
read 0: resync done";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Counter Resync Register - output channels";
prefix = "CRR_OUT";
field {
name = "Counter Resync";
description = "write 1: triggers resynchronization of this channel's DDMTD free-running counter with Out Clock 0\
write 0: no effect";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
fifo_reg {
fifo_reg {
name = "Debug FIFO Register - Host side";
prefix = "DFR_HOST";
direction = CORE_TO_BUS;
......@@ -331,43 +382,6 @@ peripheral {
};
};
reg {
name = "Aux clock configuration register";
prefix = "AUX_CR";
field {
name = "Aux output select";
prefix = "AUX_SEL";
size = 3;
type = PASS_THROUGH;
};
field {
name = "BB reference divider";
description = "Reference clock division factor. Applicable only for aux channels with BB phase detector.";
prefix = "DIV_REF";
size = 6;
type = PASS_THROUGH;
};
field {
name = "BB feedback divider";
description = "Reference clock division factor. Applicable only for aux channels with BB phase detector.";
prefix = "DIV_FB";
size = 6;
type = PASS_THROUGH;
};
field {
name = "BB gating frequency select";
description = "BB detector output gating frequency. GATE = log2(period in clk_ref cycles).";
prefix = "GATE";
size = 4;
type = PASS_THROUGH;
};
};
irq {
name = "Got a tag";
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Thu Jul 25 11:14:53 2013
-- Created : Tue Jul 15 17:31:20 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -25,14 +25,20 @@ package spll_wbgen2_pkg is
csr_n_out_i : std_logic_vector(2 downto 0);
csr_dbg_supported_i : std_logic;
eccr_ext_supported_i : std_logic;
eccr_align_done_i : std_logic;
eccr_ext_ref_present_i : std_logic;
al_cr_valid_i : std_logic_vector(8 downto 0);
al_cr_required_i : std_logic_vector(8 downto 0);
al_cref_i : std_logic_vector(31 downto 0);
al_cin_i : std_logic_vector(31 downto 0);
f_dmtd_freq_i : std_logic_vector(27 downto 0);
f_dmtd_valid_i : std_logic;
f_ref_freq_i : std_logic_vector(27 downto 0);
f_ref_valid_i : std_logic;
f_ext_freq_i : std_logic_vector(27 downto 0);
f_ext_valid_i : std_logic;
occr_out_en_i : std_logic_vector(7 downto 0);
occr_out_det_type_i : std_logic_vector(7 downto 0);
rcer_i : std_logic_vector(31 downto 0);
ocer_i : std_logic_vector(7 downto 0);
crr_in_i : std_logic_vector(31 downto 0);
crr_out_i : std_logic_vector(15 downto 0);
dfr_host_wr_req_i : std_logic;
dfr_host_value_i : std_logic_vector(31 downto 0);
dfr_host_seq_id_i : std_logic_vector(15 downto 0);
......@@ -47,14 +53,20 @@ package spll_wbgen2_pkg is
csr_n_out_i => (others => '0'),
csr_dbg_supported_i => '0',
eccr_ext_supported_i => '0',
eccr_align_done_i => '0',
eccr_ext_ref_present_i => '0',
al_cr_valid_i => (others => '0'),
al_cr_required_i => (others => '0'),
al_cref_i => (others => '0'),
al_cin_i => (others => '0'),
f_dmtd_freq_i => (others => '0'),
f_dmtd_valid_i => '0',
f_ref_freq_i => (others => '0'),
f_ref_valid_i => '0',
f_ext_freq_i => (others => '0'),
f_ext_valid_i => '0',
occr_out_en_i => (others => '0'),
occr_out_det_type_i => (others => '0'),
rcer_i => (others => '0'),
ocer_i => (others => '0'),
crr_in_i => (others => '0'),
crr_out_i => (others => '0'),
dfr_host_wr_req_i => '0',
dfr_host_value_i => (others => '0'),
dfr_host_seq_id_i => (others => '0'),
......@@ -68,7 +80,14 @@ package spll_wbgen2_pkg is
type t_spll_out_registers is record
eccr_ext_en_o : std_logic;
eccr_align_en_o : std_logic;
al_cr_valid_o : std_logic_vector(8 downto 0);
al_cr_valid_load_o : std_logic;
f_dmtd_valid_o : std_logic;
f_dmtd_valid_load_o : std_logic;
f_ref_valid_o : std_logic;
f_ref_valid_load_o : std_logic;
f_ext_valid_o : std_logic;
f_ext_valid_load_o : std_logic;
occr_out_lock_o : std_logic_vector(7 downto 0);
rcer_o : std_logic_vector(31 downto 0);
rcer_load_o : std_logic;
......@@ -85,28 +104,23 @@ package spll_wbgen2_pkg is
dfr_spll_value_wr_o : std_logic;
dfr_spll_eos_o : std_logic;
dfr_spll_eos_wr_o : std_logic;
crr_in_o : std_logic_vector(31 downto 0);
crr_in_load_o : std_logic;
crr_out_o : std_logic_vector(15 downto 0);
crr_out_load_o : std_logic;
dfr_host_wr_full_o : std_logic;
dfr_host_wr_empty_o : std_logic;
dfr_host_wr_usedw_o : std_logic_vector(12 downto 0);
trr_wr_full_o : std_logic;
trr_wr_empty_o : std_logic;
aux_cr_aux_sel_o : std_logic_vector(2 downto 0);
aux_cr_aux_sel_wr_o : std_logic;
aux_cr_div_ref_o : std_logic_vector(5 downto 0);
aux_cr_div_ref_wr_o : std_logic;
aux_cr_div_fb_o : std_logic_vector(5 downto 0);
aux_cr_div_fb_wr_o : std_logic;
aux_cr_gate_o : std_logic_vector(3 downto 0);
aux_cr_gate_wr_o : std_logic;
end record;
constant c_spll_out_registers_init_value: t_spll_out_registers := (
eccr_ext_en_o => '0',
eccr_align_en_o => '0',
al_cr_valid_o => (others => '0'),
al_cr_valid_load_o => '0',
f_dmtd_valid_o => '0',
f_dmtd_valid_load_o => '0',
f_ref_valid_o => '0',
f_ref_valid_load_o => '0',
f_ext_valid_o => '0',
f_ext_valid_load_o => '0',
occr_out_lock_o => (others => '0'),
rcer_o => (others => '0'),
rcer_load_o => '0',
......@@ -123,23 +137,11 @@ package spll_wbgen2_pkg is
dfr_spll_value_wr_o => '0',
dfr_spll_eos_o => '0',
dfr_spll_eos_wr_o => '0',
crr_in_o => (others => '0'),
crr_in_load_o => '0',
crr_out_o => (others => '0'),
crr_out_load_o => '0',
dfr_host_wr_full_o => '0',
dfr_host_wr_empty_o => '0',
dfr_host_wr_usedw_o => (others => '0'),
trr_wr_full_o => '0',
trr_wr_empty_o => '0',
aux_cr_aux_sel_o => (others => '0'),
aux_cr_aux_sel_wr_o => '0',
aux_cr_div_ref_o => (others => '0'),
aux_cr_div_ref_wr_o => '0',
aux_cr_div_fb_o => (others => '0'),
aux_cr_div_fb_wr_o => '0',
aux_cr_gate_o => (others => '0'),
aux_cr_gate_wr_o => '0'
trr_wr_empty_o => '0'
);
function "or" (left, right: t_spll_in_registers) return t_spll_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......@@ -149,11 +151,11 @@ end package;
package body spll_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
if x = '1' then
return '1';
else
return x;
end if;
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
......@@ -174,14 +176,20 @@ tmp.csr_n_ref_i := f_x_to_zero(left.csr_n_ref_i) or f_x_to_zero(right.csr_n_ref_
tmp.csr_n_out_i := f_x_to_zero(left.csr_n_out_i) or f_x_to_zero(right.csr_n_out_i);
tmp.csr_dbg_supported_i := f_x_to_zero(left.csr_dbg_supported_i) or f_x_to_zero(right.csr_dbg_supported_i);
tmp.eccr_ext_supported_i := f_x_to_zero(left.eccr_ext_supported_i) or f_x_to_zero(right.eccr_ext_supported_i);
tmp.eccr_align_done_i := f_x_to_zero(left.eccr_align_done_i) or f_x_to_zero(right.eccr_align_done_i);
tmp.eccr_ext_ref_present_i := f_x_to_zero(left.eccr_ext_ref_present_i) or f_x_to_zero(right.eccr_ext_ref_present_i);
tmp.al_cr_valid_i := f_x_to_zero(left.al_cr_valid_i) or f_x_to_zero(right.al_cr_valid_i);
tmp.al_cr_required_i := f_x_to_zero(left.al_cr_required_i) or f_x_to_zero(right.al_cr_required_i);
tmp.al_cref_i := f_x_to_zero(left.al_cref_i) or f_x_to_zero(right.al_cref_i);
tmp.al_cin_i := f_x_to_zero(left.al_cin_i) or f_x_to_zero(right.al_cin_i);
tmp.f_dmtd_freq_i := f_x_to_zero(left.f_dmtd_freq_i) or f_x_to_zero(right.f_dmtd_freq_i);
tmp.f_dmtd_valid_i := f_x_to_zero(left.f_dmtd_valid_i) or f_x_to_zero(right.f_dmtd_valid_i);
tmp.f_ref_freq_i := f_x_to_zero(left.f_ref_freq_i) or f_x_to_zero(right.f_ref_freq_i);
tmp.f_ref_valid_i := f_x_to_zero(left.f_ref_valid_i) or f_x_to_zero(right.f_ref_valid_i);
tmp.f_ext_freq_i := f_x_to_zero(left.f_ext_freq_i) or f_x_to_zero(right.f_ext_freq_i);
tmp.f_ext_valid_i := f_x_to_zero(left.f_ext_valid_i) or f_x_to_zero(right.f_ext_valid_i);
tmp.occr_out_en_i := f_x_to_zero(left.occr_out_en_i) or f_x_to_zero(right.occr_out_en_i);
tmp.occr_out_det_type_i := f_x_to_zero(left.occr_out_det_type_i) or f_x_to_zero(right.occr_out_det_type_i);
tmp.rcer_i := f_x_to_zero(left.rcer_i) or f_x_to_zero(right.rcer_i);
tmp.ocer_i := f_x_to_zero(left.ocer_i) or f_x_to_zero(right.ocer_i);
tmp.crr_in_i := f_x_to_zero(left.crr_in_i) or f_x_to_zero(right.crr_in_i);
tmp.crr_out_i := f_x_to_zero(left.crr_out_i) or f_x_to_zero(right.crr_out_i);
tmp.dfr_host_wr_req_i := f_x_to_zero(left.dfr_host_wr_req_i) or f_x_to_zero(right.dfr_host_wr_req_i);
tmp.dfr_host_value_i := f_x_to_zero(left.dfr_host_value_i) or f_x_to_zero(right.dfr_host_value_i);
tmp.dfr_host_seq_id_i := f_x_to_zero(left.dfr_host_seq_id_i) or f_x_to_zero(right.dfr_host_seq_id_i);
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-29
-- Last update: 2013-07-25
-- Last update: 2014-07-15
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -81,9 +81,9 @@ entity wr_softpll_ng is
-- use with care.
g_divide_input_by_2 : boolean := false;
-- Configuration of all output channels (phase detector type & dividers). See
-- softpll_pkg.vhd for details.
g_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_ref_clock_rate : integer := 125000000;
g_ext_clock_rate : integer := 10000000;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD
......@@ -109,9 +109,13 @@ entity wr_softpll_ng is
-- g_with_ext_clock_input == true
clk_ext_i : in std_logic;
-- External clock, multiplied to 125 MHz using the FPGA's PLL
clk_ext_mul_i : in std_logic;
-- External clock sync/alignment singnal. SoftPLL will align clk_ext_i/clk_fb_i(0)
-- to match the edges immediately following the rising edge in sync_p_i.
sync_p_i : in std_logic;
pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic;
-- DMTD oscillator drive
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
......@@ -130,11 +134,13 @@ entity wr_softpll_ng is
-- When HI, the respective clock output is locked.
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
out_status_o : out std_logic_vector(4*g_num_outputs-1 downto 0);
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
......@@ -157,28 +163,6 @@ architecture rtl of wr_softpll_ng is
constant c_DBG_FIFO_COALESCE : integer := 100;
constant c_BB_ERROR_BITS : integer := 16;
component spll_bangbang_pd
generic (
g_error_bits : integer);
port (
clk_ref_i : in std_logic;
clk_fb_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_refclk_i : in std_logic;
rst_n_fbck_i : in std_logic;
rst_n_sysclk_i : in std_logic;
cfg_div_ref_i : in std_logic_vector(5 downto 0);
cfg_div_fb_i : in std_logic_vector(5 downto 0);
cfg_gating_i : in std_logic_vector(3 downto 0);
sync_p_i : in std_logic;
sync_en_i : in std_logic;
sync_done_o : out std_logic;
err_wrap_o : out std_logic;
err_o : out std_logic_vector(g_error_bits-1 downto 0);
err_stb_o : out std_logic;
ref_present_o : out std_logic);
end component;
component dmtd_with_deglitcher
generic (
g_counter_bits : natural;
......@@ -208,7 +192,7 @@ architecture rtl of wr_softpll_ng is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -223,48 +207,25 @@ architecture rtl of wr_softpll_ng is
regs_o : out t_spll_out_registers);
end component;
procedure f_rr_arbitrate (
signal req : in std_logic_vector;
signal pre_grant : in std_logic_vector;
signal grant : out std_logic_vector)is
variable reqs : std_logic_vector(req'length - 1 downto 0);
variable gnts : std_logic_vector(req'length - 1 downto 0);
variable gnt : std_logic_vector(req'length - 1 downto 0);
variable gntM : std_logic_vector(req'length - 1 downto 0);
variable zeros : std_logic_vector(req'length - 1 downto 0);
begin
zeros := (others => '0');
reqs := req;
-- bit twiddling magic :
gnt := reqs and std_logic_vector(unsigned(not reqs) + 1);
reqs := reqs and not (std_logic_vector(unsigned(pre_grant) - 1) or pre_grant);
gnts := reqs and std_logic_vector(unsigned(not reqs) + 1);
if(reqs = zeros) then
gntM := gnt;
else
gntM := gnts;
end if;
if((req and pre_grant) = zeros) then
grant <= gntM;
end if;
end f_rr_arbitrate;
function f_onehot_decode(x : std_logic_vector) return std_logic_vector is
begin
for j in 0 to x'left loop
if x(j) /= '0' then
return std_logic_vector(to_unsigned(j, 6));
end if;
end loop; -- i
return std_logic_vector(to_unsigned(0, 6));
end f_onehot_decode;
component spll_aligner
generic (
g_counter_width : integer;
g_ref_clock_rate : integer;
g_in_clock_rate : integer;
g_sample_rate : integer);
port (
clk_sys_i : in std_logic;
clk_in_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_sys_i : in std_logic;
pps_ext_a_i : in std_logic;
pps_csync_p1_i : in std_logic;
sample_cref_o : out std_logic_vector(g_counter_width-1 downto 0);
sample_cin_o : out std_logic_vector(g_counter_width-1 downto 0);
sample_pps_o : out std_logic;
sample_valid_o : out std_logic;
sample_ack_i : in std_logic);
end component;
function f_num_total_channels
return integer is
begin
......@@ -309,52 +270,29 @@ architecture rtl of wr_softpll_ng is
return tmp;
end resize;
type t_out_channel_bb_config is record
div_ref : std_logic_vector(5 downto 0);
div_fb : std_logic_vector(5 downto 0);
gating : std_logic_vector(3 downto 0);
end record;
type t_tag_array is array (0 to f_num_total_channels-1) of std_logic_vector(g_tag_bits-1 downto 0);
type t_phase_error_array is array(0 to g_num_outputs-1) of std_logic_vector(c_BB_ERROR_BITS-1 downto 0);
type t_out_channel_bb_config_array is array (0 to g_num_outputs-1) of t_out_channel_bb_config;
signal tags, tags_masked : t_tag_array;
signal tags_grant_p, tags_p, tags_req, tags_grant : std_logic_vector(f_num_total_channels-1 downto 0);
signal tag_muxed : std_logic_vector(g_tag_bits-1 downto 0);
signal tag_src, tag_src_pre : std_logic_vector (5 downto 0);
signal tag_valid, tag_valid_pre : std_logic;
signal rst_n_refclk : std_logic;
signal rst_n_extclk : std_logic;
signal rst_n_rxclk : std_logic_vector(g_num_ref_inputs-1 downto 0);
signal rst_n_fb : std_logic;
signal deglitch_thr_slv : std_logic_vector(15 downto 0);
signal irq_tag : std_logic;
signal dmtd_freq_err : std_logic_vector(11 downto 0);
signal dmtd_freq_err_stb_p : std_logic;
signal bb_phase_err : std_logic_vector(15 downto 0);
signal bb_phase_err_stb_p, bb_phase_err_wrap : std_logic;
signal rcer_int : std_logic_vector(g_num_ref_inputs-1 downto 0);
signal ocer_int : std_logic_vector(g_num_outputs-1 downto 0);
signal clk_ref_buf : std_logic;
signal clk_rx_buf : std_logic;
signal wb_irq_out : std_logic;
signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
signal regs_in : t_SPLL_out_registers;
signal regs_out : t_SPLL_in_registers;
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
signal regs_in : t_SPLL_out_registers;
signal regs_out : t_SPLL_in_registers;
-- Debug FIFO signals
signal dbg_fifo_almostfull : std_logic;
......@@ -363,33 +301,24 @@ architecture rtl of wr_softpll_ng is
-- Temporary vectors for DDMTD clock selection (straight/reversed)
signal dmtd_ref_clk_in, dmtd_ref_clk_dmtd : std_logic_vector(g_num_ref_inputs-1 downto 0);
signal rst_n_dmtd_ref_clk : std_logic_vector(g_num_ref_inputs-1 downto 0);
signal dmtd_fb_clk_in, dmtd_fb_clk_dmtd : std_logic_vector(g_num_outputs-1 downto 0);
signal rst_n_dmtd_fb_clk : std_logic_vector(g_num_outputs-1 downto 0);
signal rst_n_dmtd_ref_clk : std_logic_vector(g_num_ref_inputs-1 downto 0);
signal bb_sync_en, bb_sync_done : std_logic;
signal ext_ref_present : std_logic;
signal fb_resync_out : std_logic_vector(g_num_outputs-1 downto 0);
signal dmtd_fb_clk_in, dmtd_fb_clk_dmtd : std_logic_vector(g_num_outputs-1 downto 0);
signal rst_n_dmtd_fb_clk : std_logic_vector(g_num_outputs-1 downto 0);
signal ext_ref_present : std_logic;
signal fb_resync_out : std_logic_vector(g_num_outputs-1 downto 0);
signal ref_resync_start_p : std_logic_vector(31 downto 0);
signal fb_resync_start_p : std_logic_vector(15 downto 0);
signal rst_n_bb_ref : std_logic_vector(g_num_outputs-1 downto 0);
signal rst_n_bb_fb : std_logic_vector(g_num_outputs-1 downto 0);
type t_aligner_sample_array is array(0 to g_num_outputs) of std_logic_vector(27 downto 0);
signal bb_chx_phase_err : t_phase_error_array;
signal bb_chx_phase_err_wrap, bb_chx_phase_err_stb_p : std_logic_vector(g_num_outputs-1 downto 0);
signal bb_config : t_out_channel_bb_config_array;
signal bb_det_reset : std_logic_vector(g_num_outputs-1 downto 0);
signal aligner_sample_valid, aligner_sample_ack : std_logic_vector(g_num_outputs downto 0);
signal aligner_sample_cref, aligner_sample_cin : t_aligner_sample_array;
begin -- rtl
resized_addr(6 downto 0) <= wb_adr_i;
resized_addr(c_wishbone_address_width-1 downto 7) <= (others => '0');
U_Adapter : wb_slave_adapter
generic map(
g_master_use_struct => true,
......@@ -403,7 +332,7 @@ begin -- rtl
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
sl_adr_i => resized_addr,
sl_adr_i => wb_adr_i,
sl_dat_i => wb_dat_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
......@@ -413,6 +342,46 @@ begin -- rtl
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o);
U_Meas_DMTD_Freq: gc_frequency_meter
generic map (
g_with_internal_timebase => false,
g_clk_sys_freq => 1,
g_counter_bits => 28)
port map (
clk_sys_i => clk_sys_i,
clk_in_i => clk_dmtd_i,
rst_n_i => rst_n_i,
pps_p1_i => pps_ext_a_i,
freq_o => regs_out.f_dmtd_freq_i,
freq_valid_o => open); -- fixme
U_Meas_REF_Freq: gc_frequency_meter
generic map (
g_with_internal_timebase => false,
g_clk_sys_freq => 1,
g_counter_bits => 28)
port map (
clk_sys_i => clk_sys_i,
clk_in_i => clk_fb_i(0),
rst_n_i => rst_n_i,
pps_p1_i => pps_ext_a_i,
freq_o => regs_out.f_ref_freq_i,
freq_valid_o => open); -- fixme
U_Meas_EXT_Freq: gc_frequency_meter
generic map (
g_with_internal_timebase => false,
g_clk_sys_freq => 1,
g_counter_bits => 28)
port map (
clk_sys_i => clk_sys_i,
clk_in_i => clk_ext_i,
rst_n_i => rst_n_i,
pps_p1_i => pps_ext_a_i,
freq_o => regs_out.f_ext_freq_i,
freq_valid_o => open); -- fixme
gen_ref_dmtds : for i in 0 to g_num_ref_inputs-1 generate
dmtd_ref_clk_in(i) <= f_pick(g_reverse_dmtds, clk_dmtd_i, clk_ref_i(i));
......@@ -441,8 +410,8 @@ begin -- rtl
clk_sys_i => clk_sys_i,
clk_in_i => dmtd_ref_clk_in(i),
resync_done_o => regs_out.crr_in_i(i),
resync_start_p_i => ref_resync_start_p(i),
resync_done_o => open,
resync_start_p_i => '0',
resync_p_a_i => fb_resync_out(0),
resync_p_o => open,
......@@ -457,199 +426,137 @@ begin -- rtl
end generate gen_ref_dmtds;
gen_feedback_dmtds : for i in 0 to g_num_outputs-1 generate
gen_output_pd_ddmtd : if(g_channels_config(i) = CH_DDMTD or i = 0) generate
dmtd_fb_clk_in(i) <= f_pick(g_reverse_dmtds, clk_dmtd_i, clk_fb_i(i));
dmtd_fb_clk_dmtd(i) <= f_pick(g_reverse_dmtds, clk_fb_i(i), clk_dmtd_i);
U_sync_rst_dmtd_fb : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => dmtd_fb_clk_dmtd(i),
rst_n_i => '1',
data_i => rst_n_i,
synced_o => rst_n_dmtd_fb_clk(i));
DMTD_FB : dmtd_with_deglitcher
generic map (
g_counter_bits => g_tag_bits,
g_divide_input_by_2 => g_divide_input_by_2)
port map (
rst_n_dmtdclk_i => rst_n_dmtd_fb_clk(i),
rst_n_sysclk_i => rst_n_i,
clk_dmtd_i => dmtd_fb_clk_dmtd(i),
clk_dmtd_en_i => '1',
clk_sys_i => clk_sys_i,
clk_in_i => dmtd_fb_clk_in(i),
resync_done_o => regs_out.crr_out_i(i),
resync_start_p_i => fb_resync_start_p(i),
resync_p_a_i => fb_resync_out(0),
resync_p_o => fb_resync_out(i),
tag_o => tags(i+g_num_ref_inputs),
tag_stb_p1_o => tags_p(i+g_num_ref_inputs),
shift_en_i => '0',
shift_dir_i => '0',
deglitch_threshold_i => deglitch_thr_slv,
dbg_dmtdout_o => open);
regs_out.occr_out_det_type_i(i) <= '0';
end generate gen_output_pd_ddmtd;
gen_output_pd_bb : if (g_channels_config(i) = CH_BANGBANG and i /= 0) generate
p_dividers_config : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(regs_in.aux_cr_aux_sel_o = std_logic_vector(to_unsigned(i, 3)) and regs_in.aux_cr_aux_sel_wr_o = '1') then
bb_config(i).div_ref <= regs_in.aux_cr_div_ref_o;
bb_config(i).div_fb <= regs_in.aux_cr_div_fb_o;
bb_config(i).gating <= regs_in.aux_cr_gate_o;
end if;
end if;
end process;
bb_det_reset(i) <= rst_n_i and ocer_int(i);
U_sync_rst_ref : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_fb_i(0), --ref_i(g_channels_config(i).ref_input),
rst_n_i => '1',
data_i => bb_det_reset(i),
synced_o => rst_n_bb_ref(i));
U_sync_rst_fb : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_fb_i(i),
rst_n_i => '1',
data_i => bb_det_reset(i),
synced_o => rst_n_bb_fb(i));
U_BB_Detect : spll_bangbang_pd
generic map (
g_error_bits => c_BB_ERROR_BITS)
port map (
-- note: bb detectors can be referenced only to the local 125 MHz oscillator
clk_ref_i => clk_fb_i(0),
clk_fb_i => clk_fb_i(i),
clk_sys_i => clk_sys_i,
rst_n_refclk_i => rst_n_bb_ref(i),
rst_n_fbck_i => rst_n_bb_fb(i),
rst_n_sysclk_i => rst_n_i,
cfg_div_ref_i => bb_config(i).div_ref,
cfg_div_fb_i => bb_config(i).div_fb,
cfg_gating_i => bb_config(i).gating,
sync_p_i => sync_p_i,
sync_en_i => '1',
sync_done_o => open,
err_o => bb_chx_phase_err(i),
err_wrap_o => bb_chx_phase_err_wrap(i),
err_stb_o => bb_chx_phase_err_stb_p(i),
ref_present_o => open);
tags(i+g_num_ref_inputs)(c_BB_ERROR_BITS downto 0) <= bb_chx_phase_err_wrap(i) & bb_chx_phase_err(i);
tags_p(i+g_num_ref_inputs) <= bb_chx_phase_err_stb_p(i);
regs_out.occr_out_det_type_i(i) <= '1';
end generate gen_output_pd_bb;
end generate gen_feedback_dmtds;
gen_with_ext_clock_input : if(g_with_ext_clock_input) generate
U_sync_rst_ext : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_ext_i,
rst_n_i => '1',
data_i => rst_n_i,
synced_o => rst_n_extclk);
dmtd_fb_clk_in(i) <= f_pick(g_reverse_dmtds, clk_dmtd_i, clk_fb_i(i));
dmtd_fb_clk_dmtd(i) <= f_pick(g_reverse_dmtds, clk_fb_i(i), clk_dmtd_i);
U_sync_rst_fb0 : gc_sync_ffs
U_sync_rst_dmtd_fb : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_fb_i(0),
clk_i => dmtd_fb_clk_dmtd(i),
rst_n_i => '1',
data_i => rst_n_i,
synced_o => rst_n_fb);
synced_o => rst_n_dmtd_fb_clk(i));
U_sync_ffs_sync_en : gc_sync_ffs
DMTD_FB : dmtd_with_deglitcher
generic map (
g_sync_edge => "positive")
g_counter_bits => g_tag_bits,
g_divide_input_by_2 => g_divide_input_by_2)
port map (
clk_i => clk_ext_i,
rst_n_i => rst_n_i,
data_i => regs_in.eccr_align_en_o,
synced_o => bb_sync_en);
rst_n_dmtdclk_i => rst_n_dmtd_fb_clk(i),
rst_n_sysclk_i => rst_n_i,
clk_dmtd_i => dmtd_fb_clk_dmtd(i),
clk_dmtd_en_i => '1',
clk_sys_i => clk_sys_i,
clk_in_i => dmtd_fb_clk_in(i),
resync_done_o => open,
resync_start_p_i => '0',
resync_p_a_i => fb_resync_out(0),
resync_p_o => fb_resync_out(i),
tag_o => tags(i+g_num_ref_inputs),
tag_stb_p1_o => tags_p(i+g_num_ref_inputs),
shift_en_i => '0',
shift_dir_i => '0',
U_sync_ffs_sync_done : gc_sync_ffs
deglitch_threshold_i => deglitch_thr_slv,
dbg_dmtdout_o => open);
end generate gen_feedback_dmtds;
gen_with_ext_clock_input : if(g_with_ext_clock_input) generate
U_DMTD_EXT : dmtd_with_deglitcher
generic map (
g_sync_edge => "positive")
g_counter_bits => g_tag_bits,
g_divide_input_by_2 => g_divide_input_by_2)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
data_i => bb_sync_done,
synced_o => regs_out.eccr_align_done_i);
rst_n_dmtdclk_i => rst_n_i, -- FIXME!
rst_n_sysclk_i => rst_n_i,
clk_dmtd_i => clk_dmtd_i,
clk_dmtd_en_i => '1',
U_Ext_BB_Detect : spll_bangbang_pd
clk_sys_i => clk_sys_i,
clk_in_i => clk_ext_mul_i,
resync_done_o => open,
resync_start_p_i => '0',
resync_p_a_i => fb_resync_out(0),
resync_p_o => open,
tag_o => tags(g_num_ref_inputs + g_num_outputs),
tag_stb_p1_o => tags_p(g_num_ref_inputs + g_num_outputs),
shift_en_i => '0',
shift_dir_i => '0',
deglitch_threshold_i => deglitch_thr_slv,
dbg_dmtdout_o => open);
U_Aligner_EXT : spll_aligner
generic map (
g_error_bits => c_BB_ERROR_BITS)
g_counter_width => 28,
g_ref_clock_rate => g_ref_clock_rate,
g_in_clock_rate => g_ext_clock_rate,
g_sample_rate => 100)
port map (
clk_ref_i => clk_ext_i,
clk_fb_i => clk_fb_i(0),
clk_sys_i => clk_sys_i,
rst_n_refclk_i => rst_n_i,
rst_n_fbck_i => rst_n_fb,
rst_n_sysclk_i => rst_n_i,
cfg_div_ref_i => std_logic_vector(to_unsigned(c_softpll_ext_div_ref, 6)),
cfg_div_fb_i => std_logic_vector(to_unsigned(c_softpll_ext_div_fb, 6)),
cfg_gating_i => std_logic_vector(to_unsigned(c_softpll_ext_log2_gating, 4)),
sync_p_i => sync_p_i,
sync_en_i => bb_sync_en,
sync_done_o => bb_sync_done,
err_o => bb_phase_err,
err_wrap_o => bb_phase_err_wrap,
err_stb_o => bb_phase_err_stb_p,
ref_present_o => ext_ref_present);
tags(g_num_ref_inputs + g_num_outputs)(c_BB_ERROR_BITS-1 downto 0) <= bb_phase_err(c_BB_ERROR_BITS-1 downto 0);
tags(g_num_ref_inputs + g_num_outputs)(c_BB_ERROR_BITS) <= bb_phase_err_wrap;
clk_in_i => clk_ext_i,
clk_ref_i => clk_fb_i(0),
rst_n_sys_i => rst_n_i,
pps_ext_a_i => pps_ext_a_i,
pps_csync_p1_i => pps_csync_p1_i,
sample_cref_o => aligner_sample_cref(g_num_outputs),
sample_cin_o => aligner_sample_cin(g_num_outputs),
sample_valid_o => aligner_sample_valid(g_num_outputs),
sample_ack_i => aligner_sample_ack(g_num_outputs)
);
regs_out.eccr_ext_supported_i <= '1';
regs_out.eccr_ext_ref_present_i <= ext_ref_present;
regs_out.eccr_ext_ref_present_i <= '1';
end generate gen_with_ext_clock_input;
aligner_sample_valid(g_num_outputs-1 downto 0) <= (others => '0');
gen_without_ext_clock_input : if(not g_with_ext_clock_input) generate
regs_out.eccr_ext_supported_i <= '0';
bb_phase_err_stb_p <= '0';
tags_p(g_num_ref_inputs + g_num_outputs) <= '0';
regs_out.eccr_ext_supported_i <= '0';
end generate gen_without_ext_clock_input;
p_ack_aligner_samples: process(regs_in, aligner_sample_valid)
begin
for i in 0 to g_num_outputs loop
aligner_sample_ack(i) <= regs_in.al_cr_valid_o(i) and regs_in.al_cr_valid_load_o;
regs_out.al_cr_valid_i(i) <= aligner_sample_valid(i);
end loop; -- i in 0 to g_num_outputs
end process;
p_mux_aligner_samples: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
for i in 0 to g_num_outputs loop
if(aligner_sample_ack(i) = '1') then
regs_out.al_cref_i <= resize( aligner_sample_cref(i), 32 );
regs_out.al_cin_i <= resize( aligner_sample_cin(i), 32 );
end if;
end loop;
end if;
end process;
U_WB_SLAVE : spll_wb_slave
generic map (
g_with_debug_fifo => f_pick(g_with_debug_fifo, 1, 0))
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
wb_adr_i => wb_in.adr(4 downto 0),
wb_adr_i => wb_in.adr(5 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
......@@ -665,17 +572,6 @@ begin -- rtl
irq_tag_i => irq_tag);
-- Counter resync logic
process(regs_in)
begin
for i in 0 to g_num_outputs-1 loop
fb_resync_start_p(i) <= regs_in.crr_out_load_o and regs_in.crr_out_o(i);
end loop;
for i in 0 to g_num_ref_inputs-1 loop
ref_resync_start_p(i) <= regs_in.crr_in_load_o and regs_in.crr_in_o(i);
end loop; -- i
end process;
p_ocer_rcer_regs : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
......@@ -723,7 +619,7 @@ begin -- rtl
end if;
end loop; -- i
if(bb_phase_err_stb_p = '1') then
if(tags_p(f_num_total_channels-1) = '1') then
tags_req(f_num_total_channels-1) <= regs_in.eccr_ext_en_o;
elsif(tags_grant(f_num_total_channels-1) = '1') then
tags_req(f_num_total_channels-1) <= '0';
......@@ -764,7 +660,7 @@ begin -- rtl
tag_valid <= tag_valid_pre;
tag_src_pre <= f_onehot_decode(tags_grant_p);
tag_src_pre <= f_onehot_decode(tags_grant_p, tag_src_pre'length);
tag_src <= tag_src_pre;
muxed := (others => '0');
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-29
-- Last update: 2013-07-25
-- Last update: 2014-07-15
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -74,10 +74,9 @@ entity xwr_softpll_ng is
-- Divides the DDMTD clock inputs by 2, removing the "CLOCK_DEDICATED_ROUTE"
-- errors under ISE tools, at the cost of bandwidth reduction. Use with care.
g_divide_input_by_2 : boolean := false;
-- Configuration of all output channels (phase detector type & dividers). See
-- softpll_pkg.vhd for details.
g_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_ref_clock_rate : integer := 125000000;
g_ext_clock_rate : integer := 10000000;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE
......@@ -99,9 +98,14 @@ entity xwr_softpll_ng is
-- g_with_ext_clock_input == true
clk_ext_i : in std_logic;
-- External clock, multiplied to 125 MHz using the FPGA's PLL
clk_ext_mul_i : in std_logic;
-- External clock sync/alignment singnal. SoftPLL will clk_ext_i/clk_fb_i(0)
-- to match the edges immediately following the rising edge in sync_p_i.
sync_p_i : in std_logic;
pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic;
-- DMTD oscillator drive
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
......@@ -115,6 +119,7 @@ entity xwr_softpll_ng is
out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
out_status_o : out std_logic_vector(4*g_num_outputs-1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
......@@ -126,7 +131,6 @@ entity xwr_softpll_ng is
end xwr_softpll_ng;
architecture wrapper of xwr_softpll_ng is
component wr_softpll_ng
generic (
g_tag_bits : integer;
......@@ -136,7 +140,8 @@ architecture wrapper of xwr_softpll_ng is
g_with_ext_clock_input : boolean;
g_reverse_dmtds : boolean;
g_divide_input_by_2 : boolean;
g_channels_config : t_softpll_channel_config_array;
g_ref_clock_rate : integer;
g_ext_clock_rate : integer;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
port (
......@@ -146,7 +151,9 @@ architecture wrapper of xwr_softpll_ng is
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic;
sync_p_i : in std_logic;
clk_ext_mul_i : in std_logic;
pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic;
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
dac_dmtd_load_o : out std_logic;
dac_out_data_o : out std_logic_vector(15 downto 0);
......@@ -154,11 +161,13 @@ architecture wrapper of xwr_softpll_ng is
dac_out_load_o : out std_logic;
out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
out_status_o : out std_logic_vector(4*g_num_outputs-1 downto 0);
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
......@@ -181,7 +190,8 @@ begin -- behavioral
g_with_ext_clock_input => g_with_ext_clock_input,
g_reverse_dmtds => g_reverse_dmtds,
g_divide_input_by_2 => g_divide_input_by_2,
g_channels_config => g_channels_config
g_ref_clock_rate => g_ref_clock_rate,
g_ext_clock_rate => g_ext_clock_rate
)
port map (
clk_sys_i => clk_sys_i,
......@@ -190,7 +200,9 @@ begin -- behavioral
clk_fb_i => clk_fb_i,
clk_dmtd_i => clk_dmtd_i,
clk_ext_i => clk_ext_i,
sync_p_i => sync_p_i,
clk_ext_mul_i => clk_ext_mul_i,
pps_csync_p1_i => pps_csync_p1_i,
pps_ext_a_i => pps_ext_a_i,
dac_dmtd_data_o => dac_dmtd_data_o,
dac_dmtd_load_o => dac_dmtd_load_o,
dac_out_data_o => dac_out_data_o,
......@@ -198,7 +210,7 @@ begin -- behavioral
dac_out_load_o => dac_out_load_o,
out_enable_i => out_enable_i,
out_locked_o => out_locked_o,
wb_adr_i => slave_i.adr(6 downto 0),
wb_adr_i => slave_i.adr,
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
......
......@@ -5,7 +5,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2013-03-20
-- Last update: 2014-07-15
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -114,6 +114,8 @@ entity wr_core is
-- Aux clocks (i.e. the FMC clock), which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_ext_mul_i : in std_logic := '0';
-- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
clk_ext_i : in std_logic := '0';
......@@ -509,7 +511,8 @@ begin
g_address_granularity => BYTE,
g_num_ref_inputs => 1,
g_num_outputs => 1 + g_aux_clks,
g_channels_config => g_softpll_channels_config)
g_ref_clock_rate => 125000000,
g_ext_clock_rate => 10000000)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_net_n,
......@@ -521,8 +524,11 @@ begin
-- DMTD Offset clock
clk_dmtd_i => clk_dmtd_i,
clk_ext_i => clk_ext_i,
sync_p_i => pps_ext_i,
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
pps_csync_p1_i => s_pps_csync,
pps_ext_a_i => pps_ext_i,
-- DMTD oscillator drive
dac_dmtd_data_o => dac_hpll_data_o,
......
......@@ -243,18 +243,20 @@ package wrcore_pkg is
version => x"00000002",
date => x"20120305",
name => "WR-Soft-PLL ")));
component xwr_softpll_ng
generic (
g_tag_bits : integer;
g_num_ref_inputs : integer;
g_num_outputs : integer;
g_with_debug_fifo : boolean := false;
g_with_ext_clock_input : boolean := false;
g_reverse_dmtds : boolean := false;
g_divide_input_by_2 : boolean := false;
g_with_debug_fifo : boolean;
g_with_ext_clock_input : boolean;
g_reverse_dmtds : boolean;
g_divide_input_by_2 : boolean;
g_ref_clock_rate : integer;
g_ext_clock_rate : integer;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config);
g_address_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -262,7 +264,9 @@ package wrcore_pkg is
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic;
sync_p_i : in std_logic;
clk_ext_mul_i : in std_logic;
pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic;
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
dac_dmtd_load_o : out std_logic;
dac_out_data_o : out std_logic_vector(15 downto 0);
......@@ -270,12 +274,13 @@ package wrcore_pkg is
dac_out_load_o : out std_logic;
out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
out_status_o : out std_logic_vector(4*g_num_outputs-1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
debug_o : out std_logic_vector(3 downto 0);
dbg_fifo_irq_o : out std_logic);
end component;
constant cc_unused_master_in : t_wishbone_master_in :=
('1', '0', '0', '0', '0', cc_dummy_data);
......@@ -296,7 +301,6 @@ package wrcore_pkg is
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024
);
......@@ -305,6 +309,7 @@ package wrcore_pkg is
clk_dmtd_i : in std_logic := '0';
clk_ref_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_ext_mul_i: in std_logic := '0';
clk_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
rst_n_i : in std_logic;
......@@ -396,7 +401,6 @@ package wrcore_pkg is
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024
);
......@@ -420,6 +424,8 @@ package wrcore_pkg is
-- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
clk_ext_i : in std_logic := '0';
clk_ext_mul_i : in std_logic;
-- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
pps_ext_i : in std_logic := '0';
......
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2013-02-08
-- Last update: 2014-07-15
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -78,7 +78,6 @@ entity xwr_core is
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024
);
......@@ -102,6 +101,8 @@ entity xwr_core is
-- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
clk_ext_i : in std_logic := '0';
clk_ext_mul_i : in std_logic := '0';
-- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
pps_ext_i : in std_logic := '0';
......@@ -229,17 +230,17 @@ begin
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_aux_sdb => g_aux_sdb,
g_softpll_channels_config => g_softpll_channels_config,
g_softpll_enable_debugger => g_softpll_enable_debugger,
g_vuart_fifo_size => g_vuart_fifo_size)
port map(
clk_sys_i => clk_sys_i,
clk_dmtd_i => clk_dmtd_i,
clk_ref_i => clk_ref_i,
clk_aux_i => clk_aux_i,
clk_ext_i => clk_ext_i,
pps_ext_i => pps_ext_i,
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
clk_dmtd_i => clk_dmtd_i,
clk_ref_i => clk_ref_i,
clk_aux_i => clk_aux_i,
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
pps_ext_i => pps_ext_i,
rst_n_i => rst_n_i,
dac_hpll_load_p1_o => dac_hpll_load_p1_o,
dac_hpll_data_o => dac_hpll_data_o,
......
files = [ "wr_xilinx_pkg.vhd" ]
files = [ "wr_xilinx_pkg.vhd", "ext_pll_10_to_125m.vhd" ]
modules = {"local" : ["wr_gtp_phy"]}
\ No newline at end of file
-- file: ext_pll_10_to_125m.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___125.000______0.000______50.0_____1014.602____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________10.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity ext_pll_10_to_125m is
port
(-- Clock in ports
clk_ext_i : in std_logic;
-- Clock out ports
clk_ext_mul_o : out std_logic;
-- Status and control signals
rst_a_i : in std_logic
);
end ext_pll_10_to_125m;
architecture xilinx of ext_pll_10_to_125m is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "ext_pll_10_to_125m,clk_wiz_v3_6,{component_name=ext_pll_10_to_125m,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=100.0,clkin2_period=100.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 100.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clk_ext_i,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => rst_a_i,
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
clkout1_buf : BUFG
port map
(O => clk_ext_mul_o,
I => clkfx);
end xilinx;
......@@ -406,7 +406,7 @@ endclass // CIWBMasterAccessor
if(request_queue.size() > 0)
begin
wb_cycle_t c;
wb_cycle_result_t res;
......@@ -416,6 +416,7 @@ endclass // CIWBMasterAccessor
case(c.ctype)
PIPELINED:
begin
pipelined_cycle(c.data, c.rw, c.data.size(), res);
c.result =res;
end
......
`define ADDR_SPLL_CSR 7'h0
`define SPLL_CSR_PER_SEL_OFFSET 0
`define SPLL_CSR_PER_SEL 32'h0000003f
`define SPLL_CSR_N_REF_OFFSET 8
`define SPLL_CSR_N_REF 32'h00003f00
`define SPLL_CSR_N_OUT_OFFSET 16
`define SPLL_CSR_N_OUT 32'h00070000
`define SPLL_CSR_PER_EN_OFFSET 19
`define SPLL_CSR_PER_EN 32'h00080000
`define ADDR_SPLL_ECCR 7'h4
`define ADDR_SPLL_CSR 8'h0
`define SPLL_CSR_UNUSED0_OFFSET 8
`define SPLL_CSR_UNUSED0 32'h00003f00
`define SPLL_CSR_N_REF_OFFSET 16
`define SPLL_CSR_N_REF 32'h003f0000
`define SPLL_CSR_N_OUT_OFFSET 24
`define SPLL_CSR_N_OUT 32'h07000000
`define SPLL_CSR_DBG_SUPPORTED_OFFSET 27
`define SPLL_CSR_DBG_SUPPORTED 32'h08000000
`define ADDR_SPLL_ECCR 8'h4
`define SPLL_ECCR_EXT_EN_OFFSET 0
`define SPLL_ECCR_EXT_EN 32'h00000001
`define SPLL_ECCR_EXT_SUPPORTED_OFFSET 1
`define SPLL_ECCR_EXT_SUPPORTED 32'h00000002
`define SPLL_ECCR_ALIGN_EN_OFFSET 2
`define SPLL_ECCR_ALIGN_EN 32'h00000004
`define SPLL_ECCR_ALIGN_DONE_OFFSET 3
`define SPLL_ECCR_ALIGN_DONE 32'h00000008
`define SPLL_ECCR_EXT_REF_PRESENT_OFFSET 4
`define SPLL_ECCR_EXT_REF_PRESENT 32'h00000010
`define ADDR_SPLL_DCCR 7'h8
`define SPLL_DCCR_GATE_DIV_OFFSET 0
`define SPLL_DCCR_GATE_DIV 32'h0000003f
`define ADDR_SPLL_RCGER 7'hc
`define SPLL_RCGER_GATE_SEL_OFFSET 0
`define SPLL_RCGER_GATE_SEL 32'hffffffff
`define ADDR_SPLL_OCCR 7'h10
`define SPLL_OCCR_OUT_EN_OFFSET 0
`define SPLL_OCCR_OUT_EN 32'h000000ff
`define SPLL_OCCR_OUT_LOCK_OFFSET 8
`define SPLL_OCCR_OUT_LOCK 32'h0000ff00
`define ADDR_SPLL_RCER 7'h14
`define ADDR_SPLL_OCER 7'h18
`define ADDR_SPLL_PER_HPLL 7'h1c
`define SPLL_PER_HPLL_ERROR_OFFSET 0
`define SPLL_PER_HPLL_ERROR 32'h0000ffff
`define SPLL_PER_HPLL_VALID_OFFSET 16
`define SPLL_PER_HPLL_VALID 32'h00010000
`define ADDR_SPLL_DAC_HPLL 7'h20
`define ADDR_SPLL_DAC_MAIN 7'h24
`define SPLL_ECCR_EXT_REF_PRESENT_OFFSET 2
`define SPLL_ECCR_EXT_REF_PRESENT 32'h00000004
`define ADDR_SPLL_AL_CR 8'h8
`define SPLL_AL_CR_VALID_OFFSET 0
`define SPLL_AL_CR_VALID 32'h000001ff
`define SPLL_AL_CR_REQUIRED_OFFSET 9
`define SPLL_AL_CR_REQUIRED 32'h0003fe00
`define ADDR_SPLL_AL_CREF 8'hc
`define ADDR_SPLL_AL_CIN 8'h10
`define ADDR_SPLL_F_DMTD 8'h14
`define SPLL_F_DMTD_FREQ_OFFSET 0
`define SPLL_F_DMTD_FREQ 32'h0fffffff
`define SPLL_F_DMTD_VALID_OFFSET 28
`define SPLL_F_DMTD_VALID 32'h10000000
`define ADDR_SPLL_F_REF 8'h18
`define SPLL_F_REF_FREQ_OFFSET 0
`define SPLL_F_REF_FREQ 32'h0fffffff
`define SPLL_F_REF_VALID_OFFSET 28
`define SPLL_F_REF_VALID 32'h10000000
`define ADDR_SPLL_F_EXT 8'h1c
`define SPLL_F_EXT_FREQ_OFFSET 0
`define SPLL_F_EXT_FREQ 32'h0fffffff
`define SPLL_F_EXT_VALID_OFFSET 28
`define SPLL_F_EXT_VALID 32'h10000000
`define ADDR_SPLL_OCCR 8'h20
`define SPLL_OCCR_OUT_EN_OFFSET 8
`define SPLL_OCCR_OUT_EN 32'h0000ff00
`define SPLL_OCCR_OUT_LOCK_OFFSET 16
`define SPLL_OCCR_OUT_LOCK 32'h00ff0000
`define ADDR_SPLL_RCER 8'h24
`define ADDR_SPLL_OCER 8'h28
`define ADDR_SPLL_DAC_HPLL 8'h40
`define ADDR_SPLL_DAC_MAIN 8'h44
`define SPLL_DAC_MAIN_VALUE_OFFSET 0
`define SPLL_DAC_MAIN_VALUE 32'h0000ffff
`define SPLL_DAC_MAIN_DAC_SEL_OFFSET 16
`define SPLL_DAC_MAIN_DAC_SEL 32'h000f0000
`define ADDR_SPLL_DEGLITCH_THR 7'h28
`define ADDR_SPLL_DFR_SPLL 7'h2c
`define ADDR_SPLL_DEGLITCH_THR 8'h48
`define ADDR_SPLL_DFR_SPLL 8'h4c
`define SPLL_DFR_SPLL_VALUE_OFFSET 0
`define SPLL_DFR_SPLL_VALUE 32'h7fffffff
`define SPLL_DFR_SPLL_EOS_OFFSET 31
`define SPLL_DFR_SPLL_EOS 32'h80000000
`define ADDR_SPLL_CRR_IN 7'h30
`define ADDR_SPLL_CRR_OUT 7'h34
`define ADDR_SPLL_EIC_IDR 7'h40
`define ADDR_SPLL_EIC_IDR 8'h60
`define SPLL_EIC_IDR_TAG_OFFSET 0
`define SPLL_EIC_IDR_TAG 32'h00000001
`define ADDR_SPLL_EIC_IER 7'h44
`define ADDR_SPLL_EIC_IER 8'h64
`define SPLL_EIC_IER_TAG_OFFSET 0
`define SPLL_EIC_IER_TAG 32'h00000001
`define ADDR_SPLL_EIC_IMR 7'h48
`define ADDR_SPLL_EIC_IMR 8'h68
`define SPLL_EIC_IMR_TAG_OFFSET 0
`define SPLL_EIC_IMR_TAG 32'h00000001
`define ADDR_SPLL_EIC_ISR 7'h4c
`define ADDR_SPLL_EIC_ISR 8'h6c
`define SPLL_EIC_ISR_TAG_OFFSET 0
`define SPLL_EIC_ISR_TAG 32'h00000001
`define ADDR_SPLL_DFR_HOST_R0 7'h50
`define ADDR_SPLL_DFR_HOST_R0 8'h70
`define SPLL_DFR_HOST_R0_VALUE_OFFSET 0
`define SPLL_DFR_HOST_R0_VALUE 32'hffffffff
`define ADDR_SPLL_DFR_HOST_R1 7'h54
`define ADDR_SPLL_DFR_HOST_R1 8'h74
`define SPLL_DFR_HOST_R1_SEQ_ID_OFFSET 0
`define SPLL_DFR_HOST_R1_SEQ_ID 32'h0000ffff
`define ADDR_SPLL_DFR_HOST_CSR 7'h58
`define ADDR_SPLL_DFR_HOST_CSR 8'h78
`define SPLL_DFR_HOST_CSR_FULL_OFFSET 16
`define SPLL_DFR_HOST_CSR_FULL 32'h00010000
`define SPLL_DFR_HOST_CSR_EMPTY_OFFSET 17
`define SPLL_DFR_HOST_CSR_EMPTY 32'h00020000
`define SPLL_DFR_HOST_CSR_USEDW_OFFSET 0
`define SPLL_DFR_HOST_CSR_USEDW 32'h00001fff
`define ADDR_SPLL_TRR_R0 7'h5c
`define ADDR_SPLL_TRR_R0 8'h7c
`define SPLL_TRR_R0_VALUE_OFFSET 0
`define SPLL_TRR_R0_VALUE 32'h00ffffff
`define SPLL_TRR_R0_CHAN_ID_OFFSET 24
`define SPLL_TRR_R0_CHAN_ID 32'h7f000000
`define SPLL_TRR_R0_DISC_OFFSET 31
`define SPLL_TRR_R0_DISC 32'h80000000
`define ADDR_SPLL_TRR_CSR 7'h60
`define ADDR_SPLL_TRR_CSR 8'h80
`define SPLL_TRR_CSR_EMPTY_OFFSET 17
`define SPLL_TRR_CSR_EMPTY 32'h00020000
......@@ -3,7 +3,7 @@ action = "synthesis"
fetchto = "../../../ip_cores"
top_module = "spec_top"
#top_module = "spec_top"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
......@@ -12,8 +12,8 @@ syn_project = "spec_top_wrc.xise"
modules = { "local" :
[ "../../../top/spec_1_1/wr_core_demo",
"../../../platform",
"../../../ip_cores/general-cores",
"../../../ip_cores/etherbone-core",
"../../../ip_cores/gn4124-core"]
}
"../../../platform" ],
"git" :
[ "git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git" ] };
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -5,5 +5,5 @@ vlog_opt="+incdir+../../sim +incdir+gn4124_bfm"
files = [ "main.sv" ]
modules = { "local" : [ "../..", "../../top/spec_1_1/wr_core_demo", "gn4124_bfm"] }
modules = { "local" : [ "../..", "../../top/spec_1_1/wr_core_demo", "../../../general-cores", "../../../gn4124-core", "../../../etherbone-core", "gn4124_bfm"] }
-- GN412X_BFMBAR set to: BAR=0, BASE=0xFF00000000000000, MASK=0xF8000000, VC=0, TC=0x7, S=0
-- GN412X_BFMBFM BAR set to: BAR=0, BASE=0x0000000040000000, MASK=0xE0000000
-- GN412X_BFMBFM BAR set to: BAR=1, BASE=0x0000000020000000, MASK=0xE0000000
--<<<< P2L Header: (P2L Target Write), FBE=0xF, LBE=0xF, V=0, LENGTH=0x001--<<<< Address: 0x00000000000A021C @ 2217 ns
......@@ -7,7 +7,10 @@ const uint64_t BASE_WRPC = 'h0080000;
module main;
reg clk_125m_pllref = 0;
reg clk_20m_vcxo = 0;
reg clk_ext = 0;
always #50ns clk_ext <= ~clk_ext;
always #4ns clk_125m_pllref <= ~clk_125m_pllref;
always #20ns clk_20m_vcxo <= ~clk_20m_vcxo;
......@@ -44,7 +47,7 @@ module main;
//$display("dupa1");
//acc.write('ha0400, 'h0deadbee);
//$display("dupa2");
acc.write('ha021c, 'hfafa);
//acc.write('ha021c, 'hfafa);
$display("dupa3");
......
onerror {resume}
quietly WaveActivateNextPane {} 0
#add wave -noupdate /main/DUT/U_VIC/g_interface_mode
#add wave -noupdate /main/DUT/U_VIC/g_address_granularity
#add wave -noupdate /main/DUT/U_VIC/g_num_interrupts
#add wave -noupdate /main/DUT/U_VIC/clk_sys_i
#add wave -noupdate /main/DUT/U_VIC/rst_n_i
#add wave -noupdate /main/DUT/U_VIC/slave_i
#add wave -noupdate /main/DUT/U_VIC/slave_o
#add wave -noupdate /main/DUT/U_VIC/irqs_i
#add wave -noupdate /main/DUT/U_VIC/irq_master_o
add wave -noupdate /main/clk_125m_pllref
add wave -noupdate /main/clk_20m_vcxo
add wave -noupdate /main/DUT/clk_20m_vcxo_i
add wave -noupdate /main/DUT/clk_125m_pllref_p_i
add wave -noupdate /main/DUT/clk_125m_pllref_n_i
add wave -noupdate /main/DUT/fpga_pll_ref_clk_101_p_i
add wave -noupdate /main/DUT/fpga_pll_ref_clk_101_n_i
add wave -noupdate /main/DUT/L_CLKp
add wave -noupdate /main/DUT/L_CLKn
add wave -noupdate /main/DUT/L_RST_N
add wave -noupdate /main/I_Gennum/ready
add wave -noupdate /main/I_Gennum/p2l_data
add wave -noupdate /main/I_Gennum/p2l_valid
add wave -noupdate /main/DUT/cmp_gn4124_core/p2l_data_i
add wave -noupdate /main/DUT/cmp_gn4124_core/p2l_valid_i
add wave -noupdate /main/DUT/cmp_gn4124_core/csr_adr_o
add wave -noupdate /main/DUT/cmp_gn4124_core/csr_dat_o
add wave -noupdate /main/DUT/cmp_gn4124_core/dma_adr_o
add wave -noupdate /main/DUT/cmp_gn4124_core/dma_dat_o
add wave -noupdate /main/DUT/dac_hpll_data
add wave -noupdate /main/DUT/dac_hpll_load_p1
add wave -noupdate /main/DUT/dac_cs1_n_o
add wave -noupdate /main/DUT/dac_cs2_n_o
add wave -noupdate /main/DUT/dac_clr_n_o
add wave -noupdate /main/DUT/GPIO
add wave -noupdate /main/DUT/P2L_RDY
add wave -noupdate /main/DUT/P2L_CLKn
add wave -noupdate /main/DUT/P2L_CLKp
add wave -noupdate /main/DUT/P2L_DATA
add wave -noupdate /main/DUT/P2L_DFRAME
add wave -noupdate /main/DUT/P2L_VALID
add wave -noupdate /main/DUT/P_WR_REQ
add wave -noupdate /main/DUT/P_WR_RDY
add wave -noupdate /main/DUT/RX_ERROR
add wave -noupdate /main/DUT/L2P_DATA
add wave -noupdate /main/DUT/L2P_DFRAME
add wave -noupdate /main/DUT/L2P_VALID
add wave -noupdate /main/DUT/L2P_CLKn
add wave -noupdate /main/DUT/L2P_CLKp
add wave -noupdate /main/DUT/L2P_EDB
add wave -noupdate /main/DUT/L2P_RDY
add wave -noupdate /main/DUT/L_WR_RDY
add wave -noupdate /main/DUT/P_RD_D_RDY
add wave -noupdate /main/DUT/TX_ERROR
add wave -noupdate /main/DUT/VC_RDY
add wave -noupdate /main/DUT/LED_RED
add wave -noupdate /main/DUT/LED_GREEN
add wave -noupdate /main/DUT/dac_sclk_o
add wave -noupdate /main/DUT/dac_din_o
add wave -noupdate /main/DUT/wrc_slave_i.cyc
add wave -noupdate /main/DUT/wrc_slave_i.stb
add wave -noupdate /main/DUT/wrc_slave_i.adr
add wave -noupdate /main/DUT/wrc_slave_i.dat
add wave -noupdate /main/DUT/dac_clr_n_o
add wave -noupdate /main/DUT/dac_cs1_n_o
add wave -noupdate /main/DUT/dac_cs2_n_o
add wave -noupdate /main/DUT/fpga_scl_b
add wave -noupdate /main/DUT/fpga_sda_b
add wave -noupdate /main/DUT/button1_i
add wave -noupdate /main/DUT/button2_i
add wave -noupdate /main/DUT/thermo_id
add wave -noupdate /main/DUT/sfp_txp_o
add wave -noupdate /main/DUT/sfp_txn_o
add wave -noupdate /main/DUT/sfp_rxp_i
add wave -noupdate /main/DUT/sfp_rxn_i
add wave -noupdate /main/DUT/sfp_mod_def0_b
add wave -noupdate /main/DUT/sfp_mod_def1_b
add wave -noupdate /main/DUT/sfp_mod_def2_b
add wave -noupdate /main/DUT/sfp_rate_select_b
add wave -noupdate /main/DUT/sfp_tx_fault_i
add wave -noupdate /main/DUT/sfp_tx_disable_o
add wave -noupdate /main/DUT/sfp_los_i
add wave -noupdate /main/DUT/dio_clk_p_i
add wave -noupdate /main/DUT/dio_clk_n_i
add wave -noupdate /main/DUT/dio_n_i
add wave -noupdate /main/DUT/dio_p_i
add wave -noupdate /main/DUT/dio_n_o
add wave -noupdate /main/DUT/dio_p_o
add wave -noupdate /main/DUT/dio_oe_n_o
add wave -noupdate /main/DUT/dio_term_en_o
add wave -noupdate /main/DUT/dio_onewire_b
add wave -noupdate /main/DUT/dio_sdn_n_o
add wave -noupdate /main/DUT/dio_sdn_ck_n_o
add wave -noupdate /main/DUT/dio_led_top_o
add wave -noupdate /main/DUT/dio_led_bot_o
add wave -noupdate /main/DUT/uart_rxd_i
add wave -noupdate /main/DUT/uart_txd_o
add wave -noupdate /main/DUT/l_clk
add wave -noupdate /main/DUT/gtp_dedicated_clk
add wave -noupdate /main/DUT/p2l_pll_locked
add wave -noupdate /main/DUT/rst_a
add wave -noupdate /main/DUT/rst
add wave -noupdate /main/DUT/ram_we
add wave -noupdate /main/DUT/ddr_dma_adr
add wave -noupdate /main/DUT/irq_to_gn4124
add wave -noupdate /main/DUT/spi_slave_select
add wave -noupdate /main/DUT/pllout_clk_sys
add wave -noupdate /main/DUT/pllout_clk_dmtd
add wave -noupdate /main/DUT/pllout_clk_fb_pllref
add wave -noupdate /main/DUT/pllout_clk_fb_dmtd
add wave -noupdate /main/DUT/clk_20m_vcxo_buf
add wave -noupdate /main/DUT/clk_125m_pllref
add wave -noupdate /main/DUT/clk_sys
add wave -noupdate /main/DUT/clk_dmtd
add wave -noupdate /main/DUT/dac_rst_n
add wave -noupdate /main/DUT/led_divider
add wave -noupdate /main/DUT/wrc_scl_o
add wave -noupdate /main/DUT/wrc_scl_i
add wave -noupdate /main/DUT/wrc_sda_o
add wave -noupdate /main/DUT/wrc_sda_i
add wave -noupdate /main/DUT/sfp_scl_o
add wave -noupdate /main/DUT/sfp_scl_i
add wave -noupdate /main/DUT/sfp_sda_o
add wave -noupdate /main/DUT/sfp_sda_i
add wave -noupdate /main/DUT/dio
add wave -noupdate /main/DUT/dac_hpll_load_p1
add wave -noupdate /main/DUT/dac_dpll_load_p1
add wave -noupdate /main/DUT/dac_hpll_data
add wave -noupdate /main/DUT/dac_dpll_data
add wave -noupdate /main/DUT/pps
add wave -noupdate /main/DUT/pps_led
add wave -noupdate /main/DUT/phy_tx_data
add wave -noupdate /main/DUT/phy_tx_k
add wave -noupdate /main/DUT/phy_tx_disparity
add wave -noupdate /main/DUT/phy_tx_enc_err
add wave -noupdate /main/DUT/phy_rx_data
add wave -noupdate /main/DUT/phy_rx_rbclk
add wave -noupdate /main/DUT/phy_rx_k
add wave -noupdate /main/DUT/phy_rx_enc_err
add wave -noupdate /main/DUT/phy_rx_bitslide
add wave -noupdate /main/DUT/phy_rst
add wave -noupdate /main/DUT/phy_loopen
add wave -noupdate /main/DUT/dio_in
add wave -noupdate /main/DUT/dio_out
add wave -noupdate /main/DUT/dio_clk
add wave -noupdate /main/DUT/local_reset_n
add wave -noupdate /main/DUT/button1_synced
add wave -noupdate /main/DUT/genum_wb_out
add wave -noupdate /main/DUT/genum_wb_in
add wave -noupdate /main/DUT/genum_csr_ack_i
add wave -noupdate /main/DUT/wrc_slave_i
add wave -noupdate /main/DUT/wrc_slave_o
add wave -noupdate /main/DUT/owr_en
add wave -noupdate /main/DUT/owr_i
add wave -noupdate /main/DUT/wb_adr
add wave -noupdate /main/DUT/etherbone_rst_n
add wave -noupdate /main/DUT/etherbone_src_out
add wave -noupdate /main/DUT/etherbone_src_in
add wave -noupdate /main/DUT/etherbone_snk_out
add wave -noupdate /main/DUT/etherbone_snk_in
add wave -noupdate /main/DUT/etherbone_wb_out
add wave -noupdate /main/DUT/etherbone_wb_in
add wave -noupdate /main/DUT/etherbone_cfg_in
add wave -noupdate /main/DUT/etherbone_cfg_out
add wave -noupdate /main/DUT/local_reset
add wave -noupdate /main/DUT/ext_pll_reset
add wave -noupdate /main/DUT/clk_ext
add wave -noupdate /main/DUT/clk_ext_mul
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2367015 ps} 0}
configure wave -namecolwidth 150
......@@ -55,4 +154,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {26250 ns}
WaveRestoreZoom {0 ps} {31500 ns}
......@@ -240,6 +240,13 @@ architecture rtl of spec_top is
rst_n_o : out std_logic);
end component;
component ext_pll_10_to_125m
port (
clk_ext_i : in std_logic;
clk_ext_mul_o : out std_logic;
rst_a_i : in std_logic);
end component;
--component chipscope_ila
-- port (
-- CONTROL : inout std_logic_vector(35 downto 0);
......@@ -376,9 +383,30 @@ architecture rtl of spec_top is
signal etherbone_wb_in : t_wishbone_master_in;
signal etherbone_cfg_in : t_wishbone_slave_in;
signal etherbone_cfg_out : t_wishbone_slave_out;
signal local_reset, ext_pll_reset : std_logic;
signal clk_ext, clk_ext_mul : std_logic;
signal clk_ref_div2 : std_logic;
begin
local_reset <= not local_reset_n;
U_Ext_PLL : ext_pll_10_to_125m
port map (
clk_ext_i => clk_ext,
clk_ext_mul_o => clk_ext_mul,
rst_a_i => ext_pll_reset);
U_Extend_EXT_Reset : gc_extend_pulse
generic map (
g_width => 1000)
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
pulse_i => local_reset,
extended_o => ext_pll_reset);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
......@@ -623,20 +651,21 @@ begin
--
g_phys_uart => true,
g_virtual_uart => true,
g_aux_clks => 1,
g_aux_clks => 0,
g_ep_rxbuf_size => 1024,
g_dpram_initf => "wrc.ram",
g_dpram_initf => "", --wrc.ram",
g_dpram_size => 90112/4, --16384,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_125m_pllref,
clk_aux_i => (others => '0'),
clk_ext_i => dio_clk,
pps_ext_i => dio_in(3),
rst_n_i => local_reset_n,
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_125m_pllref,
clk_aux_i => (others => '0'),
clk_ext_i => clk_ext,
clk_ext_mul_i => clk_ext_mul,
pps_ext_i => dio_in(3),
rst_n_i => local_reset_n,
dac_hpll_load_p1_o => dac_hpll_load_p1,
dac_hpll_data_o => dac_hpll_data,
......@@ -656,19 +685,19 @@ begin
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
led_act_o => LED_RED,
led_link_o => LED_GREEN,
scl_o => wrc_scl_o,
scl_i => wrc_scl_i,
sda_o => wrc_sda_o,
sda_i => wrc_sda_i,
sfp_scl_o => sfp_scl_o,
sfp_scl_i => sfp_scl_i,
sfp_sda_o => sfp_sda_o,
sfp_sda_i => sfp_sda_i,
sfp_det_i => sfp_mod_def0_b,
btn1_i => button1_i,
btn2_i => button2_i,
led_act_o => LED_RED,
led_link_o => LED_GREEN,
scl_o => wrc_scl_o,
scl_i => wrc_scl_i,
sda_o => wrc_sda_o,
sda_i => wrc_sda_i,
sfp_scl_o => sfp_scl_o,
sfp_scl_i => sfp_scl_i,
sfp_sda_o => sfp_sda_o,
sfp_sda_i => sfp_sda_i,
sfp_det_i => sfp_mod_def0_b,
btn1_i => button1_i,
btn2_i => button2_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
......@@ -689,7 +718,7 @@ begin
tm_dac_value_o => open,
tm_dac_wr_o => open,
tm_clk_aux_lock_en_i => (others=>'0'),
tm_clk_aux_lock_en_i => (others => '0'),
tm_clk_aux_locked_o => open,
tm_time_valid_o => open,
tm_tai_o => open,
......@@ -697,7 +726,7 @@ begin
pps_p_o => pps,
pps_led_o => pps_led,
dio_o => dio_out(4 downto 1),
-- dio_o => dio_out(4 downto 1),
rst_aux_n_o => etherbone_rst_n
);
......@@ -830,18 +859,28 @@ begin
OB => dio_n_o(i)
);
end generate gen_dio_iobufs;
U_input_buffer : IBUFDS
U_input_buffer : IBUFGDS
generic map (
DIFF_TERM => true)
port map (
O => dio_clk,
O => clk_ext,
I => dio_clk_p_i,
IB => dio_clk_n_i
);
dio_led_bot_o <= '0';
dio_out(0) <= pps;
process(clk_125m_pllref)
begin
if rising_edge(clk_125m_pllref) then
clk_ref_div2 <= not clk_ref_div2;
end if;
end process;
dio_out(0) <= pps;
dio_out(1) <= clk_ref_div2;
dio_oe_n_o(0) <= '0';
dio_oe_n_o(2 downto 1) <= (others => '0');
dio_oe_n_o(3) <= '1'; -- for external 1-PPS
......
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