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White Rabbit core collection
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f622e81b
Commit
f622e81b
authored
Sep 25, 2019
by
Tomasz Wlostowski
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platform: pre-validated version of kintex-7 lpdc phy
parent
2931c154
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2 changed files
with
26 additions
and
59 deletions
+26
-59
gtxe2_lp.vhd
platform/xilinx/wr_gtp_phy/kintex7-lp/gtxe2_lp.vhd
+14
-12
wr_gtx_phy_kintex7_lp.vhd
...rm/xilinx/wr_gtp_phy/kintex7-lp/wr_gtx_phy_kintex7_lp.vhd
+12
-47
No files found.
platform/xilinx/wr_gtp_phy/kintex7-lp/gtxe2_lp.vhd
View file @
f622e81b
...
...
@@ -135,7 +135,7 @@ port
TXUSRCLK_IN
:
in
std_logic
;
TXUSRCLK2_IN
:
in
std_logic
;
------------------ Transmit Ports - TX Data Path interface -----------------
txdata_in
:
in
std_logic_vector
(
7
9
downto
0
);
txdata_in
:
in
std_logic_vector
(
1
9
downto
0
);
---------------- Transmit Ports - TX Driver and OOB signaling --------------
GTXTXN_OUT
:
out
std_logic
;
GTXTXP_OUT
:
out
std_logic
;
...
...
@@ -169,6 +169,8 @@ architecture RTL of whiterabbit_gtxe2_channel_wrapper_GT is
-- RX Datapath signals
signal
rxdata_i
:
std_logic_vector
(
63
downto
0
);
signal
rxchariscomma_float_i
:
std_logic_vector
(
5
downto
0
);
signal
rxcharisk_float_i
:
std_logic_vector
(
5
downto
0
);
signal
rxdisperr_float_i
:
std_logic_vector
(
5
downto
0
);
signal
rxnotintable_float_i
:
std_logic_vector
(
5
downto
0
);
signal
rxrundisp_float_i
:
std_logic_vector
(
5
downto
0
);
signal
rxdata_out_i
:
std_logic_vector
(
19
downto
0
);
...
...
@@ -178,11 +180,11 @@ architecture RTL of whiterabbit_gtxe2_channel_wrapper_GT is
-- TX Datapath signals
signal
txdata_i
:
std_logic_vector
(
63
downto
0
);
signal
txdata_in_i
:
std_logic_vector
(
7
9
downto
0
);
signal
txdata_in_i
:
std_logic_vector
(
1
9
downto
0
);
signal
txchardispmode_i
:
std_logic_vector
(
7
downto
0
);
signal
txchardispval_i
:
std_logic_vector
(
7
downto
0
);
signal
txkerr_float_i
:
std_logic_vector
(
2
downto
0
);
signal
txrundisp_float_i
:
std_logic_vector
(
2
downto
0
);
signal
txkerr_float_i
:
std_logic_vector
(
5
downto
0
);
signal
txrundisp_float_i
:
std_logic_vector
(
5
downto
0
);
signal
rxstartofseq_float_i
:
std_logic
;
--******************************** Main Body of Code***************************
...
...
@@ -206,11 +208,11 @@ begin
rxdata_out_i
<=
(
rxdisperr_i
(
1
)
&
rxcharisk_i
(
1
)
&
rxdata_i
(
15
downto
8
)
&
rxdisperr_i
(
0
)
&
rxcharisk_i
(
0
)
&
rxdata_i
(
7
downto
0
));
------------- GT txdata_i Assignments for
8
0 bit datapath -------
------------- GT txdata_i Assignments for
2
0 bit datapath -------
txchardispmode_i
<=
(
t
xdata_in_i
(
79
)
&
txdata_in_i
(
69
)
&
txdata_in_i
(
59
)
&
txdata_in_i
(
49
)
&
txdata_in_i
(
39
)
&
txdata_in_i
(
29
)
&
txdata_in_i
(
19
)
&
txdata_in_i
(
9
));
txchardispval_i
<=
(
t
xdata_in_i
(
78
)
&
txdata_in_i
(
68
)
&
txdata_in_i
(
58
)
&
txdata_in_i
(
48
)
&
txdata_in_i
(
38
)
&
txdata_in_i
(
28
)
&
txdata_in_i
(
18
)
&
txdata_in_i
(
8
));
txdata_i
<=
(
t
xdata_in_i
(
77
downto
70
)
&
txdata_in_i
(
67
downto
60
)
&
txdata_in_i
(
57
downto
50
)
&
txdata_in_i
(
47
downto
40
)
&
txdata_in_i
(
37
downto
30
)
&
txdata_in_i
(
27
downto
2
0
)
&
txdata_in_i
(
17
downto
10
)
&
txdata_in_i
(
7
downto
0
));
txchardispmode_i
<=
(
t
ied_to_ground_vec_i
(
5
downto
0
)
&
txdata_in_i
(
19
)
&
txdata_in_i
(
9
));
txchardispval_i
<=
(
t
ied_to_ground_vec_i
(
5
downto
0
)
&
txdata_in_i
(
18
)
&
txdata_in_i
(
8
));
txdata_i
<=
(
t
ied_to_ground_vec_i
(
47
downto
0
)
&
txdata_in_i
(
17
downto
10
)
&
txdata_in_i
(
7
downto
0
));
----------------------------- GTXE2 Instance --------------------------
...
...
@@ -423,7 +425,7 @@ begin
TX_XCLK_SEL
=>
(
"TXOUT"
),
-------------------------FPGA TX Interface Attributes-------------------------
TX_DATA_WIDTH
=>
(
8
0
),
TX_DATA_WIDTH
=>
(
2
0
),
-------------------------TX Configurable Driver Attributes-------------------------
TX_DEEMPH0
=>
(
"00000"
),
...
...
@@ -463,7 +465,7 @@ begin
CPLL_LOCK_CFG
=>
(
x"01E8"
),
CPLL_REFCLK_DIV
=>
(
1
),
RXOUT_DIV
=>
(
8
),
TXOUT_DIV
=>
(
2
),
TXOUT_DIV
=>
(
8
),
SATA_CPLL_CFG
=>
(
"VCO_3000MHZ"
),
--------------RX Initialization and Reset Attributes-------------
...
...
@@ -491,7 +493,7 @@ begin
RX_INT_DATAWIDTH
=>
(
0
),
-------------------------FPGA TX Interface Attribute-------------------------
TX_INT_DATAWIDTH
=>
(
1
),
TX_INT_DATAWIDTH
=>
(
0
),
------------------TX Configurable Driver Attributes---------------
TX_QPI_STATUS_EN
=>
(
'0'
),
...
...
@@ -552,7 +554,7 @@ begin
----------------- FPGA TX Interface Datapath Configuration ----------------
TX8B10BEN
=>
'0'
,
------------------------------- Loopback Ports -----------------------------
LOOPBACK
=>
tied_to_ground_vec_i
(
2
downto
0
),
--
LOOPBACK_IN,
LOOPBACK
=>
LOOPBACK_IN
,
----------------------------- PCI Express Ports ----------------------------
PHYSTATUS
=>
open
,
RXRATE
=>
tied_to_ground_vec_i
(
2
downto
0
),
...
...
platform/xilinx/wr_gtp_phy/kintex7-lp/wr_gtx_phy_kintex7_lp.vhd
View file @
f622e81b
...
...
@@ -6,7 +6,7 @@
-- Author : Peter Jansweijer, Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2013-04-08
-- Last update: 2019-0
6-26
-- Last update: 2019-0
7-01
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -420,16 +420,17 @@ begin -- rtl
ctrl_i
=>
tx_k_i
(
1
),
out_10b_o
=>
tx_data_8b10b
(
9
downto
0
));
U_Enc2
:
entity
work
.
gc_enc_8b10b
generic
map
(
generic
map
(
g_use_internal_running_disparity
=>
false
)
port
map
(
clk_i
=>
tx_out_clk_div2
,
rst_n_i
=>
gtx_rst_n_txdiv2
,
in_8b_i
=>
tx_data_i
(
7
downto
0
),
dispar_i
=>
run_disparity_q0
,
dispar_o
=>
run_disparity_q1
,
in_8b_i
=>
tx_data_i
(
7
downto
0
),
ctrl_i
=>
tx_k_i
(
0
),
out_10b_o
=>
tx_data_8b10b
(
19
downto
10
));
...
...
@@ -437,7 +438,7 @@ generic map (
begin
if
rising_edge
(
tx_out_clk_div2
)
then
if
tx_sw_reset
=
'1
'
then
if
gtx_rst_n_txdiv2
=
'0
'
then
run_disparity_reg
<=
'0'
;
else
run_disparity_reg
<=
run_disparity_q1
;
...
...
@@ -509,10 +510,10 @@ generic map (
GTTXRESET_IN
=>
gtx_tx_reset_a
,
TXUSERRDY_IN
=>
qpll_locked_i
,
------------------ Transmit Ports - FPGA TX Interface Ports ----------------
TXUSRCLK_IN
=>
tx_out_clk
_div1
,
TXUSRCLK2_IN
=>
tx_out_clk
_div2
,
TXUSRCLK_IN
=>
tx_out_clk
,
TXUSRCLK2_IN
=>
tx_out_clk
,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA_IN
=>
f_widen
(
tx_data_8b10b
,
4
),
TXDATA_IN
=>
f_widen
(
tx_data_8b10b
,
1
),
---------------- Transmit Ports - TX Driver and OOB signaling --------------
GTXTXN_OUT
=>
pad_txn_o
,
GTXTXP_OUT
=>
pad_txp_o
,
...
...
@@ -528,52 +529,16 @@ generic map (
U_GenTxUsrClk
:
PLLE2_ADV
generic
map
(
BANDWIDTH
=>
"HIGH"
,
COMPENSATION
=>
"ZHOLD"
,
STARTUP_WAIT
=>
"FALSE"
,
DIVCLK_DIVIDE
=>
1
,
CLKFBOUT_MULT
=>
14
,
CLKFBOUT_PHASE
=>
0
.
000
,
CLKOUT0_DIVIDE
=>
28
,
CLKOUT0_PHASE
=>
0
.
000
,
CLKOUT0_DUTY_CYCLE
=>
0
.
500
,
CLKOUT1_DIVIDE
=>
14
,
CLKOUT1_PHASE
=>
0
.
000
,
CLKOUT1_DUTY_CYCLE
=>
0
.
500
,
CLKIN1_PERIOD
=>
8
.
000
)
port
map
(
CLKFBOUT
=>
pll_clkfbout_bufin
,
CLKOUT0
=>
tx_out_clk_div2_bufin
,
CLKOUT1
=>
tx_out_clk_div1_bufin
,
CLKFBIN
=>
pll_clkfbout
,
CLKIN1
=>
tx_out_clk
,
CLKIN2
=>
'0'
,
CLKINSEL
=>
'1'
,
LOCKED
=>
txusrpll_locked
,
DADDR
=>
"0000000"
,
DI
=>
x"0000"
,
DWE
=>
'0'
,
PWRDWN
=>
'0'
,
DCLK
=>
'0'
,
DEN
=>
'0'
,
RST
=>
txusrpll_reset
);
txusrpll_locked
<=
'1'
;
tx_out_clk_div2
<=
tx_out_clk
;
U_BUF_TxOutClk
:
BUFG
port
map
(
I
=>
tx_out_clk_bufin
,
O
=>
tx_out_clk
);
U_BUF_TxOutClk2
:
BUFG
port
map
(
I
=>
tx_out_clk_div2_bufin
,
O
=>
tx_out_clk_div2
);
U_BUF_TxOutClk1
:
BUFG
port
map
(
I
=>
tx_out_clk_div1_bufin
,
O
=>
tx_out_clk_div1
);
U_BUF_TxOutClkFB
:
BUFG
port
map
(
...
...
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