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White Rabbit core collection
Commit f7a594df authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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Merge branch 'wishbonized' of ohwr.org:hdl-core-lib/wr-cores into wishbonized 

Conflicts:
	modules/wrsw_pps_gen/build_wb.sh
parents 21202a78 471b2740
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Showing with 594 additions and 106 deletions
modules/wr_softpll/wr_softpll.vhd
View file @ f7a594df
......@@ -3,11 +3,14 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity wr_softpll is
generic(
g_deglitcher_threshold : integer;
g_tag_bits : integer
g_tag_bits : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port(
......@@ -16,7 +19,7 @@ entity wr_softpll is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic;
clk_aux_i: in std_logic := '0';
clk_aux_i : in std_logic := '0';
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_hpll_load_o : out std_logic;
......@@ -24,16 +27,17 @@ entity wr_softpll is
dac_dmpll_data_o : out std_logic_vector(15 downto 0);
dac_dmpll_load_o : out std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic;
debug_o : out std_logic_vector(3 downto 0)
wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
debug_o : out std_logic_vector(3 downto 0)
);
end wr_softpll;
......@@ -130,7 +134,7 @@ architecture rtl of wr_softpll is
signal per_hpll_p : std_logic;
signal tag_ref_p : std_logic;
signal tag_fb_p : std_logic;
signal tag_aux_p : std_logic;
signal tag_aux_p : std_logic;
signal rst_n_refclk : std_logic;
signal rst_n_dmtdclk : std_logic;
......@@ -141,12 +145,12 @@ architecture rtl of wr_softpll is
signal spll_per_hpll : std_logic_vector(31 downto 0);
signal spll_tag_ref : std_logic_vector(31 downto 0);
signal spll_tag_fb : std_logic_vector(31 downto 0);
signal spll_tag_aux : std_logic_vector(31 downto 0);
signal spll_tag_aux : std_logic_vector(31 downto 0);
signal tag_hpll_rd_period_ack : std_logic;
signal tag_ref_rd_ack : std_logic;
signal tag_fb_rd_ack : std_logic;
signal tag_aux_rd_ack : std_logic;
signal tag_aux_rd_ack : std_logic;
signal spll_csr_tag_en : std_logic_vector(3 downto 0);
signal spll_csr_tag_rdy : std_logic_vector(3 downto 0);
......@@ -170,9 +174,40 @@ architecture rtl of wr_softpll is
O : out std_logic;
I : in std_logic);
end component;
signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
begin -- rtl
resized_addr(5 downto 0) <= wb_addr_i;
resized_addr(c_wishbone_address_width-1 downto 4) <= (others => '0');
U_Adapter : wb_slave_adapter
generic map(
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
sl_adr_i => resized_addr,
sl_dat_i => wb_data_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
sl_stb_i => wb_stb_i,
sl_we_i => wb_we_i,
sl_dat_o => wb_data_o,
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o);
sync_ffs_rst1 : gc_sync_ffs
generic map (
g_sync_edge => "positive")
......@@ -281,12 +316,12 @@ begin -- rtl
clk_sys_i => clk_sys_i,
clk_in_i => clk_rx_buf,
tag_o => tag_ref,
tag_stb_p1_o => tag_ref_p,
shift_en_i => '0',
shift_dir_i => '0',
tag_o => tag_ref,
tag_stb_p1_o => tag_ref_p,
shift_en_i => '0',
shift_dir_i => '0',
deglitch_threshold_i => deglitch_thr_slv,
dbg_dmtdout_o => open);
dbg_dmtdout_o => open);
DMTD_AUX : dmtd_with_deglitcher
generic map (
......@@ -299,12 +334,12 @@ begin -- rtl
clk_sys_i => clk_sys_i,
clk_in_i => clk_aux_i,
tag_o => tag_aux,
tag_stb_p1_o => tag_aux_p,
shift_en_i => '0',
shift_dir_i => '0',
tag_o => tag_aux,
tag_stb_p1_o => tag_aux_p,
shift_en_i => '0',
shift_dir_i => '0',
deglitch_threshold_i => deglitch_thr_slv,
dbg_dmtdout_o => open);
dbg_dmtdout_o => open);
DMTD_FB : dmtd_with_deglitcher
generic map (
......@@ -317,13 +352,13 @@ begin -- rtl
clk_sys_i => clk_sys_i,
clk_in_i => clk_ref_buf,
tag_o => tag_fb,
tag_stb_p1_o => tag_fb_p,
shift_en_i => '0',
shift_dir_i => '0',
tag_o => tag_fb,
tag_stb_p1_o => tag_fb_p,
shift_en_i => '0',
shift_dir_i => '0',
deglitch_threshold_i => deglitch_thr_slv,
dbg_dmtdout_o => open);
dbg_dmtdout_o => open);
end generate gen_with_single_dmtd;
--buf_rx_clk : BUFG
......@@ -338,8 +373,8 @@ begin -- rtl
clk_ref_buf <= clk_ref_i;
clk_rx_buf <= clk_rx_i;
clk_rx_buf <= clk_rx_i;
PERIOD_DET : hpll_period_detect
port map (
clk_ref_i => clk_rx_buf,
......@@ -358,14 +393,14 @@ begin -- rtl
port map (
rst_n_i => rst_n_i,
wb_clk_i => clk_sys_i,
wb_addr_i => wb_addr_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_addr_i => wb_in.adr(3 downto 0),
wb_data_i => wb_in.dat,
wb_data_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_irq_o => wb_irq_o,
spll_csr_tag_en_o => spll_csr_tag_en,
......@@ -374,8 +409,8 @@ begin -- rtl
tag_ref_rd_ack_o => tag_ref_rd_ack,
spll_tag_fb_i => spll_tag_fb,
tag_fb_rd_ack_o => tag_fb_rd_ack,
spll_tag_aux_i => spll_tag_aux,
tag_aux_rd_ack_o => tag_aux_rd_ack,
spll_tag_aux_i => spll_tag_aux,
tag_aux_rd_ack_o => tag_aux_rd_ack,
spll_per_hpll_i => spll_per_hpll,
tag_hpll_rd_period_o => tag_hpll_rd_period_ack,
......@@ -425,7 +460,7 @@ begin -- rtl
end if;
if(tag_aux_p = '1') then
spll_tag_aux <= std_logic_vector(to_unsigned(0, 32-g_tag_bits)) & tag_aux;
spll_tag_aux <= std_logic_vector(to_unsigned(0, 32-g_tag_bits)) & tag_aux;
spll_csr_tag_rdy(0) <= spll_csr_tag_en(0);
elsif(tag_aux_rd_ack = '1') then
spll_csr_tag_rdy(0) <= '0';
......
modules/wr_softpll/xwb_wr_softpll.vhd 0 → 100644
View file @ f7a594df
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity xwb_wr_softpll is
generic(
g_deglitcher_threshold : integer;
g_tag_bits : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic;
clk_aux_i : in std_logic := '0';
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_hpll_load_o : out std_logic;
dac_dmpll_data_o : out std_logic_vector(15 downto 0);
dac_dmpll_load_o : out std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
wb_irq_o : out std_logic;
debug_o : out std_logic_vector(3 downto 0)
);
end wr_softpll;
architecture behavioral of xwb_wr_softpll is
component wr_softpll is
generic(
g_deglitcher_threshold : integer;
g_tag_bits : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic;
clk_aux_i : in std_logic := '0';
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_hpll_load_o : out std_logic;
dac_dmpll_data_o : out std_logic_vector(15 downto 0);
dac_dmpll_load_o : out std_logic;
wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
debug_o : out std_logic_vector(3 downto 0)
);
end component;
begin -- behavioral
WRAPPED_SOFTPLL : wr_softpll
generic map(
g_deglitcher_threshold => g_deglitcher_threshold,
g_tag_bits => g_tag_bits,
g_interface_mode => CLASSIC;
g_address_granularity => WORD
);
port(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
clk_ref_i => clk_ref_i,
clk_dmtd_i => clk_dmtd_i,
clk_rx_i => clk_rx_i,
clk_aux_i => clk_aux_i,
dac_hpll_data_o => dac_hpll_data_o,
dac_hpll_load_o => dac_hpll_load_o,
dac_dmpll_data_o => dac_dmpll_data_o,
dac_dmpll_load_o => dac_dmpll_load_o,
wb_addr_i => slave_i.adr(5 downto 0);
wb_data_i => slave_i.dat,
wb_data_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
wb_irq_o => wb_irq_o,
debug_o => debug_o
);
end behavioral;
modules/wrsw_pps_gen/Manifest.py
View file @ f7a594df
files = ["pps_gen_wb.vhd",
"wrsw_pps_gen.vhd"];
\ No newline at end of file
"wrsw_pps_gen.vhd",
"xwb_pps_gen.vhd"];
modules/wrsw_pps_gen/build_wb.sh
View file @ f7a594df
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/pps_gen.html -V pps_gen_wb.vhd -C ../../../software/include/hw/pps_gen_regs.h --cstyle defines --lang vhdl -K ../../sim/pps_gen_regs.v wrsw_pps_gen.wb
\ No newline at end of file
wbgen2 -D ./doc/pps_gen.html -V pps_gen_wb.vhd -C ../../../software/include/hw/pps_gen_regs.h --cstyle defines --lang vhdl -K ../../sim/pps_gen_regs.v wrsw_pps_gen.wb
modules/wrsw_pps_gen/pps_gen_regs.h 0 → 100644
View file @ f7a594df
/*
Register definitions for slave core: WR Switch PPS generator and RTC
* File : pps_gen_regs.h
* Author : auto-generated by wbgen2 from wrsw_pps_gen.wb
* Created : Thu Oct 27 21:29:19 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_pps_gen.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB
#define __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control Register */
/* definitions for field: Reset counter in reg: Control Register */
#define PPSG_CR_CNT_RST WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Enable counter in reg: Control Register */
#define PPSG_CR_CNT_EN WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Adjust offset in reg: Control Register */
#define PPSG_CR_CNT_ADJ WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Set time in reg: Control Register */
#define PPSG_CR_CNT_SET WBGEN2_GEN_MASK(3, 1)
/* definitions for field: PPS Pulse width in reg: Control Register */
#define PPSG_CR_PWIDTH_MASK WBGEN2_GEN_MASK(4, 28)
#define PPSG_CR_PWIDTH_SHIFT 4
#define PPSG_CR_PWIDTH_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define PPSG_CR_PWIDTH_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Nanosecond counter register */
/* definitions for register: UTC Counter register (least-significant part) */
/* definitions for register: UTC Counter register (most-significant part) */
/* definitions for register: Nanosecond adjustment register */
/* definitions for register: UTC Adjustment register (least-significant part) */
/* definitions for register: UTC Adjustment register (most-significant part) */
/* definitions for register: External sync control register */
/* definitions for field: Sync to external PPS input in reg: External sync control register */
#define PPSG_ESCR_SYNC WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PPS output valid in reg: External sync control register */
#define PPSG_ESCR_PPS_VALID WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timecode output(UTC+cycles) valid in reg: External sync control register */
#define PPSG_ESCR_TM_VALID WBGEN2_GEN_MASK(2, 1)
PACKED struct PPSG_WB {
/* [0x0]: REG Control Register */
uint32_t CR;
/* [0x4]: REG Nanosecond counter register */
uint32_t CNTR_NSEC;
/* [0x8]: REG UTC Counter register (least-significant part) */
uint32_t CNTR_UTCLO;
/* [0xc]: REG UTC Counter register (most-significant part) */
uint32_t CNTR_UTCHI;
/* [0x10]: REG Nanosecond adjustment register */
uint32_t ADJ_NSEC;
/* [0x14]: REG UTC Adjustment register (least-significant part) */
uint32_t ADJ_UTCLO;
/* [0x18]: REG UTC Adjustment register (most-significant part) */
uint32_t ADJ_UTCHI;
/* [0x1c]: REG External sync control register */
uint32_t ESCR;
};
#endif
modules/wrsw_pps_gen/pps_gen_wb.vhd
View file @ f7a594df
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : pps_gen_wb.vhd
-- Author : auto-generated by wbgen2 from wrsw_pps_gen.wb
-- Created : Mon May 9 00:28:48 2011
-- Created : Thu Oct 27 21:29:19 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_pps_gen.wb
......@@ -57,7 +57,11 @@ entity pps_gen_wb is
-- Ports for asynchronous (clock: refclk_i) RW/RW BIT field: 'Sync to external PPS input' in reg: 'External sync control register'
ppsg_escr_sync_o : out std_logic;
ppsg_escr_sync_i : in std_logic;
ppsg_escr_sync_load_o : out std_logic
ppsg_escr_sync_load_o : out std_logic;
-- Port for asynchronous (clock: refclk_i) BIT field: 'PPS output valid' in reg: 'External sync control register'
ppsg_escr_pps_valid_o : out std_logic;
-- Port for asynchronous (clock: refclk_i) BIT field: 'Timecode output(UTC+cycles) valid' in reg: 'External sync control register'
ppsg_escr_tm_valid_o : out std_logic
);
end pps_gen_wb;
......@@ -121,6 +125,12 @@ signal ppsg_escr_sync_lw_s0 : std_logic ;
signal ppsg_escr_sync_lw_s1 : std_logic ;
signal ppsg_escr_sync_lw_s2 : std_logic ;
signal ppsg_escr_sync_rwsel : std_logic ;
signal ppsg_escr_pps_valid_int : std_logic ;
signal ppsg_escr_pps_valid_sync0 : std_logic ;
signal ppsg_escr_pps_valid_sync1 : std_logic ;
signal ppsg_escr_tm_valid_int : std_logic ;
signal ppsg_escr_tm_valid_sync0 : std_logic ;
signal ppsg_escr_tm_valid_sync1 : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -180,6 +190,8 @@ begin
ppsg_escr_sync_lw_read_in_progress <= '0';
ppsg_escr_sync_rwsel <= '0';
ppsg_escr_sync_int_write <= '0';
ppsg_escr_pps_valid_int <= '0';
ppsg_escr_tm_valid_int <= '0';
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -236,25 +248,32 @@ begin
case rwaddr_reg(2 downto 0) is
when "000" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
ppsg_cr_cnt_rst_int <= wrdata_reg(0);
ppsg_cr_cnt_rst_int_delay <= wrdata_reg(0);
ppsg_cr_cnt_en_int <= wrdata_reg(1);
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
ppsg_cr_cnt_adj_int_write <= wrdata_reg(2);
ppsg_cr_cnt_adj_lw <= '1';
ppsg_cr_cnt_adj_lw_delay <= '1';
ppsg_cr_cnt_adj_lw_read_in_progress <= '0';
ppsg_cr_cnt_adj_rwsel <= '1';
rddata_reg(3) <= 'X';
ppsg_cr_cnt_set_int <= wrdata_reg(3);
ppsg_cr_cnt_set_int_delay <= wrdata_reg(3);
ppsg_cr_pwidth_int <= wrdata_reg(31 downto 4);
ppsg_cr_pwidth_swb <= '1';
ppsg_cr_pwidth_swb_delay <= '1';
else
rddata_reg(0) <= 'X';
rddata_reg(1) <= ppsg_cr_cnt_en_int;
rddata_reg(2) <= 'X';
ppsg_cr_cnt_adj_lw <= '1';
ppsg_cr_cnt_adj_lw_delay <= '1';
ppsg_cr_cnt_adj_lw_read_in_progress <= '1';
ppsg_cr_cnt_adj_rwsel <= '0';
rddata_reg(3) <= 'X';
rddata_reg(31 downto 4) <= ppsg_cr_pwidth_int;
end if;
ack_sreg(5) <= '1';
......@@ -433,18 +452,24 @@ begin
ack_in_progress <= '1';
when "111" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
ppsg_escr_sync_int_write <= wrdata_reg(0);
ppsg_escr_sync_lw <= '1';
ppsg_escr_sync_lw_delay <= '1';
ppsg_escr_sync_lw_read_in_progress <= '0';
ppsg_escr_sync_rwsel <= '1';
ppsg_escr_pps_valid_int <= wrdata_reg(1);
rddata_reg(1) <= 'X';
ppsg_escr_tm_valid_int <= wrdata_reg(2);
rddata_reg(2) <= 'X';
else
rddata_reg(0) <= 'X';
ppsg_escr_sync_lw <= '1';
ppsg_escr_sync_lw_delay <= '1';
ppsg_escr_sync_lw_read_in_progress <= '1';
ppsg_escr_sync_rwsel <= '0';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(1) <= ppsg_escr_pps_valid_int;
rddata_reg(2) <= ppsg_escr_tm_valid_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
......@@ -689,6 +714,38 @@ begin
end process;
-- PPS output valid
-- synchronizer chain for field : PPS output valid (type RW/RO, bus_clock_int <-> refclk_i)
process (refclk_i, rst_n_i)
begin
if (rst_n_i = '0') then
ppsg_escr_pps_valid_o <= '0';
ppsg_escr_pps_valid_sync0 <= '0';
ppsg_escr_pps_valid_sync1 <= '0';
elsif rising_edge(refclk_i) then
ppsg_escr_pps_valid_sync0 <= ppsg_escr_pps_valid_int;
ppsg_escr_pps_valid_sync1 <= ppsg_escr_pps_valid_sync0;
ppsg_escr_pps_valid_o <= ppsg_escr_pps_valid_sync1;
end if;
end process;
-- Timecode output(UTC+cycles) valid
-- synchronizer chain for field : Timecode output(UTC+cycles) valid (type RW/RO, bus_clock_int <-> refclk_i)
process (refclk_i, rst_n_i)
begin
if (rst_n_i = '0') then
ppsg_escr_tm_valid_o <= '0';
ppsg_escr_tm_valid_sync0 <= '0';
ppsg_escr_tm_valid_sync1 <= '0';
elsif rising_edge(refclk_i) then
ppsg_escr_tm_valid_sync0 <= ppsg_escr_tm_valid_int;
ppsg_escr_tm_valid_sync1 <= ppsg_escr_tm_valid_sync0;
ppsg_escr_tm_valid_o <= ppsg_escr_tm_valid_sync1;
end if;
end process;
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
......
modules/wrsw_pps_gen/wrsw_pps_gen.vhd
View file @ f7a594df
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-09-02
-- Last update: 2011-05-11
-- Last update: 2011-10-27
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -18,6 +18,7 @@
-- Date Version Author Description
-- 2010-09-02 1.0 twlostow Created
-- 2011-05-09 1.1 twlostow Added external PPS input
-- 2011-10-26 1.2 greg.d Added wb slave adapter
-------------------------------------------------------------------------------
library ieee;
......@@ -26,29 +27,39 @@ use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity wrsw_pps_gen is
generic(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
rst_n_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
pps_in_i : in std_logic;
-- Single-pulse PPS output for synchronizing endpoints to
pps_csync_o : out std_logic;
pps_out_o : out std_logic
pps_out_o : out std_logic;
pps_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic
);
end wrsw_pps_gen;
......@@ -87,7 +98,9 @@ architecture behavioral of wrsw_pps_gen is
ppsg_adj_utchi_wr_o : out std_logic;
ppsg_escr_sync_o : out std_logic;
ppsg_escr_sync_i : in std_logic;
ppsg_escr_sync_load_o : out std_logic);
ppsg_escr_sync_load_o : out std_logic;
ppsg_escr_pps_valid_o : out std_logic;
ppsg_escr_tm_valid_o : out std_logic);
end component;
......@@ -106,17 +119,18 @@ architecture behavioral of wrsw_pps_gen is
signal ppsg_cntr_utclo : std_logic_vector(31 downto 0);
signal ppsg_cntr_utchi : std_logic_vector(7 downto 0);
signal ppsg_adj_nsec : std_logic_vector(27 downto 0);
signal ppsg_adj_nsec_wr : std_logic;
signal ppsg_adj_utclo : std_logic_vector(31 downto 0);
signal ppsg_adj_utclo_wr : std_logic;
signal ppsg_adj_utchi : std_logic_vector(7 downto 0);
signal ppsg_adj_utchi_wr : std_logic;
signal ppsg_escr_sync_load : std_logic;
signal ppsg_escr_sync_in : std_logic;
signal ppsg_adj_nsec : std_logic_vector(27 downto 0);
signal ppsg_adj_nsec_wr : std_logic;
signal ppsg_adj_utclo : std_logic_vector(31 downto 0);
signal ppsg_adj_utclo_wr : std_logic;
signal ppsg_adj_utchi : std_logic_vector(7 downto 0);
signal ppsg_adj_utchi_wr : std_logic; signal ppsg_escr_sync_load : std_logic;
signal ppsg_escr_sync_in : std_logic;
signal ppsg_escr_sync_out : std_logic;
signal ppsg_escr_pps_valid : std_logic;
signal ppsg_escr_tm_valid : std_logic;
signal cntr_nsec : unsigned (27 downto 0);
signal cntr_utc : unsigned (39 downto 0);
......@@ -139,9 +153,39 @@ architecture behavioral of wrsw_pps_gen is
signal pps_in_p : std_logic;
signal sync_in_progress : std_logic;
signal ext_sync_p : std_logic;
signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
begin -- behavioral
resized_addr(4 downto 0) <= wb_addr_i;
resized_addr(c_wishbone_address_width-1 downto 5) <= (others => '0');
U_Adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
sl_adr_i => resized_addr,
sl_dat_i => wb_data_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
sl_stb_i => wb_stb_i,
sl_we_i => wb_we_i,
sl_dat_o => wb_data_o,
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o);
sync_reset_refclk : gc_sync_ffs
generic map (
......@@ -306,36 +350,38 @@ begin -- behavioral
Uwb_slave : pps_gen_wb
port map (
rst_n_i => rst_n_i,
wb_clk_i => clk_sys_i,
wb_addr_i => wb_addr_i(2 downto 0),
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
refclk_i => clk_ref_i,
ppsg_cr_cnt_rst_o => ppsg_cr_cnt_rst,
ppsg_cr_cnt_en_o => ppsg_cr_cnt_en,
ppsg_cr_cnt_adj_o => ppsg_cr_cnt_adj_o,
ppsg_cr_cnt_adj_i => ppsg_cr_cnt_adj_i,
ppsg_cr_cnt_adj_load_o => ppsg_cr_cnt_adj_load,
ppsg_escr_sync_o => ppsg_escr_sync_out,
ppsg_escr_sync_i => ppsg_escr_sync_in,
ppsg_escr_sync_load_o => ppsg_escr_sync_load,
ppsg_cr_cnt_set_o => ppsg_cr_cnt_set_p,
ppsg_cr_pwidth_o => ppsg_cr_pwidth,
ppsg_cntr_nsec_i => ppsg_cntr_nsec,
ppsg_cntr_utclo_i => ppsg_cntr_utclo,
ppsg_cntr_utchi_i => ppsg_cntr_utchi,
ppsg_adj_nsec_o => ppsg_adj_nsec,
ppsg_adj_nsec_wr_o => ppsg_adj_nsec_wr,
ppsg_adj_utclo_o => ppsg_adj_utclo,
ppsg_adj_utclo_wr_o => ppsg_adj_utclo_wr,
ppsg_adj_utchi_o => ppsg_adj_utchi,
ppsg_adj_utchi_wr_o => ppsg_adj_utchi_wr);
rst_n_i => rst_n_i,
wb_clk_i => clk_sys_i,
wb_addr_i => wb_in.adr(2 downto 0),
wb_data_i => wb_in.dat,
wb_data_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
refclk_i => clk_ref_i,
ppsg_cr_cnt_rst_o => ppsg_cr_cnt_rst,
ppsg_cr_cnt_en_o => ppsg_cr_cnt_en,
ppsg_cr_cnt_adj_o => ppsg_cr_cnt_adj_o,
ppsg_cr_cnt_adj_i => ppsg_cr_cnt_adj_i,
ppsg_cr_cnt_adj_load_o => ppsg_cr_cnt_adj_load,
ppsg_escr_sync_o => ppsg_escr_sync_out,
ppsg_escr_sync_i => ppsg_escr_sync_in,
ppsg_escr_sync_load_o => ppsg_escr_sync_load,
ppsg_cr_cnt_set_o => ppsg_cr_cnt_set_p,
ppsg_cr_pwidth_o => ppsg_cr_pwidth,
ppsg_cntr_nsec_i => ppsg_cntr_nsec,
ppsg_cntr_utclo_i => ppsg_cntr_utclo,
ppsg_cntr_utchi_i => ppsg_cntr_utchi,
ppsg_adj_nsec_o => ppsg_adj_nsec,
ppsg_adj_nsec_wr_o => ppsg_adj_nsec_wr,
ppsg_adj_utclo_o => ppsg_adj_utclo,
ppsg_adj_utclo_wr_o => ppsg_adj_utclo_wr,
ppsg_adj_utchi_o => ppsg_adj_utchi,
ppsg_adj_utchi_wr_o => ppsg_adj_utchi_wr,
ppsg_escr_pps_valid_o => ppsg_escr_pps_valid,
ppsg_escr_tm_valid_o => ppsg_escr_tm_valid);
-- start the adjustment upon write of 1 to CNT_ADJ bit
cntr_adjust_p <= ppsg_cr_cnt_adj_load and ppsg_cr_cnt_adj_o;
......@@ -358,18 +404,18 @@ begin -- behavioral
begin
if rising_edge(clk_ref_i) then
if(rst_synced_refclk = '0') then
ext_sync_p <= '0';
sync_in_progress <= '0';
ext_sync_p <= '0';
sync_in_progress <= '0';
ppsg_escr_sync_in <= '0';
else
if(ppsg_escr_sync_load = '1' and ppsg_escr_sync_out = '1') then
sync_in_progress <= '1';
sync_in_progress <= '1';
ppsg_escr_sync_in <= '0';
end if;
if(sync_in_progress = '1' and pps_in_p = '1') then
ext_sync_p <= '1';
sync_in_progress <= '0';
ext_sync_p <= '1';
sync_in_progress <= '0';
ppsg_escr_sync_in <= '1';
else
ext_sync_p <= '0';
......@@ -377,5 +423,10 @@ begin -- behavioral
end if;
end if;
end process;
tm_utc_o <= std_logic_vector(cntr_utc);
tm_cycles_o <= std_logic_vector(cntr_nsec);
tm_time_valid_o <= ppsg_escr_tm_valid;
pps_valid_o <= ppsg_escr_pps_valid;
end behavioral;
modules/wrsw_pps_gen/wrsw_pps_gen.wb
View file @ f7a594df
......@@ -169,6 +169,29 @@ peripheral {
load = LOAD_EXT;
clock = "refclk_i";
};
field {
name = "PPS output valid";
description = "write 1: PPS output provides reliable 1-PPS signal\
write 0: PPS output is invalid";
prefix = "PPS_VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "refclk_i";
};
field {
name = "Timecode output(UTC+cycles) valid";
description = "write 1: Timecode output provides valid time\
write 0: Timecode output does not provide valid time";
prefix = "TM_VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "refclk_i";
};
};
};
modules/wrsw_pps_gen/xwb_pps_gen.vhd 0 → 100644
View file @ f7a594df
-------------------------------------------------------------------------------
-- Title : PPS Generator & UTC Realtime clock
-- Project : WhiteRabbit Switch
-------------------------------------------------------------------------------
-- File : xwb_pps_gen.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-09-02
-- Last update: 2011-10-27
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-09-02 1.0 twlostow Created
-- 2011-05-09 1.1 twlostow Added external PPS input
-- 2011-10-26 1.2 greg.d xwb module
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity xwb_pps_gen is
generic(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pps_in_i : in std_logic;
-- Single-pulse PPS output for synchronizing endpoints to
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
pps_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic
);
end xwb_pps_gen;
architecture behavioral of xwb_pps_gen is
component wrsw_pps_gen is
generic(
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity
);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
pps_in_i : in std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
pps_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic
);
end component;
begin -- behavioral
WRAPPED_PPSGEN : wrsw_pps_gen
generic map(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity
)
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
wb_addr_i => slave_i.adr(4 downto 0),
wb_data_i => slave_i.dat,
wb_data_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
pps_in_i => pps_in_i,
pps_csync_o => pps_csync_o,
pps_out_o => pps_out_o,
pps_valid_o => pps_valid_o,
tm_utc_o => tm_utc_o,
tm_cycles_o => tm_cycles_o,
tm_time_valid_o => tm_time_valid_o
);
end behavioral;
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