modules/wr_tbi_phy: dec_8b10b is now in general_cores

f99a845e · Grzegorz Daniluk · 3840ad26 · f99a845e · f99a845e
Commit f99a845e authored Aug 25, 2017 by Grzegorz Daniluk
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Showing with 3 additions and 4 deletions

Manifest.py modules/wr_tbi_phy/Manifest.py +1 -2

wr_tbi_phy.vhd modules/wr_tbi_phy/wr_tbi_phy.vhd +2 -2

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--- a/modules/wr_tbi_phy/Manifest.py
+++ b/modules/wr_tbi_phy/Manifest.py
-files = [	"dec_8b10b.vhd",
-                "enc_8b10b.vhd",
+files = [	"enc_8b10b.vhd",
                "wr_tbi_phy.vhd",
                "disparity_gen_pkg.vhd" ];
--- a/modules/wr_tbi_phy/wr_tbi_phy.vhd
+++ b/modules/wr_tbi_phy/wr_tbi_phy.vhd
@@ -66,7 +66,7 @@ end wr_tbi_phy;

 architecture rtl of wr_tbi_phy is

-  component dec_8b10b
+  component gc_dec_8b10b
    port (
      clk_i       : in  std_logic;
      rst_n_i     : in  std_logic;
@@ -124,7 +124,7 @@ begin  -- rtl
    end if;
  end process;

-  U_DEC : dec_8b10b
+  U_DEC : gc_dec_8b10b
    port map (
      clk_i    => tbi_rbclk_i,
      rst_n_i  => rst_synced_rbclk_n,