Commit fd2f6589 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

pps_gen: add separate flags for setting seconds and nanoseconds

When WR PTP Core is set in GrandMaster mode it aligns its nanosecond
counter to 1-PPS and 10MHz coming from external source. When user wants
to set seconds counter to a desired value, the nanosecond counter was
also set (zeroed) causing additional (random) offset to the external
source.
parent e59ec3ed
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/pps_gen.html -V pps_gen_wb.vhd -C pps_gen_regs.h --cstyle defines --lang vhdl -K ../../sim/pps_gen_regs.v pps_gen_wb.wb
wbgen2 -D ./doc/pps_gen.html -V pps_gen_wb.vhd -C pps_gen_regs.h --cstyle struct --lang vhdl -K ../../sim/pps_gen_regs.v pps_gen_wb.wb
......@@ -3,7 +3,7 @@
* File : pps_gen_regs.h
* Author : auto-generated by wbgen2 from pps_gen_wb.wb
* Created : Thu Feb 14 11:00:34 2013
* Created : Fri Jul 26 15:09:09 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
......@@ -73,20 +73,30 @@
/* definitions for field: Timecode output(UTC+cycles) valid in reg: External sync control register */
#define PPSG_ESCR_TM_VALID WBGEN2_GEN_MASK(2, 1)
/* [0x0]: REG Control Register */
#define PPSG_REG_CR 0x00000000
/* [0x4]: REG Nanosecond counter register */
#define PPSG_REG_CNTR_NSEC 0x00000004
/* [0x8]: REG UTC Counter register (least-significant part) */
#define PPSG_REG_CNTR_UTCLO 0x00000008
/* [0xc]: REG UTC Counter register (most-significant part) */
#define PPSG_REG_CNTR_UTCHI 0x0000000c
/* [0x10]: REG Nanosecond adjustment register */
#define PPSG_REG_ADJ_NSEC 0x00000010
/* [0x14]: REG UTC Adjustment register (least-significant part) */
#define PPSG_REG_ADJ_UTCLO 0x00000014
/* [0x18]: REG UTC Adjustment register (most-significant part) */
#define PPSG_REG_ADJ_UTCHI 0x00000018
/* [0x1c]: REG External sync control register */
#define PPSG_REG_ESCR 0x0000001c
/* definitions for field: Set seconds counter in reg: External sync control register */
#define PPSG_ESCR_SEC_SET WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Set nanoseconds counter in reg: External sync control register */
#define PPSG_ESCR_NSEC_SET WBGEN2_GEN_MASK(4, 1)
PACKED struct PPSG_WB {
/* [0x0]: REG Control Register */
uint32_t CR;
/* [0x4]: REG Nanosecond counter register */
uint32_t CNTR_NSEC;
/* [0x8]: REG UTC Counter register (least-significant part) */
uint32_t CNTR_UTCLO;
/* [0xc]: REG UTC Counter register (most-significant part) */
uint32_t CNTR_UTCHI;
/* [0x10]: REG Nanosecond adjustment register */
uint32_t ADJ_NSEC;
/* [0x14]: REG UTC Adjustment register (least-significant part) */
uint32_t ADJ_UTCLO;
/* [0x18]: REG UTC Adjustment register (most-significant part) */
uint32_t ADJ_UTCHI;
/* [0x1c]: REG External sync control register */
uint32_t ESCR;
};
#endif
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : pps_gen_wb.vhd
-- Author : auto-generated by wbgen2 from pps_gen_wb.wb
-- Created : Thu Feb 14 11:00:34 2013
-- Created : Fri Jul 26 15:09:09 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
......@@ -62,7 +62,11 @@ entity pps_gen_wb is
-- Port for asynchronous (clock: refclk_i) BIT field: 'PPS output valid' in reg: 'External sync control register'
ppsg_escr_pps_valid_o : out std_logic;
-- Port for asynchronous (clock: refclk_i) BIT field: 'Timecode output(UTC+cycles) valid' in reg: 'External sync control register'
ppsg_escr_tm_valid_o : out std_logic
ppsg_escr_tm_valid_o : out std_logic;
-- Port for MONOSTABLE field: 'Set seconds counter' in reg: 'External sync control register'
ppsg_escr_sec_set_o : out std_logic;
-- Port for MONOSTABLE field: 'Set nanoseconds counter' in reg: 'External sync control register'
ppsg_escr_nsec_set_o : out std_logic
);
end pps_gen_wb;
......@@ -132,6 +136,10 @@ signal ppsg_escr_pps_valid_sync1 : std_logic ;
signal ppsg_escr_tm_valid_int : std_logic ;
signal ppsg_escr_tm_valid_sync0 : std_logic ;
signal ppsg_escr_tm_valid_sync1 : std_logic ;
signal ppsg_escr_sec_set_dly0 : std_logic ;
signal ppsg_escr_sec_set_int : std_logic ;
signal ppsg_escr_nsec_set_dly0 : std_logic ;
signal ppsg_escr_nsec_set_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -191,6 +199,8 @@ begin
ppsg_escr_sync_int_write <= '0';
ppsg_escr_pps_valid_int <= '0';
ppsg_escr_tm_valid_int <= '0';
ppsg_escr_sec_set_int <= '0';
ppsg_escr_nsec_set_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -200,6 +210,8 @@ begin
ppsg_adj_nsec_wr_o <= '0';
ppsg_adj_utclo_wr_o <= '0';
ppsg_adj_utchi_wr_o <= '0';
ppsg_escr_sec_set_int <= '0';
ppsg_escr_nsec_set_int <= '0';
ack_in_progress <= '0';
else
ppsg_cr_cnt_rst_int <= ppsg_cr_cnt_rst_int_delay;
......@@ -455,6 +467,8 @@ begin
ppsg_escr_sync_rwsel <= '1';
ppsg_escr_pps_valid_int <= wrdata_reg(1);
ppsg_escr_tm_valid_int <= wrdata_reg(2);
ppsg_escr_sec_set_int <= wrdata_reg(3);
ppsg_escr_nsec_set_int <= wrdata_reg(4);
end if;
if (wb_we_i = '0') then
rddata_reg(0) <= 'X';
......@@ -465,8 +479,8 @@ begin
end if;
rddata_reg(1) <= ppsg_escr_pps_valid_int;
rddata_reg(2) <= ppsg_escr_tm_valid_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(3) <= '0';
rddata_reg(4) <= '0';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
......@@ -740,6 +754,32 @@ begin
end process;
-- Set seconds counter
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ppsg_escr_sec_set_dly0 <= '0';
ppsg_escr_sec_set_o <= '0';
elsif rising_edge(clk_sys_i) then
ppsg_escr_sec_set_dly0 <= ppsg_escr_sec_set_int;
ppsg_escr_sec_set_o <= ppsg_escr_sec_set_int and (not ppsg_escr_sec_set_dly0);
end if;
end process;
-- Set nanoseconds counter
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ppsg_escr_nsec_set_dly0 <= '0';
ppsg_escr_nsec_set_o <= '0';
elsif rising_edge(clk_sys_i) then
ppsg_escr_nsec_set_dly0 <= ppsg_escr_nsec_set_int;
ppsg_escr_nsec_set_o <= ppsg_escr_nsec_set_int and (not ppsg_escr_nsec_set_dly0);
end if;
end process;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
......@@ -192,6 +192,22 @@ peripheral {
clock = "refclk_i";
};
field {
name = "Set seconds counter";
description = "write 1: set seconds counter to the value stored in ADJ_UTCLO and ADJ_UTCHI. Nanoseconds counter stays unchanged.\
write 0: no effect";
prefix = "SEC_SET";
type = MONOSTABLE;
};
field {
name = "Set nanoseconds counter";
description = "write 1: set nanoseconds counter to the value stored in ADJ_NSEC. Seconds counter stays unchanged.\
write 0: no effect";
prefix = "NSEC_SET";
type = MONOSTABLE;
};
};
};
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-09-02
-- Last update: 2012-08-08
-- Last update: 2013-07-26
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -110,7 +110,9 @@ architecture behavioral of wr_pps_gen is
ppsg_escr_sync_i : in std_logic;
ppsg_escr_sync_load_o : out std_logic;
ppsg_escr_pps_valid_o : out std_logic;
ppsg_escr_tm_valid_o : out std_logic);
ppsg_escr_tm_valid_o : out std_logic;
ppsg_escr_sec_set_o : out std_logic;
ppsg_escr_nsec_set_o : out std_logic);
end component;
......@@ -138,6 +140,8 @@ architecture behavioral of wr_pps_gen is
signal ppsg_escr_sync_load : std_logic;
signal ppsg_escr_sync_in : std_logic;
signal ppsg_escr_sync_out : std_logic;
signal ppsg_escr_sec_set : std_logic;
signal ppsg_escr_nsec_set : std_logic;
signal ppsg_escr_pps_valid : std_logic;
signal ppsg_escr_tm_valid : std_logic;
......@@ -385,7 +389,7 @@ begin -- behavioral
end if;
-- got SET TIME command - load the counter with new value
if(ppsg_cr_cnt_set_p = '1' or ext_sync_p = '1') then
if(ppsg_cr_cnt_set_p = '1' or ext_sync_p = '1' or ppsg_escr_nsec_set = '1') then
cntr_nsec <= adj_nsec;
adjust_done_nsec <= '1';
ns_overflow <= '0';
......@@ -456,7 +460,7 @@ begin -- behavioral
adjust_in_progress_utc <= '0';
elsif(ppsg_cr_cnt_en = '1') then
if(ppsg_cr_cnt_set_p = '1') then
if(ppsg_cr_cnt_set_p = '1' or ppsg_escr_sec_set = '1') then
cntr_utc <= adj_utc;
adjust_done_utc <= '1';
elsif(cntr_adjust_p = '1') then
......@@ -555,7 +559,9 @@ begin -- behavioral
ppsg_adj_utchi_o => ppsg_adj_utchi,
ppsg_adj_utchi_wr_o => ppsg_adj_utchi_wr,
ppsg_escr_pps_valid_o => ppsg_escr_pps_valid,
ppsg_escr_tm_valid_o => ppsg_escr_tm_valid);
ppsg_escr_tm_valid_o => ppsg_escr_tm_valid,
ppsg_escr_sec_set_o => ppsg_escr_sec_set,
ppsg_escr_nsec_set_o => ppsg_escr_nsec_set);
-- start the adjustment upon write of 1 to CNT_ADJ bit
cntr_adjust_p <= ppsg_cr_cnt_adj_load and ppsg_cr_cnt_adj_o;
......
......@@ -22,3 +22,7 @@
`define PPSG_ESCR_PPS_VALID 32'h00000002
`define PPSG_ESCR_TM_VALID_OFFSET 2
`define PPSG_ESCR_TM_VALID 32'h00000004
`define PPSG_ESCR_SEC_SET_OFFSET 3
`define PPSG_ESCR_SEC_SET 32'h00000008
`define PPSG_ESCR_NSEC_SET_OFFSET 4
`define PPSG_ESCR_NSEC_SET 32'h00000010
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