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White Rabbit core collection
Commit fd467fd2 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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update wrpc testbench

parent 9211cad9
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Showing with 5332 additions and 2188 deletions
testbench/wrc_core/main_tb/functions.svh 0 → 100644
View file @ fd467fd2
`define WIRE_VHD_SV_WRFSRC(vhd_dst, sv_src) \
assign vhd_dst``_i.cyc = sv_src.cyc; \
assign vhd_dst``_i.stb = sv_src.stb; \
assign vhd_dst``_i.adr = sv_src.adr; \
assign vhd_dst``_i.dat = sv_src.dat_o; \
assign vhd_dst``_i.sel = sv_src.sel; \
assign vhd_dst``_i.we = sv_src.we; \
assign sv_src.ack = vhd_dst``_o.ack; \
assign sv_src.err = vhd_dst``_o.err; \
assign sv_src.stall = vhd_dst``_o.stall;
`define WIRE_VHD_SV_WRFSNK(sv_dst, vhd_src) \
assign sv_dst.cyc = vhd_src``_o.cyc; \
assign sv_dst.stb = vhd_src``_o.stb; \
assign sv_dst.adr = vhd_src``_o.adr; \
assign sv_dst.dat_o = vhd_src``_o.dat; \
assign sv_dst.sel = vhd_src``_o.sel; \
assign sv_dst.we = vhd_src``_o.we; \
assign vhd_src``_i.ack = sv_dst.ack; \
assign vhd_src``_i.err = sv_dst.err; \
assign vhd_src``_i.stall = sv_dst.stall;
`define WIRE_VHD_SV_WBM(vhd_dst, sv_src) \
assign vhd_dst``_o.cyc = sv_src.cyc; \
assign vhd_dst``_o.stb = sv_src.stb; \
assign vhd_dst``_o.adr = sv_src.adr; \
assign vhd_dst``_o.dat = sv_src.dat_o; \
assign vhd_dst``_o.sel = sv_src.sel; \
assign vhd_dst``_o.we = sv_src.we; \
assign sv_src.ack = vhd_dst``_i.ack; \
assign sv_src.err = vhd_dst``_i.err; \
assign sv_src.dat_i = vhd_dst``_i.dat; \
assign sv_src.stall = vhd_dst``_i.stall;
int tx_sizes[$], tx_padded[$];
//////////////////////////////////////////////////////////
task send_frames(WBPacketSource src, int n_packets);
int i, seed = 0,n1=0,n2=0;
int cur_size, dir;
EthPacket pkt, tmpl;
EthPacket to_ext[$], to_minic[$];
EthPacketGenerator gen = new;
tmpl = new;
tmpl.src = '{22,33,44,44,55,66};
tmpl.dst = '{'hff,'hff,'hff,'hff,'hff,'hff};
//tmpl.dst = '{'h01,'h1b,'h19,'h00,'h00,'h00}; // PTP dst MAC
tmpl.has_smac = 1;
tmpl.is_q = 0;
tmpl.ethertype = {'h0800};
//tmpl.ethertype = {'hdbff};
//tmpl.ethertype = {'h88f7};
//gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE /*| EthPacketGenerator::RX_OOB*/) ;
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD ) ;
gen.set_template(tmpl);
gen.set_size(1, 1500);
cur_size = 60;
dir = 1;
for(i=0;i<n_packets;i++) begin
/* switch between incrementing/decrementing */
if(cur_size == 1495)
dir = 0;
if(cur_size == 1)
dir = 1;
/* increment/decrement frame size, based on dir */
if(dir == 1)
cur_size += 1;
else
cur_size -= 1;
pkt = gen.gen(cur_size);
//pkt = gen.gen();
tx_sizes = {tx_sizes, pkt.size};
tx_padded = {tx_padded, padded_size(pkt)};
src.send(pkt);
#100us;
end
endtask
function int nopad_size(EthPacket pkt);
int i;
if(pkt.size > 64)
nopad_size = pkt.size;
else begin
nopad_size = 1;
for(i=1; i<pkt.size; i++) begin
if(pkt.payload[i]==0) break;
nopad_size = nopad_size + 1;
end
nopad_size = nopad_size + 14; //+header
end
endfunction;
function int padded_size(EthPacket pkt);
if(pkt.size < 60) padded_size = 60;
else padded_size = pkt.size;
endfunction;
function int find_pkt_size(EthPacket pkt, int start, int limit);
int i;
for(i=start; i<start+limit; i++) begin
if(pkt.size == tx_sizes[i])
return i;
end
return -1;
endfunction;
testbench/wrc_core/main_tb/main.sv
View file @ fd467fd2
......@@ -10,8 +10,15 @@
`include "wb_packet_source.svh"
`include "wb_packet_sink.svh"
`include "if_wb_link.svh"
`include "functions.svh"
`include "drivers/simdrv_minic.svh"
`include "drivers/simdrv_wr_endpoint.svh"
`include "lbk_regs.v"
//import wishbone_pkg::*;
`define BASE_SYSCON 'h20400
`define BASE_MINIC 'h20000
module main;
......@@ -20,20 +27,31 @@ module main;
wire clk_sys;
wire rst_n;
IWishboneMaster WB (
.clk_i(clk_sys),
.rst_n_i(rst_n));
IWishboneMaster #(2,16) U_ep_src (
.clk_i(clk_sys),
.rst_n_i(rst_n));
IWishboneSlave #(2,16) U_ep_snk (
.clk_i(clk_sys),
.rst_n_i(rst_n));
WBPacketSource ep_src;
WBPacketSink ep_snk;
/* WB masters */
IWishboneMaster WB_wrc (clk_sys, rst_n);
IWishboneMaster WB_ep (clk_sys, rst_n);
IWishboneMaster WB_lbk (clk_sys, rst_n);
/* WB accessors */
CWishboneAccessor acc_wrc, acc_ep, acc_lbk;
/* Fabrics */
IWishboneMaster #(2,16) WB_wrc_src (clk_sys, rst_n);
IWishboneSlave #(2,16) WB_wrc_snk (clk_sys, rst_n);
IWishboneMaster #(2,16) WB_ep_src (clk_sys, rst_n);
IWishboneSlave #(2,16) WB_ep_snk (clk_sys, rst_n);
/* Fabrics accessors */
WBPacketSource wrc_src, ep_src;
WBPacketSink wrc_snk, ep_snk;
/* VHDL package types */
//wire t_wishbone_master_out vhd_epwbm_o;
//wire t_wishbone_master_in vhd_epwbm_i;
//wire t_wrf_source_out vhd_epsrc_o;
//wire t_wrf_source_in vhd_epsrc_i;
//wire t_wrf_sink_out vhd_epsnk_o;
//wire t_wrf_sink_in vhd_epsnk_i;
tbi_clock_rst_gen
#(
......@@ -45,17 +63,34 @@ module main;
.rst_n_o(rst_n)
);
wire [7:0]phy_tx_data ;
wire phy_tx_k ;
wire phy_tx_disparity ;
wire phy_tx_enc_err ;
wire [7:0]phy_rx_data ;
wire phy_rx_rbclk ;
wire phy_rx_k ;
wire phy_rx_enc_err ;
wire [3:0]phy_rx_bitslide ;
wire phy_rst ;
wire [7:0]phy_tx_data;
wire phy_tx_k;
wire phy_tx_disparity;
wire phy_tx_enc_err;
wire [7:0]phy_rx_data;
wire phy_rx_rbclk;
wire phy_rx_k;
wire phy_rx_enc_err;
wire [3:0]phy_rx_bitslide;
wire phy_rst;
wire phy_loopen;
// set of wires between WRC and WRF_LBK
wire wrc_src_cyc;
wire wrc_src_stb;
wire [1:0] wrc_src_sel;
wire [1:0] wrc_src_adr;
wire [15:0] wrc_src_dat;
wire wrc_src_ack;
wire wrc_src_stall;
wire wrc_src_err;
wire wrc_snk_cyc;
wire wrc_snk_stb;
wire [1:0] wrc_snk_sel;
wire [1:0] wrc_snk_adr;
wire [15:0] wrc_snk_dat;
wire wrc_snk_ack;
wire wrc_snk_stall;
wire wrc_snk_err;
wr_core #(
.g_simulation (1),
......@@ -90,34 +125,53 @@ module main;
.btn1_i(1'b0),
.btn2_i(1'b0),
.ext_snk_adr_i (U_ep_src.adr[1:0]),
.ext_snk_dat_i (U_ep_src.dat_o),
.ext_snk_sel_i (U_ep_src.sel),
.ext_snk_cyc_i (U_ep_src.cyc),
//.ext_snk_adr_i (WB_wrc_src.adr[1:0]),
//.ext_snk_dat_i (WB_wrc_src.dat_o),
//.ext_snk_sel_i (WB_wrc_src.sel),
//.ext_snk_cyc_i (WB_wrc_src.cyc),
//.ext_snk_we_i (1'b1),
//.ext_snk_stb_i (WB_wrc_src.stb),
//.ext_snk_ack_o (WB_wrc_src.ack),
//.ext_snk_err_o (WB_wrc_src.err),
//.ext_snk_stall_o(WB_wrc_src.stall),
//.ext_src_adr_o (WB_wrc_snk.adr),
//.ext_src_dat_o (WB_wrc_snk.dat_i),
//.ext_src_sel_o (WB_wrc_snk.sel),
//.ext_src_cyc_o (WB_wrc_snk.cyc),
//.ext_src_stb_o (WB_wrc_snk.stb),
//.ext_src_we_o (WB_wrc_snk.we),
//.ext_src_ack_i (WB_wrc_snk.ack),
//.ext_src_err_i (WB_wrc_snk.err),
//.ext_src_stall_i(WB_wrc_snk.stall),
.ext_snk_adr_i (wrc_snk_adr),
.ext_snk_dat_i (wrc_snk_dat),
.ext_snk_sel_i (wrc_snk_sel),
.ext_snk_cyc_i (wrc_snk_cyc),
.ext_snk_we_i (1'b1),
.ext_snk_stb_i (U_ep_src.stb),
.ext_snk_ack_o (U_ep_src.ack),
.ext_snk_err_o (U_ep_src.err),
.ext_snk_stall_o(U_ep_src.stall),
.ext_src_adr_o (U_ep_snk.adr),
.ext_src_dat_o (U_ep_snk.dat_i),
.ext_src_sel_o (U_ep_snk.sel),
.ext_src_cyc_o (U_ep_snk.cyc),
.ext_src_stb_o (U_ep_snk.stb),
.ext_src_we_o (U_ep_snk.we),
.ext_src_ack_i (U_ep_snk.ack),
.ext_src_err_i (U_ep_snk.err),
.ext_src_stall_i(U_ep_snk.stall),
.wb_adr_i (WB.master.adr[31:0]),
.wb_dat_i (WB.master.dat_o),
.wb_dat_o (WB.master.dat_i),
.wb_sel_i (4'b1111),
.wb_we_i (WB.master.we),
.wb_cyc_i (WB.master.cyc),
.wb_stb_i (WB.master.stb),
.wb_ack_o (WB.master.ack),
.wb_stall_o (WB.master.stall),
.ext_snk_stb_i (wrc_snk_stb),
.ext_snk_ack_o (wrc_snk_ack),
.ext_snk_err_o (wrc_snk_err),
.ext_snk_stall_o(wrc_snk_stall),
.ext_src_adr_o (wrc_src_adr),
.ext_src_dat_o (wrc_src_dat),
.ext_src_sel_o (wrc_src_sel),
.ext_src_cyc_o (wrc_src_cyc),
.ext_src_stb_o (wrc_src_stb),
.ext_src_we_o (),
.ext_src_ack_i (wrc_src_ack),
.ext_src_err_i (wrc_src_err),
.ext_src_stall_i(wrc_src_stall),
.wb_adr_i (WB_wrc.master.adr[31:0]),
.wb_dat_i (WB_wrc.master.dat_o),
.wb_dat_o (WB_wrc.master.dat_i),
.wb_sel_i (4'b1111),
.wb_we_i (WB_wrc.master.we),
.wb_cyc_i (WB_wrc.master.cyc),
.wb_stb_i (WB_wrc.master.stb),
.wb_ack_o (WB_wrc.master.ack),
.wb_stall_o (WB_wrc.master.stall),
.phy_ref_clk_i(clk_ref),
.phy_tx_data_o(phy_tx_data),
......@@ -133,112 +187,171 @@ module main;
.phy_loopen_o(phy_lo)
);
assign phy_rx_data = phy_tx_data;
assign phy_rx_k = phy_tx_k;
wr_endpoint #(
.g_interface_mode(PIPELINED),
.g_address_granularity(BYTE),
.g_simulation (1),
.g_pcs_16bit (0),
.g_rx_buffer_size (1024),
.g_with_rx_buffer (1),
.g_with_timestamper (0),
.g_with_dpi_classifier (0),
.g_with_vlans (0),
.g_with_rtu (0))
EP (
.clk_ref_i(clk_ref),
.clk_sys_i(clk_sys),
.clk_dmtd_i(clk_ref),
.rst_n_i(rst_n),
.pps_csync_p1_i(1'b0),
.phy_sfp_tx_fault_i(1'b0),
.phy_sfp_los_i(1'b0),
.phy_rdy_i(1'b1),
.phy_ref_clk_i(clk_ref),
.phy_tx_data_o(phy_rx_data),
.phy_tx_k_o(phy_rx_k),
.phy_tx_disparity_i(phy_tx_disparity),
.phy_tx_enc_err_i(phy_tx_enc_err),
.phy_rx_data_i(phy_tx_data),
.phy_rx_clk_i(clk_ref),
.phy_rx_k_i(phy_tx_k),
.phy_rx_enc_err_i(phy_rx_enc_err),
.phy_rx_bitslide_i(phy_rx_bitslide),
.src_dat_o (WB_ep_snk.slave.dat_i),
.src_adr_o (WB_ep_snk.slave.adr),
.src_sel_o (WB_ep_snk.slave.sel),
.src_cyc_o (WB_ep_snk.slave.cyc),
.src_stb_o (WB_ep_snk.slave.stb),
.src_we_o (WB_ep_snk.slave.we),
.src_stall_i(WB_ep_snk.slave.stall),
.src_ack_i (WB_ep_snk.slave.ack),
.src_err_i (1'b0),
.snk_dat_i (WB_ep_src.master.dat_o),
.snk_adr_i (WB_ep_src.master.adr),
.snk_sel_i (WB_ep_src.master.sel),
.snk_cyc_i (WB_ep_src.master.cyc),
.snk_stb_i (WB_ep_src.master.stb),
.snk_we_i (WB_ep_src.master.we),
.snk_stall_o(WB_ep_src.master.stall),
.snk_ack_o (WB_ep_src.master.ack),
.snk_err_o (WB_ep_src.master.err),
.wb_cyc_i (WB_ep.master.cyc),
.wb_stb_i (WB_ep.master.stb),
.wb_we_i (WB_ep.master.we),
.wb_sel_i (WB_ep.master.sel),
.wb_adr_i (WB_ep.master.adr[7:0]),
.wb_dat_i (WB_ep.master.dat_o),
.wb_dat_o (WB_ep.master.dat_i),
.wb_ack_o (WB_ep.master.ack),
.wb_stall_o(WB_ep.master.stall));
wrf_loopback #(
.g_interface_mode(PIPELINED),
.g_address_granularity(BYTE))
WRF_LBK (
.clk_sys_i(clk_sys),
.rst_n_i(rst_n),
.snk_cyc_i(wrc_src_cyc),
.snk_stb_i(wrc_src_stb),
.snk_we_i (1'b1),
.snk_sel_i(wrc_src_sel),
.snk_adr_i(wrc_src_adr),
.snk_dat_i(wrc_src_dat),
.snk_ack_o(wrc_src_ack),
.snk_stall_o(wrc_src_stall),
.src_cyc_o(wrc_snk_cyc),
.src_stb_o(wrc_snk_stb),
.src_we_o (),
.src_sel_o(wrc_snk_sel),
.src_adr_o(wrc_snk_adr),
.src_dat_o(wrc_snk_dat),
.src_ack_i(wrc_snk_ack),
.src_stall_i(wrc_snk_stall),
.wb_cyc_i(WB_lbk.master.cyc),
.wb_stb_i(WB_lbk.master.stb),
.wb_we_i (WB_lbk.master.we),
.wb_sel_i(4'b1111),
.wb_adr_i(WB_lbk.master.adr),
.wb_dat_i(WB_lbk.master.dat_o),
.wb_dat_o(WB_lbk.master.dat_i),
.wb_ack_o(WB_lbk.master.ack),
.wb_stall_o(WB_lbk.master.stall));
/* Wire together VHD and SV types */
//`WIRE_VHD_SV_WBM(vhd_epwbm, WB_ep);
//`WIRE_VHD_SV_WRFSNK(WB_ep_snk, vhd_epsrc);
//`WIRE_VHD_SV_WRFSRC(vhd_epsnk, WB_ep_src);
assign phy_tx_disparity = 0;
assign phy_tx_enc_err = 0;
assign phy_rx_enc_err = 0;
int tx_sizes[$], tx_padded[$];
//////////////////////////////////////
task send_frames(WBPacketSource src, int n_packets);
int i, seed = 0,n1=0,n2=0;
int cur_size, dir;
EthPacket pkt, tmpl;
EthPacket to_ext[$], to_minic[$];
EthPacketGenerator gen = new;
tmpl = new;
tmpl.src = '{1,2,3,4,5,6};
tmpl.dst = '{'hff,'hff,'hff,'hff,'hff,'hff};
//tmpl.dst = '{'h01,'h1b,'h19,'h00,'h00,'h00}; // PTP dst MAC
tmpl.has_smac = 1;
tmpl.is_q = 0;
//tmpl.ethertype = {'h0800};
tmpl.ethertype = {'hdbff};
//tmpl.ethertype = {'h88f7};
//gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE /*| EthPacketGenerator::RX_OOB*/) ;
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD ) ;
gen.set_template(tmpl);
gen.set_size(1, 1500);
cur_size = 0;
dir = 1;
for(i=0;i<n_packets;i++) begin
/* switch between incrementing/decrementing */
if(cur_size == 1495)
dir = 0;
if(cur_size == 1)
dir = 1;
/* increment/decrement frame size, based on dir */
if(dir == 1)
cur_size += 1;
else
cur_size -= 1;
pkt = gen.gen(cur_size);
//pkt = gen.gen();
tx_sizes = {tx_sizes, pkt.size};
tx_padded = {tx_padded, padded_size(pkt)};
src.send(pkt);
end
endtask
function int nopad_size(EthPacket pkt);
int i;
if(pkt.size > 64)
nopad_size = pkt.size;
else begin
nopad_size = 1;
for(i=1; i<pkt.size; i++) begin
if(pkt.payload[i]==0) break;
nopad_size = nopad_size + 1;
end
nopad_size = nopad_size + 14; //+header
end
endfunction;
function int padded_size(EthPacket pkt);
if(pkt.size < 60) padded_size = 60;
else padded_size = pkt.size;
endfunction;
function int find_pkt_size(EthPacket pkt, int start, int limit);
int i;
for(i=start; i<start+limit; i++) begin
if(pkt.size == tx_sizes[i])
return i;
end
return -1;
endfunction;
//////////////////////////////////////
// DPI import exports
//////////////////////////////////////
//export "DPI-C" task SV_minic_write;
//export "DPI-C" task SV_minic_read;
//import "DPI-C" context task C_minic_rx_frame();
//import "DPI-C" context task C_minic_init();
//task SV_minic_write(uint32_t addr, uint32_t val);
// acc.write(`BASE_MINIC + addr, val);
//endtask
//task SV_minic_read(uint32_t addr, output uint32_t val);
// uint64_t val64;
// acc.read(`BASE_MINIC + addr, val64);
// val = val64;
// //return val64;
//endtask
//////////////////////////////////////
initial begin
CWishboneAccessor acc;
//CWishboneAccessor acc_wrc;
CSimDrv_WR_Endpoint ep_drv;
@(posedge rst_n);
repeat(3) @(posedge clk_sys);
#1us;
acc = WB.get_accessor();
acc.set_mode(PIPELINED);
WB.settings.cyc_on_stall = 1;
acc_wrc = WB_wrc.get_accessor();
acc_wrc.set_mode(PIPELINED);
WB_wrc.settings.cyc_on_stall = 1;
acc_ep = WB_ep.get_accessor();
WB_ep.settings.cyc_on_stall = 1;
acc_ep.set_mode(PIPELINED);
ep_drv = new(acc_ep, 0);
ep_drv.init(0);
ep_src = new(U_ep_src.get_accessor());
U_ep_src.settings.cyc_on_stall = 1;
wrc_src = new(WB_wrc_src.get_accessor());
WB_wrc_src.settings.cyc_on_stall = 1;
ep_src = new(WB_ep_src.get_accessor());
WB_ep_src.settings.cyc_on_stall = 1;
#1us
acc.write(`BASE_SYSCON + `ADDR_SYSC_RSTR, 'hdeadbee | `SYSC_RSTR_RST);
acc_wrc.write(`BASE_SYSCON + `ADDR_SYSC_RSTR, 'hdeadbee | `SYSC_RSTR_RST);
#1us;
acc.write(`BASE_SYSCON + `ADDR_SYSC_RSTR, 'hdeadbee );
acc_wrc.write(`BASE_SYSCON + `ADDR_SYSC_RSTR, 'hdeadbee );
#400us;
#1400us;
tx_sizes = {};
//NOW LET'S SEND SOME FRAMES
send_frames(ep_src, 3000);
//send_frames(wrc_src, 3000);
send_frames(ep_src, 20);
end
......@@ -247,36 +360,79 @@ module main;
int i = 0, correct = 0, j;
int drop_first = 1;
int size_pos;
U_ep_snk.settings.gen_random_stalls = 1;
ep_snk = new(U_ep_snk.get_accessor());
CSimDrv_Minic minic;
EthPacket rxp;
int prev_size=0;
uint64_t val64;
WB_wrc_snk.settings.gen_random_stalls = 1;
wrc_snk = new(WB_wrc_snk.get_accessor());
WB_ep_snk.settings.gen_random_stalls = 0;
ep_snk = new(WB_ep_snk.get_accessor());
acc_lbk = WB_lbk.get_accessor();
acc_lbk.set_mode(PIPELINED);
WB_lbk.settings.cyc_on_stall = 1;
#1us;
acc_lbk.write(`ADDR_LBK_MCR, `LBK_MCR_ENA);
#1200us;
//minic = new('h1000, acc_wrc, `BASE_MINIC, acc_wrc, 'h4d98);
//minic.init();
while(1) begin
ep_snk.recv(pkt);
size_pos = find_pkt_size(pkt, i, 5);
assert (pkt.size == tx_padded[i] && nopad_size(pkt) == tx_sizes[i]) begin
correct = correct + 1;
$display("--> recv: size=%4d, nopad=%4d", pkt.size, nopad_size(pkt));
end
else assert (pkt.error == 1'b1 || (pkt.size == tx_padded[size_pos] && nopad_size(pkt) == tx_sizes[size_pos])) begin
if(size_pos == -1)
$warning("(%1d) Lost frame with size: %4d", pkt.error, tx_sizes[i]);
for(j=i; j<size_pos; j++)
$warning("(%1d) Lost frame with size: %4d", pkt.error, tx_sizes[j]);
if(pkt.error == 1'b0) i = size_pos;
correct = correct + 1;
$display("--> recv: size=%4d, nopad=%4d", pkt.size, nopad_size(pkt));
end
else begin
$display("Frame dump:");
for(j=0; j<pkt.size-14; j++) begin
$write("0x%02X ", pkt.payload[j]);
end
$fatal("(%1d) Size does not match: pkt.size=%4d, nopad.size=%4d, padded=%4d,
sizes=%4d", pkt.error, pkt.size, nopad_size(pkt), tx_padded[i], tx_sizes[i]);
end
i = i+1;
#1us;
ep_snk.recv(pkt);
$display("--> recv: size=%4d", pkt.size);
acc_lbk.read(`ADDR_LBK_RCV_CNT, val64);
$display("rcv_cnt: %d", val64);
acc_lbk.read(`ADDR_LBK_DRP_CNT, val64);
$display("drp_cnt: %d", val64);
acc_lbk.read(`ADDR_LBK_FWD_CNT, val64);
$display("fwd_cnt: %d", val64);
//acc_lbk.write(`ADDR_LBK_MCR, `LBK_MCR_CLR);
//acc_lbk.write(`ADDR_LBK_MCR, 0);
//minic.run();
//if(minic.poll()) begin
// minic.recv(rxp);
// $display("got frame size: %d; diff: %d", rxp.size, rxp.size - prev_size);
// prev_size = rxp.size;
//end
//wrc_snk.recv(pkt);
//size_pos = find_pkt_size(pkt, i, 5);
//assert (pkt.size == tx_padded[i] && nopad_size(pkt) == tx_sizes[i]) begin
// correct = correct + 1;
// $display("--> recv: size=%4d, nopad=%4d", pkt.size, nopad_size(pkt));
//end
//else assert (pkt.error == 1'b1 || (pkt.size == tx_padded[size_pos] && nopad_size(pkt) == tx_sizes[size_pos])) begin
// if(size_pos == -1)
// $warning("(%1d) Lost frame with size: %4d", pkt.error, tx_sizes[i]);
// for(j=i; j<size_pos; j++)
// $warning("(%1d) Lost frame with size: %4d", pkt.error, tx_sizes[j]);
// if(pkt.error == 1'b0) i = size_pos;
// correct = correct + 1;
// $display("--> recv: size=%4d, nopad=%4d", pkt.size, nopad_size(pkt));
//end
//else begin
// $display("Frame dump:");
// for(j=0; j<pkt.size-14; j++) begin
// $write("0x%02X ", pkt.payload[j]);
// end
// $fatal("(%1d) Size does not match: pkt.size=%4d, nopad.size=%4d, padded=%4d,
// sizes=%4d", pkt.error, pkt.size, nopad_size(pkt), tx_padded[i], tx_sizes[i]);
//end
//i = i+1;
end
end
/////////////////// DPI
//always @posedge(wb_read_req)
//begin
// wb_read_done = 1'b0;
// acc.read(`BASE_MINIC + wb_read_adr, wb_read_val);
// wb_read_done = 1'b1;
//end
//////////////////////////
endmodule // main
testbench/wrc_core/main_tb/run.do
View file @ fd467fd2
#vlog -dpiheader dpi/minic_dpi.h -sv main.sv +incdir+"." +incdir+../../../sim
vlog -sv main.sv +incdir+"." +incdir+../../../sim
make -f Makefile
#vsim -sv_lib dpi/minic -L unisim -t 10fs work.main -voptargs="+acc"
vsim -L unisim -t 10fs work.main -voptargs="+acc"
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 25ms
run 200ms
wave zoomfull
radix -hexadecimal
testbench/wrc_core/main_tb/sw/wrc.ram
View file @ fd467fd2
This source diff could not be displayed because it is too large. You can view the blob instead.
testbench/wrc_core/main_tb/wave.do
View file @ fd467fd2
......@@ -4,152 +4,112 @@ add wave -noupdate /main/DUT/PERIPH/rst_n_i
add wave -noupdate /main/DUT/rst_net_n
add wave -noupdate /main/DUT/rst_wrc_n
add wave -noupdate /main/DUT/clk_sys_i
add wave -noupdate -group WR-CORE /main/DUT/wb_adr_i
add wave -noupdate -group WR-CORE /main/DUT/wb_dat_i
add wave -noupdate -group WR-CORE /main/DUT/wb_dat_o
add wave -noupdate -group WR-CORE /main/DUT/wb_sel_i
add wave -noupdate -group WR-CORE /main/DUT/wb_we_i
add wave -noupdate -group WR-CORE /main/DUT/wb_cyc_i
add wave -noupdate -group WR-CORE /main/DUT/wb_stb_i
add wave -noupdate -group WR-CORE /main/DUT/wb_ack_o
add wave -noupdate -group WR-CORE /main/DUT/wb_err_o
add wave -noupdate -group WR-CORE /main/DUT/wb_rty_o
add wave -noupdate -group WR-CORE /main/DUT/wb_stall_o
add wave -noupdate -expand -group Endpoint -group {FABRIC IF} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/snk_dat_i
add wave -noupdate -expand -group Endpoint -group {FABRIC IF} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/snk_adr_i
add wave -noupdate -expand -group Endpoint -group {FABRIC IF} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/snk_sel_i
add wave -noupdate -expand -group Endpoint -group {FABRIC IF} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/snk_cyc_i
add wave -noupdate -expand -group Endpoint -group {FABRIC IF} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/snk_stb_i
add wave -noupdate -expand -group Endpoint -group {FABRIC IF} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/snk_we_i
add wave -noupdate -expand -group Endpoint -group {FABRIC IF} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/snk_stall_o
add wave -noupdate -expand -group Endpoint -group {FABRIC IF} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/snk_ack_o
add wave -noupdate -expand -group Endpoint -group {FABRIC IF} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/snk_err_o
add wave -noupdate -expand -group Endpoint -group {FABRIC IF} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/snk_rty_o
add wave -noupdate -expand -group Endpoint -expand -group {FABRIC RX} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/src_dat_o
add wave -noupdate -expand -group Endpoint -expand -group {FABRIC RX} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/src_adr_o
add wave -noupdate -expand -group Endpoint -expand -group {FABRIC RX} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/src_sel_o
add wave -noupdate -expand -group Endpoint -expand -group {FABRIC RX} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/src_cyc_o
add wave -noupdate -expand -group Endpoint -expand -group {FABRIC RX} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/src_stb_o
add wave -noupdate -expand -group Endpoint -expand -group {FABRIC RX} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/src_we_o
add wave -noupdate -expand -group Endpoint -expand -group {FABRIC RX} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/src_stall_i
add wave -noupdate -expand -group Endpoint -expand -group {FABRIC RX} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/src_ack_i
add wave -noupdate -expand -group Endpoint -expand -group {FABRIC RX} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/src_err_i
add wave -noupdate -expand -group Endpoint -expand -group {HEADER PROCESSOR} -height 16 /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/state
add wave -noupdate -expand -group Endpoint -expand -group {HEADER PROCESSOR} -radix unsigned /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/counter
add wave -noupdate -expand -group Endpoint -expand -group {HEADER PROCESSOR} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/sof_p1
add wave -noupdate -expand -group Endpoint -expand -group {HEADER PROCESSOR} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/sof_reg
add wave -noupdate -expand -group Endpoint -expand -group {HEADER PROCESSOR} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/eof_p1
add wave -noupdate -expand -group Endpoint -expand -group {HEADER PROCESSOR} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/tx_en
add wave -noupdate -expand -group Endpoint -expand -group {HEADER PROCESSOR} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/bitsel_d
add wave -noupdate -expand -group Endpoint -expand -group {HEADER PROCESSOR} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/pcs_busy_i
add wave -noupdate -expand -group Endpoint -expand -group {HEADER PROCESSOR} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/src_dreq_i
add wave -noupdate -expand -group Endpoint -group {TX PATH} -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe(0)
add wave -noupdate -expand -group Endpoint -group {TX PATH} -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe(1)
add wave -noupdate -expand -group Endpoint -group {TX PATH} -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe(2)
add wave -noupdate -expand -group Endpoint -group {TX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe(3)
add wave -noupdate -expand -group Endpoint -group {TX PATH} -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe(4)
add wave -noupdate -expand -group Endpoint -group {TX PATH} -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Path/dreq_pipe
add wave -noupdate -expand -group Endpoint -expand -group TX_CRC -height 16 /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/state
add wave -noupdate -expand -group Endpoint -expand -group TX_CRC /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/in_payload
add wave -noupdate -expand -group Endpoint -expand -group TX_PCS -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/pcs_fab_i
add wave -noupdate -expand -group Endpoint -expand -group TX_PCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/pcs_error_o
add wave -noupdate -expand -group Endpoint -expand -group TX_PCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/pcs_busy_o
add wave -noupdate -expand -group Endpoint -expand -group TX_PCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/pcs_dreq_o
add wave -noupdate -expand -group Endpoint -expand -group TX_PCS -height 16 /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/tx_state
add wave -noupdate -expand -group Endpoint -expand -group TX_PCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/fifo_almost_full
add wave -noupdate -expand -group Endpoint -group RX_PCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/pcs_busy_o
add wave -noupdate -expand -group Endpoint -group RX_PCS -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/pcs_fab_o
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(0)
add wave -noupdate -expand -group {RX PATH} -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(1)
add wave -noupdate -expand -group {RX PATH} -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(2)
add wave -noupdate -expand -group {RX PATH} -expand -group PFilter /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/rst_n_rx_i
add wave -noupdate -expand -group {RX PATH} -expand -group PFilter /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/drop_o
add wave -noupdate -expand -group {RX PATH} -expand -group PFilter /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/pclass_o
add wave -noupdate -expand -group {RX PATH} -expand -group PFilter /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/done_int
add wave -noupdate -expand -group {RX PATH} -expand -group PFilter /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/done_o
add wave -noupdate -expand -group {RX PATH} -expand -group PFilter /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/regs
add wave -noupdate -expand -group {RX PATH} -expand -group PFilter /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/pfcr0_enable_rxclk
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(3)
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/dreq_pipe(3)
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/full_o
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/empty_o
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/almostfull_o
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/fifo_we
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/rx_rdreq
add wave -noupdate -expand -group {RX PATH} -radix unsigned /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rd_count_o
add wave -noupdate -expand -group {RX PATH} -radix unsigned /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/wr_count_o
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(4)
add wave -noupdate -expand -group {RX PATH} -height 16 /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Insert_OOB/state
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/dreq_pipe(4)
add wave -noupdate -expand -group {RX PATH} -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(5)
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/dreq_pipe(5)
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_crc_size_checker/size_check_ok
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_crc_size_checker/crc_match
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_crc_size_checker/q_bytesel
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_crc_size_checker/oob_in
add wave -noupdate -expand -group {RX PATH} -height 16 /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_crc_size_checker/state
add wave -noupdate -expand -group {RX PATH} -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(6)
add wave -noupdate -expand -group {RX PATH} -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(7)
add wave -noupdate -expand -group {RX PATH} -radix unsigned /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/level_o
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/empty_o
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/full_o
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/almost_empty_o
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/almost_full_o
add wave -noupdate -expand -group {RX PATH} -radix unsigned /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/count_o
add wave -noupdate -expand -group {RX PATH} -expand -group rx_buf -height 16 /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/state
add wave -noupdate -expand -group {RX PATH} -expand -group rx_buf /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/in_prev_addr
add wave -noupdate -expand -group {RX PATH} -expand -group rx_buf /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/q_in
add wave -noupdate -expand -group {RX PATH} -expand -group rx_buf /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/q_in_valid
add wave -noupdate -expand -group {RX PATH} -expand -group rx_buf /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/q_drop
add wave -noupdate -expand -group {RX PATH} -expand -group rx_buf /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/U_Inferred_FIFO/we_int
add wave -noupdate -expand -group {RX PATH} -expand -group rx_buf -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/fab_to_encode
add wave -noupdate -expand -group {RX PATH} -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(8)
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/dreq_pipe(8)
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Gen_Status/mbuf_valid_i
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Gen_Status/mbuf_drop_i
add wave -noupdate -expand -group {RX PATH} /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Gen_Status/mbuf_is_pause_i
add wave -noupdate -expand -group {RX PATH} -height 16 /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Gen_Status/state
add wave -noupdate -expand -group {RX PATH} -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(9)
add wave -noupdate /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_RX_Wishbone_Master/snk_dreq_o
add wave -noupdate /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_RX_Wishbone_Master/sof_reg
add wave -noupdate -height 16 /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_RX_Wishbone_Master/state
add wave -noupdate -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_RX_Wishbone_Master/src_wb_o
add wave -noupdate -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_RX_Wishbone_Master/src_wb_i
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/clk_sys_i
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/clk_rx_i
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/regs_i.pfcr0_enable_o
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/pfilter_drop
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_pf_drop
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_valid
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_full
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_rd
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_match_buff/U_match_buffer/do_write
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_match_buff/U_match_buffer/pointer
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_match_buff/U_match_buffer/pointer_zero
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_match_buff/U_match_buffer/pointer_full
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_match_buff/U_match_buffer/empty
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_match_buff/U_match_buffer/valid_count
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_match_buff/U_match_buffer/we_i
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_match_buff/U_match_buffer/rd_i
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_match_buff/U_match_buffer/gen_sregs(2)/U_SRLx/gen_srl32/U_SRLC32/A
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_match_buff/U_match_buffer/gen_sregs(2)/U_SRLx/gen_srl32/U_SRLC32/D
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_match_buff/U_match_buffer/gen_sregs(2)/U_SRLx/gen_srl32/U_SRLC32/Q
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_match_buff/U_match_buffer/gen_sregs(2)/U_SRLx/gen_srl32/U_SRLC32/CLK
add wave -noupdate -expand -group MBUF /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_match_buff/U_match_buffer/gen_sregs(2)/U_SRLx/gen_srl32/U_SRLC32/CE
add wave -noupdate -expand -group MBUF -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_match_buff/U_match_buffer/gen_sregs(2)/U_SRLx/gen_srl32/U_SRLC32/SHIFT_REG
add wave -noupdate -group FMux -expand /main/DUT/U_WBP_Mux/ep_src_o
add wave -noupdate -group FMux /main/DUT/U_WBP_Mux/ep_src_i
add wave -noupdate -group FMux /main/DUT/U_WBP_Mux/ep_snk_o
add wave -noupdate -group FMux -expand /main/DUT/U_WBP_Mux/ep_snk_i
add wave -noupdate -group FMux /main/DUT/U_WBP_Mux/mux_src_o
add wave -noupdate -group FMux /main/DUT/U_WBP_Mux/mux_src_i
add wave -noupdate -group FMux /main/DUT/U_WBP_Mux/mux_snk_o
add wave -noupdate -group FMux -expand -subitemconfig {/main/DUT/U_WBP_Mux/mux_snk_i(1) -expand /main/DUT/U_WBP_Mux/mux_snk_i(0) -expand} /main/DUT/U_WBP_Mux/mux_snk_i
add wave -noupdate -group FMux /main/DUT/U_WBP_Mux/mux_class_i
add wave -noupdate -group Minic /main/DUT/MINI_NIC/src_o
add wave -noupdate -group Minic /main/DUT/MINI_NIC/src_i
add wave -noupdate -group Minic /main/DUT/MINI_NIC/snk_o
add wave -noupdate -group Minic /main/DUT/MINI_NIC/snk_i
add wave -noupdate -group Minic /main/DUT/MINI_NIC/U_Wrapped_Minic/nrx_avail
add wave -noupdate -group Minic /main/DUT/MINI_NIC/U_Wrapped_Minic/nrx_bufstart
add wave -noupdate -group Minic /main/DUT/MINI_NIC/U_Wrapped_Minic/nrx_bufsize
add wave -noupdate -group Minic /main/DUT/MINI_NIC/U_Wrapped_Minic/nrx_mem_a_saved
add wave -noupdate -group Minic /main/DUT/MINI_NIC/U_Wrapped_Minic/nrx_buf_full
add wave -noupdate -group Minic /main/DUT/MINI_NIC/U_Wrapped_Minic/nrx_valid
add wave -noupdate -group Minic -expand /main/DUT/MINI_NIC/wb_i
add wave -noupdate -group Minic -expand /main/DUT/MINI_NIC/wb_o
add wave -noupdate -expand -group EP_INT -expand /main/DUT/U_Endpoint/snk_i
add wave -noupdate -expand -group EP_INT -expand /main/DUT/U_Endpoint/src_o
add wave -noupdate -expand -group EP_INT -group TX_PCS -expand /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/pcs_fab_i
add wave -noupdate -expand -group EP_INT -group RX_PCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/pcs_fab_o
add wave -noupdate -expand -group EP_INT -expand -group CRC -height 16 /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_crc_size_checker/state
add wave -noupdate -expand -group EP_INT -expand -group CRC /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_crc_size_checker/sreg_enable
add wave -noupdate -expand -group EP_INT -expand -group CRC /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_crc_size_checker/q_data
add wave -noupdate -expand -group EP_INT -expand -group CRC /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_crc_size_checker/q_dvalid_out
add wave -noupdate -expand -group EP_INT -expand -group CRC /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_crc_size_checker/q_dvalid_in
add wave -noupdate -expand -group EP_INT -expand -group CRC /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_crc_size_checker/qfull
add wave -noupdate -group ext_snk /main/DUT/ext_snk_adr_i
add wave -noupdate -group ext_snk /main/DUT/ext_snk_dat_i
add wave -noupdate -group ext_snk /main/DUT/ext_snk_sel_i
add wave -noupdate -group ext_snk /main/DUT/ext_snk_cyc_i
add wave -noupdate -group ext_snk /main/DUT/ext_snk_stb_i
add wave -noupdate -group ext_snk /main/DUT/ext_snk_ack_o
add wave -noupdate -group ext_snk /main/DUT/ext_snk_err_o
add wave -noupdate -group ext_snk /main/DUT/ext_snk_stall_o
add wave -noupdate -group ext_src /main/DUT/ext_src_adr_o
add wave -noupdate -group ext_src /main/DUT/ext_src_dat_o
add wave -noupdate -group ext_src /main/DUT/ext_src_sel_o
add wave -noupdate -group ext_src /main/DUT/ext_src_cyc_o
add wave -noupdate -group ext_src /main/DUT/ext_src_stb_o
add wave -noupdate -group ext_src /main/DUT/ext_src_ack_i
add wave -noupdate -group ext_src /main/DUT/ext_src_err_i
add wave -noupdate -group ext_src /main/DUT/ext_src_stall_i
add wave -noupdate -expand -group EP_EXT -expand -group src /main/EP/src_cyc_o
add wave -noupdate -expand -group EP_EXT -expand -group src /main/EP/src_stb_o
add wave -noupdate -expand -group EP_EXT -expand -group src /main/EP/src_sel_o
add wave -noupdate -expand -group EP_EXT -expand -group src /main/EP/src_adr_o
add wave -noupdate -expand -group EP_EXT -expand -group src /main/EP/src_dat_o
add wave -noupdate -expand -group EP_EXT -expand -group src /main/EP/src_stall_i
add wave -noupdate -expand -group EP_EXT -expand -group src /main/EP/src_ack_i
add wave -noupdate -expand -group EP_EXT -expand -group src /main/EP/src_err_i
add wave -noupdate -expand -group EP_EXT -expand -group snk /main/EP/snk_cyc_i
add wave -noupdate -expand -group EP_EXT -expand -group snk /main/EP/snk_stb_i
add wave -noupdate -expand -group EP_EXT -expand -group snk /main/EP/snk_sel_i
add wave -noupdate -expand -group EP_EXT -expand -group snk /main/EP/snk_adr_i
add wave -noupdate -expand -group EP_EXT -expand -group snk /main/EP/snk_dat_i
add wave -noupdate -expand -group EP_EXT -expand -group snk /main/EP/snk_stall_o
add wave -noupdate -expand -group EP_EXT -expand -group snk /main/EP/snk_ack_o
add wave -noupdate -expand -group EP_EXT -expand -group snk /main/EP/snk_err_o
add wave -noupdate -expand -group EP_EXT -expand -group snk /main/EP/snk_rty_o
add wave -noupdate -expand -group EP_EXT -group TX_PCS /main/EP/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/pcs_fab_i
add wave -noupdate -expand -group EP_EXT -group RX_PCS -expand /main/EP/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/pcs_fab_o
add wave -noupdate -expand -group EP_EXT -expand -group RX_PATH -expand -subitemconfig {/main/EP/U_Rx_Path/fab_pipe(4) -expand /main/EP/U_Rx_Path/fab_pipe(5) -expand} /main/EP/U_Rx_Path/fab_pipe
add wave -noupdate -expand -group EP_EXT -expand -group RX_PATH /main/EP/U_Rx_Path/dreq_pipe
add wave -noupdate -expand -group EP_EXT -expand -group RX_PATH -expand -group CRC -height 16 /main/EP/U_Rx_Path/U_crc_size_checker/state
add wave -noupdate -expand -group EP_EXT -expand -group RX_PATH -expand -group CRC -expand /main/EP/U_Rx_Path/U_crc_size_checker/q_data
add wave -noupdate -expand -group EP_EXT -expand -group RX_PATH -expand -group CRC /main/EP/U_Rx_Path/U_crc_size_checker/sreg_enable
add wave -noupdate -expand -group EP_EXT -expand -group RX_PATH -expand -group CRC /main/EP/U_Rx_Path/U_crc_size_checker/q_dvalid_out
add wave -noupdate -expand -group EP_EXT -expand -group RX_PATH -expand -group CRC /main/EP/U_Rx_Path/U_crc_size_checker/q_dvalid_in
add wave -noupdate -expand -group EP_EXT -expand -group RX_PATH -expand -group CRC /main/EP/U_Rx_Path/U_crc_size_checker/qfull
add wave -noupdate -group WB /main/EP/wb_cyc_i
add wave -noupdate -group WB /main/EP/wb_stb_i
add wave -noupdate -group WB /main/EP/wb_we_i
add wave -noupdate -group WB /main/EP/wb_sel_i
add wave -noupdate -group WB /main/EP/wb_adr_i
add wave -noupdate -group WB /main/EP/wb_dat_i
add wave -noupdate -group WB /main/EP/wb_dat_o
add wave -noupdate -group WB /main/EP/wb_ack_o
add wave -noupdate -group WB /main/EP/wb_stall_o
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/clk_sys_i
add wave -noupdate -expand -group LBK -expand /main/WRF_LBK/X_LOOPBACK/wb_i
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/wb_o
add wave -noupdate -expand -group LBK -height 16 /main/WRF_LBK/X_LOOPBACK/lbk_rxfsm
add wave -noupdate -expand -group LBK -height 16 /main/WRF_LBK/X_LOOPBACK/lbk_txfsm
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/wrf_snk_i
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/wrf_snk_o
add wave -noupdate -expand -group LBK -expand /main/WRF_LBK/X_LOOPBACK/wrf_src_o
add wave -noupdate -expand -group LBK -expand /main/WRF_LBK/X_LOOPBACK/wrf_src_i
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/rcv_cnt
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/drp_cnt
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/fwd_cnt
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/ack_cnt
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/fsize
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/txsize
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/tx_cnt
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/ffifo_empty
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/ffifo_full
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/frame_wr
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/frame_rd
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/frame_in
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/frame_out
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/sfifo_empty
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/sfifo_full
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/fsize_wr
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/fsize_rd
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/fsize_in
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/fsize_out
add wave -noupdate -expand -group LBK /main/WRF_LBK/X_LOOPBACK/regs_fromwb.mcr_ena_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {9719712580 fs} 0}
configure wave -namecolwidth 209
WaveRestoreCursors {{Cursor 2} {1607388000000 fs} 1}
configure wave -namecolwidth 204
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
......@@ -163,4 +123,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {67940302500 fs}
WaveRestoreZoom {0 fs} {8282223600 ps}
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