When WR PTP Core is set in GrandMaster mode it aligns its nanosecond
counter to 1-PPS and 10MHz coming from external source. When user wants
to set seconds counter to a desired value, the nanosecond counter was
also set (zeroed) causing additional (random) offset to the external
source.

Conflicts:
	modules/wr_softpll_ng/wr_softpll_ng.vhd

Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>

Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>

Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>

Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>

This had nothing to do with WR, wasn't used here, and is now removed.

This may fix the WRs locking offsets issue & save a lot of FPGA resources.
Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>

also, the datasheet says our new flash chips are only good to 33MHz
with slow reads. change quartus fpga load config to 20MHz (not 40).

bugfixes

wr_core: adapted for multichannel SoftPLL. Added SPLL channel phase detector mode and debug FIFO enable generic parameters. Updated tm_aux_lock_en, tm_aux_locked, tm_dac_wr to support multiple aux clocks correctly

wr_softpll_ng: choice between Bang-Bang and DDMTD channels. Made debug FIFO optional in wbgen2 core (new wbgen2 required). Dynamic reconfiguration of BB dividers/gating

Conflicts:

	modules/wr_softpll_ng/spll_wb_slave.vhd
	modules/wr_softpll_ng/spll_wbgen2_pkg.vhd

Conflicts:

	Manifest.py
	modules/wr_si57x_interface/si570_if_wb.vhd
	modules/wr_si57x_interface/si570_if_wb.wb
	modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
	modules/wr_si57x_interface/wr_si57x_interface.vhd

When WR starts up on a node, the first thing it does is kill its link.
Previously on Altera we ignored attempts to reset the link and thus
the switch never sees the link go down. It seems this matters.

The autonegotiation state machine uses an_rx_val in the sys clock domain.
The rx pcs passes the an_rx_val to the sys domain using a handshake.
Unfortunately, the value can change even after the handshake goes high.
On Altera, this led to the autonegotiation state machine entering state "0".
... from which it would never leave and the link stayed dead forever.

On Altera platforms this bug manifests as the minic failing to TX packets
correctly and the whole PTP state machine grinding to a halt.

This was already fixed in the 16bit version.