- 09 Aug, 2019 1 commit
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li hongming authored
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- 22 Jan, 2019 3 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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li hongming authored
The UG382 of Spartan-6 says that the PLLIN of BUFPLL should come from PLL (CLKOUT0/1) or BUFG. "Banks 1, 3, 4, and 5 can optionally be driven by a BUFG (O) when using ENABLE_SYNC (FALSE)." I've tried to modify the setting of ENABLE_SYNC for oserdes_4_to_1/bufpll, but the 10MHz output is still missing. So I have to change the setting of "cmp_sys_clk_pll" to make the 500MHz come from CLKOUT1 and clk_ref come from CLKOUT2.
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- 21 Jan, 2019 20 commits
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li hongming authored
change the function of LEDs: the front end LEDs display the status of link and sync. the on-board LEDS display the act of link and PPS.
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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li hongming authored
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li hongming authored
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Grzegorz Daniluk authored
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li hongming authored
Solve compile bug in ucf file.
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li hongming authored
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li hongming authored
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li hongming authored
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li hongming authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Vraliens authored
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Vraliens authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
This reverts commit 21c67bc8. DCM is much more jittery than PLL_BASE: DCM_SP: 125MHz -> 62.5MHz: pk-to-pk jitter: 300ps 125MHz -> 125MHz: pk-to-pk jitter: 200ps 20MHz -> 62.5MHz: pk-to-pk jitter: 1772ps (!!!!) PLL_BASE: 125MHz -> 62.5MHz: pk-to-pk jitter: 185ps 125MHz-> 125MHz: pk-to-pk jitter 161ps 20MHz -> 62.5MHz: pk-to-pk jitter 417ps
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- 03 Dec, 2018 8 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
syn: remove Makefiles, they are auto-generated and contain paths that are not exportable to other users (such as the location of the Xilinx ISE tools)
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Dimitris Lampridis authored
This allows to use the same top level vhd for different synthesis targets. Example, we can use the spec_ref_design from top/ in two different syn/, one for a SPEC45T and another one for a SPEC150T.
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Dimitris Lampridis authored
hdl: bump general-cores, vme64x-core and gn4124-core to latest version in preparation for updating the SPEC and SVEC reference designs
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Dimitris Lampridis authored
Every clock management block in Spartan-6 has 2xDCM and 1xPLL. PLLs are therefore a scarcer resource and should be preserved for user applications whenever possible. In this case, it is very much possible to generate the necessary clocks via DCMs. Furthermore, we expose the unused CLKFX output of one of the DCMs (along with a generic to configure the multiplication/division factors), in case it can be used by the user application.
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Dimitris Lampridis authored
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Dimitris Lampridis authored
This guarantees that the 125MHz ref clock and the 62.5MHz system clock will be phase aligned. (This only affects g_fpga_family = spartan6, when g_use_default_plls = true)
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Grzegorz Daniluk authored
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- 20 Nov, 2018 1 commit
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Grzegorz Daniluk authored
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- 16 Nov, 2018 4 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 15 Nov, 2018 2 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 29 Oct, 2018 1 commit
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Dimitris Lampridis authored
Second attempt to use dual reset async fifos and pulse synchronizers. The first one was 9810ef9a, later on reverted by 93d49e1f, because it was causing sync problems when unplugging/replugging the fiber. The problem was in the endpoint's rx path, where one side of the reset (the rx_clk side) was taking into account the state of the PHY (via the phy_rdy_i signal), while the other side (the sys_clk side) was not. This has been fixed in this commit, by using phy_rdy_i as an active-low reset source for both clock domains of the rx path. Tested on an SPEC, works.
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