- 17 Jul, 2014 4 commits
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Tomasz Wlostowski authored
Conflicts: ip_cores/etherbone-core ip_cores/general-cores ip_cores/gn4124-core modules/wrc_core/wrcore_pkg.vhd modules/wrc_core/xwr_core.vhd syn/spec_1_1/wr_core_demo/Manifest.py syn/spec_1_1/wr_core_demo/spec_top_wrc.xise
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Wesley W. Terpstra authored
The softpll_ng takes in a reset line from the sys clock domain. It instantiates several dmtd_with_deglitcher FSMs which need reset. The symptom of this bug is that on 3% of power-ups, some of the deglitchers will not issue tags, because they power-on into an undefined FSM state. This is caused by feeding the reset from a different clock domain, leading to a race condition on release. There was some code that probably used to solve this issue, whereby the sys reset was synchronized to the clk_dmtd_i. However, the softpll_ng instantiates multiple deglitchers, each in a different domain and thus this single synchronizer chain can not work for all of the deglitcher instances. The fix is simple: synchronize the reset for each clock domain.
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Maciej Lipinski authored
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Maciej Lipinski authored
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- 12 Jun, 2014 3 commits
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Grzegorz Daniluk authored
Under higher load of traffic SOF was being detected while main FSM was not yet done with sending frame. That caused OOB FSM to reset and "tx timestamp never became available" warnings in WR PTP Core software.
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Tomasz Wlostowski authored
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Grzegorz Daniluk authored
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- 18 Mar, 2014 2 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 20 Feb, 2014 1 commit
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Maciej Lipinski authored
[EP/tx_head_proc] bugfix: we had a problem with handling the error from PCS - if it occured when already the next frame was being set (addr), the PCS got confused
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- 14 Feb, 2014 2 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
Because the same module will be used in wrsw_nic for untagging frames.
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- 04 Feb, 2014 28 commits
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Grzegorz Daniluk authored
switch-optimization: ep_rx_buffer: don't count bytes inside FIFO when there is no flow control (which is currently always the case)
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
count_o is connected to level_o but wr_endpoint doesn't use this information for flow control.
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Grzegorz Daniluk authored
Conflicts: modules/wr_endpoint/endpoint_vectorized_top.vhd modules/wr_endpoint/ep_rx_path.vhd modules/wr_endpoint/ep_tx_path.vhd
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Grzegorz Daniluk authored
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Maciej Lipinski authored
improved test inj_gen mode configuration (can be changed separately from other config - different valid bit). This was convenient for software control implementation
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
corrected generation as it was sending 2 bytes more than in the set template (2-byte junk at the end)
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Maciej Lipinski authored
corrected test-frame generation using pck_injection (dev/null before VLAN unit cause VLAN unit and injection unit use the same RAM)
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Maciej Lipinski authored
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Maciej Lipinski authored
bugfix: hanged when dreq=low from PCS at the last word (EOF from CRC) -> one of reaons: ugly bug in pack_fifo_content function
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
added abort of RTU request - in case of error in the input frame, receiving of frame is aborted, error status sent to SWcore, and the RTU request needs to be aborted as well, otherwise SWcore gets lost
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Maciej Lipinski authored
bugfix: when frame corrupted in the header (or vlan unit droping frame cause frame is tagged and port is set to be access) the request to RTU was sent anyway... swcore was dropping frame, then receiving wrong RTU response... a mess. Now no rtu-req is done when frame corrupted in the header. still need to fix swcore->input block
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Maciej Lipinski authored
changed the size of tx pcs fifo to an original (master, 20) - I stupiditly done it so big (40) that small frames would not get through
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Maciej Lipinski authored
changed the order of modules so that rtu_request is done before rx_buffer (and at the same time as VLANs are handled)
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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