White Rabbit core collection:master commitshttps://ohwr.org/project/wr-cores/commits/master2023-12-20T08:44:36Zhttps://ohwr.org/project/wr-cores/commit/0f8fbced87988254f5c9ca55c0e04585b29b485cbin/wrpc: update firmwares2023-12-20T08:44:36ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/wr-cores/commit/39825ec55291cb12492090093f27a50f9d0b73d9spec_serial_dac_arb: decrease clock2023-12-19T09:04:16ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/wr-cores/commit/9a6ced7b7f4d7146d0262ac777101cbd9a1a4a51serial_dac856x.vhd: set gain2023-12-19T09:04:16ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/wr-cores/commit/eefe0fce1374c6de82d093827e34cf4eaad4c17aplatform/xilinx: add more support for aux pll2023-12-19T09:04:16ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/wr-cores/commit/c0d38f144e63d110d270096113a96034f887bc97wr_gtp_phy: allow not to use xilinx platform2023-12-19T09:04:16ZTristan Gingoldtristan.gingold@cern.ch
if the user design already includes the transceiver
(this change avoid inclusion of usless/conflicting xdc files)https://ohwr.org/project/wr-cores/commit/74d821a79d77ab8e7d52125b8205a8f39d548837pxie-fmc: support aux pll2023-12-19T09:04:16ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/wr-cores/commit/fe370b6997020e460f48b6d468f656584c31e9a3board/fasec: support aux pll2023-12-19T09:04:16ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/wr-cores/commit/8e79d0bc37ba9da8770ca0faa6d5efecde933703board/Manifest.py: add fasec2023-12-19T09:04:16ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/wr-cores/commit/1541066a2fb6d46c5abfa705c77d0f6ed72b6ae4Merge branch 'peter_gtp_bitslide' into 'wrpc-v5'2023-12-12T13:02:00ZTristan Gingoldtristan.gingold@cern.ch
Add generic: Artix7 gtp depends on rx_byte_is_aligned
See merge request <a href="/project/wr-cores/merge_requests/11" data-original="project/wr-cores!11" data-link="false" data-link-reference="false" data-project="10728" data-merge-request="280" data-reference-type="merge_request" data-container="body" data-placement="bottom" title="Add generic: Artix7 gtp depends on rx_byte_is_aligned" class="gfm gfm-merge_request has-tooltip">!11</a>https://ohwr.org/project/wr-cores/commit/c2b7c093a359eb525627aded6096692dfa8986f5Add generic: Artix7 gtp depends on rx_byte_is_aligned2023-12-11T16:56:22ZPeter Jansweijerpeterj@nikhef.nlhttps://ohwr.org/project/wr-cores/commit/d7c7b52ec2fff66280b212ffd146e1ca7e1a299bMerge branch 'peter_lpdc_via_wishbone_mdio' into 'wrpc-v5'2023-12-11T10:41:02ZTristan Gingoldtristan.gingold@cern.ch
Update family7 gtx-lp and gthe4-lp, now using lpdc via wishbone mdio
See merge request <a href="/project/wr-cores/merge_requests/9" data-original="project/wr-cores!9" data-link="false" data-link-reference="false" data-project="10728" data-merge-request="250" data-reference-type="merge_request" data-container="body" data-placement="bottom" title="Update family7 gtx-lp and gthe4-lp, now using lpdc via wishbone mdio" class="gfm gfm-merge_request has-tooltip">!9</a>https://ohwr.org/project/wr-cores/commit/bb25c7387c5f8f1f8275c7c4e7d75adcaf081954Merge branch 'wrpc-v5-sim-works' into 'wrpc-v5'2023-12-11T10:39:30ZTristan Gingoldtristan.gingold@cern.ch
wrc_core sim for wrpc-v5 works
See merge request <a href="/project/wr-cores/merge_requests/10" data-original="project/wr-cores!10" data-link="false" data-link-reference="false" data-project="10728" data-merge-request="270" data-reference-type="merge_request" data-container="body" data-placement="bottom" title="wrc_core sim for wrpc-v5 works" class="gfm gfm-merge_request has-tooltip">!10</a>https://ohwr.org/project/wr-cores/commit/296c17cc84b3199c9836fbe08d5b2ada66688d57Remove wrc.bram2023-11-24T16:24:05ZAndela Kosticandela.kostic@cern.chhttps://ohwr.org/project/wr-cores/commit/cd942e1319213e8bd1b02df25e4ab9ce343144dfSupport both wrc_core and streamers-on-spec_trigger-distribution testbenches2023-11-24T16:11:23ZAndela Kosticandela.kostic@cern.ch
Now, in testbench/wrc_core there are two folders - modelsim and riviera. Each of them contains
Manifest.py and run.do adjusted for the simulation with ModelSim/Riviera. One should navigate to
one of these folders to run the simulation with the corresponding simulator.
The streamers-on-spec_trigger-distribution testbench works now for wrpc-v5 in ModelSim.
However, it does not work with Riviera. The problem is that the secureip library cannot be
compiled for the spartan 6 and the Riviera version after 2008.https://ohwr.org/project/wr-cores/commit/db46b00a6bfff2fb6c4f94ab7642cd881378dd9bTestbench wrc_core now works with Riviera-PRO2023-11-10T14:07:49ZAndela Kosticandela.kostic@cern.ch
The testbench wrc_core for wrpc-v5 now works both with Riviera-PRO and ModelSim.
In Manifest.py, some lines should be commented out depending on the simulation tool (ModelSim or Riviera).
To run the simulation with Riviera, use run_riv.do.
To run the simulation with ModelSim, use run.do.https://ohwr.org/project/wr-cores/commit/815f56e2beceb769a8b8a16160b8882dda72b508Testbench wrc_core now works with Riviera-PRO2023-11-10T13:59:10ZAndela Kosticandela.kostic@cern.ch
The testbench wrc_core for wrpc-v5 now works both with Riviera-PRO and ModelSim.
In Manifest.py, some lines should be commented out depending on the simulation tool (ModelSim or Riviera).
To run the simulation with Riviera, use run_riv.do.
To run the simulation with ModelSim, use run.do.https://ohwr.org/project/wr-cores/commit/06d5a438c78330c96c5ff3cfb89f98d53ac54ff1Ensure functionality of wrc_core testbench for wrpc-v52023-11-09T10:23:32ZAndela Kosticandela.kostic@cern.ch
In wrpc-v5, LM32 is replaced by RISC-V. Hence, the new compiled WRPC software
for the simulation is added (wrc.bram file).
Also, the size of the RAM used by the WRPC software is increased.
The testbench sets hdl_testbench structure used for communication with the software.
The simulation works with ModelSim.https://ohwr.org/project/wr-cores/commit/89fd975c6237f46a57239b867a264d0527678f1dwr_softpll_ng: improved CDC logic. Fixes rare no-locks/FIFO errors, likely due…2023-11-06T16:20:59ZTomasz Wlostowskitomasz.wlostowski@cern.chwr_softpll_ng: improved CDC logic. Fixes rare no-locks/FIFO errors, likely due to synthesizer doing some weird cross-clock-domains logic optimizations
https://ohwr.org/project/wr-cores/commit/ccd0d2d62642b2ba4644231f95898e3bf20605afdmtd_with_deglitcher: reset only the counter, not the whole deglitching FSM2023-10-22T22:03:47ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/2cc1bd7434c903f626060795804e09131897a055dmtd_sampler: make oversamping enable signal truly sync2023-09-18T13:26:13ZTristan Gingoldtristan.gingold@cern.ch
... with the input clockhttps://ohwr.org/project/wr-cores/commit/cf7ae807b80d57dcfea51e2166b79f5d8384b0cawr_softpll_ng: avoid index error2023-09-18T13:25:03ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/wr-cores/commit/72796f3474fda36cd568127e310ba2c0e384350ewrc_dac_dithering: avoid bias2023-09-06T14:08:02ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/wr-cores/commit/51bb4579707f8a4bdf1ad14e14e16eef122f35d5wr_core: added optional dithered DAC driver module2023-09-06T09:12:02ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/4fe0f3cc863e5f71b1cd037987b3057689543c20wr_softpll_ng: extend DAC bit count in DAC_HELPER/DAC_MAIN regs to 24 for HW ...2023-09-06T08:39:05ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/4cc5b6f191e8ca08a4fd95ec2629cb65e4fdd998dmtd_with_deglitcher: add optional jitter measurement2023-09-06T08:12:48ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/wr-cores/commit/a224e333afef80ce6b7aabd906741c5de6645301reverse oversampled DDMTD mode2023-09-06T07:39:15ZTomasz Wlostowskitomasz.wlostowski@cern.ch
wr_core: add generic for reverse DDMTD operation
wr_gtx_phy_kintex7_lp: make 'reversed' DDMTD operation a generichttps://ohwr.org/project/wr-cores/commit/1b0ac87a1658bceafd55d70a12a06f61b2289766wr_softpll_ng: remove unused DDMTD features2023-09-05T07:20:21ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/0e3962b4d4f8def75e2804d5b85eb183fdbea6efGTHE4_lp 125 / 100 MHz PHY Reference Clock selection2023-08-31T07:55:28ZPeter Jansweijerpeterj@nikhef.nlhttps://ohwr.org/project/wr-cores/commit/0c342bd3275c1f6dda6f10e273627c6ad32ac648family7-gtx-lp lpdc via wishbone mdio2023-08-25T10:08:11ZPeter Jansweijerpeterj@nikhef.nlhttps://ohwr.org/project/wr-cores/commit/816c05548eb91d048a53b694a204195cfc65adadfamily7-gthe4-lp lpdc via wishbone mdio2023-08-25T10:07:01ZPeter Jansweijerpeterj@nikhef.nlhttps://ohwr.org/project/wr-cores/commit/64c1032f5e8bfded92ee0618ab861739310412c3serial_dac856x: add auto-initialization2023-07-21T12:34:40ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/wr-cores/commit/bf48dc31ce30f51a847e9a29b9e885e70a468bf3Add serial_dac856x (and a testbench)2023-07-21T11:55:32ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/wr-cores/commit/7cd9b30fe36abcac6721b93a86b1c783ab504644xwrc_board_pxie_fmc: add pps_valid_o output2023-07-21T09:28:53ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/wr-cores/commit/7a1a969cc182e6d5169f670698c6d8071d68a033Merge branch 'wrpc-v5-rst' into 'wrpc-v5'2023-07-20T14:16:21ZTristan Gingoldtristan.gingold@cern.ch
boards: fix incorrect logic of reset input for aasd
See merge request <a href="/project/wr-cores/merge_requests/8" data-original="project/wr-cores!8" data-link="false" data-link-reference="false" data-project="10728" data-merge-request="246" data-reference-type="merge_request" data-container="body" data-placement="bottom" title="boards: fix incorrect logic of reset input for aasd" class="gfm gfm-merge_request has-tooltip">!8</a>https://ohwr.org/project/wr-cores/commit/2d7e024563a8dd093a5171288afa66d0594a69c7boards: fix incorrect logic of reset input for aasd2023-07-20T09:35:38ZTristan Gingoldtristan.gingold@cern.ch
The arst_i input of gc_reset_multi_aasd is active high,
so the resets must be or-ed (using positive logic)https://ohwr.org/project/wr-cores/commit/1ee142a3830995ea2e940165b3b86fb95667b019wr_softpll_ng.vhd: minor indentation2023-06-14T06:32:56ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/wr-cores/commit/91ea0ab027717eb1beb7051c9a72dc76ec482cecwrc_core: add g_hwbld_date generic2023-06-12T11:39:00ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/wr-cores/commit/6f867f11ca3484ef51439e62e7e755ed8788b518wrc_syscon_wb: add sfp2, add build-date2023-06-12T11:39:00ZTristan Gingoldtristan.gingold@cern.ch
Remove unused led_green and led_red, regenerate
Generate H header with struct (instead of offsets)https://ohwr.org/project/wr-cores/commit/8feb29dccb03792b276804824ed09b3bf9781c16wrc_core: remove unused led_green and led_red2023-06-12T11:39:00ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/wr-cores/commit/3c5cf0df8fd366ce87ae5a9f90297d44dce333a5gtx: remove useless (and incorrect) parentheses2023-06-12T11:39:00ZTristan Gingoldtristan.gingold@cern.ch