1. 27 Jul, 2018 1 commit
  2. 14 Feb, 2017 1 commit
  3. 26 Oct, 2016 1 commit
  4. 31 May, 2016 1 commit
    • Maciej Lipinski's avatar
      Adding WR transmission module · 5c8532a5
      Maciej Lipinski authored
      it contains streamers as well as a WB-accessible registers for:
      - reading/controling statistics (module to be added)
      - debugging
      - controlling streamers, e.g. reset sequence
      5c8532a5
  5. 24 May, 2016 1 commit
  6. 07 Mar, 2016 1 commit
  7. 26 Aug, 2013 1 commit
  8. 22 Aug, 2013 1 commit
  9. 17 Apr, 2013 1 commit
  10. 18 Dec, 2012 1 commit
  11. 11 Sep, 2012 1 commit
  12. 31 Jul, 2012 1 commit
  13. 03 Jul, 2012 1 commit
    • Stefan Rauch's avatar
      Massive reorginizaion of GSI project files. · 1b373238
      Stefan Rauch authored
        * Added the new SCU2 target (different pinouts and components)
        * Moved common components (uart) to modules
        * Moved the common spec and SCU DAC files into modules
        * Added the DDR3 controller for Altera
        * Removed a few superfluous files from version control
      1b373238
  14. 22 May, 2012 1 commit
  15. 27 Mar, 2012 1 commit
  16. 26 Mar, 2012 1 commit
  17. 08 Mar, 2012 2 commits
  18. 10 Feb, 2012 1 commit
  19. 06 Feb, 2012 1 commit
  20. 24 Jan, 2012 1 commit
  21. 20 Jan, 2012 2 commits
  22. 19 Jan, 2012 1 commit
  23. 17 Jan, 2012 1 commit
  24. 09 Dec, 2011 1 commit
  25. 28 Oct, 2011 1 commit
  26. 27 Oct, 2011 1 commit
  27. 26 Oct, 2011 1 commit
  28. 25 Oct, 2011 1 commit
  29. 11 May, 2011 2 commits