1. 23 May, 2019 1 commit
  2. 14 May, 2019 1 commit
    • Maciej Lipinski's avatar
      [wr_streamers_demo] Updated the streamers demo to work Boards Support Package · 15403bb0
      Maciej Lipinski authored
      The streamers demo was using very old top. With the updated of resets,
      etc, it stopped working (at least the testbench did stop). So, I finally
      updated this top to work (in the testbench at least) with the new BSP.
      This required a major re-do of the top. I left from the old as much
      as I could. The new top is based on the spec_ref_design. This was
      tested only for simulation
      (testbech/wr_streamers/streamers-on-spec_trigger-distribution).
      A commit with updates to simulation follows.
      15403bb0
  3. 26 Apr, 2019 1 commit
  4. 21 Jan, 2019 12 commits
  5. 03 Dec, 2018 2 commits
  6. 16 Oct, 2018 3 commits
  7. 27 Jul, 2018 1 commit
  8. 20 Mar, 2018 1 commit
  9. 15 Dec, 2017 1 commit
  10. 13 Dec, 2017 6 commits
    • Grzegorz Daniluk's avatar
    • Grzegorz Daniluk's avatar
      fasec: update WRPC to v4.2 · 2d55ee1d
      Grzegorz Daniluk authored
      2d55ee1d
    • Peter Jansweijer's avatar
      a6256755
    • Peter Jansweijer's avatar
      CLBv2: removed DIO pin comment · 622c948b
      Peter Jansweijer authored
      622c948b
    • Peter Jansweijer's avatar
      clbv3 reference design files · 522c6cbd
      Peter Jansweijer authored
      updates kintex7 phy name to reflect new peter_xilinx_phys convention
      add clbv3 reference design files
      last commit also needs artix7 support in xwrc_platform_xilinx.vhd
      added BullsEye connections
      CLBv3: moved dmtd div2 and buffer into xwrc_platform_xilinx.vhd
      CLBv3: implementation files (including bmm)
      CLBv3: Clean up
      
      Conflicts:
      	platform/xilinx/xwrc_platform_xilinx.vhd
      522c6cbd
    • Peter Jansweijer's avatar
      clbv2 reference design files · d2f24245
      Peter Jansweijer authored
      added clbv2_ref_design files
      added initial clbv2_ref_design ucf file
      removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization
      removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization, phy16
      Merge branch 'peter_clbv2_ref_design' of ohwr.org:hdl-core-lib/wr-cores into peter_clbv2_ref_design
      clk_20m_vcxo_i free running clock for reset gen. (thus no need for separate 125 MHz fpga input; remove clk_125m_pllref_p/n_i)
      updates kintex7 phy name to reflect new peter_xilinx_phys convention
      last commit also needs artix7 support in xwrc_platform_xilinx.vhd
      CLBv2: reference clock is 62.5 MHz for 16 bit PHYs. Changed naming convention accordingly.
      CLBv2: point proper bram file
      CLBv2: implementation (including bmm)
      CLBv2 reference design cleaned
      CLBv2: updated (hdlmake made) Xilinx ISE project file
      d2f24245
  11. 08 Dec, 2017 1 commit
  12. 30 Nov, 2017 1 commit
  13. 24 Nov, 2017 2 commits
  14. 18 Aug, 2017 1 commit
  15. 30 Jun, 2017 3 commits
  16. 19 Jun, 2017 1 commit
  17. 14 Jun, 2017 2 commits