...
 
Commits (159)
......@@ -19,3 +19,4 @@ doc/
Makefile
*.xml
xgui/
*.orig
\ No newline at end of file
[submodule "ip_cores/general-cores"]
path = ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
url = https://ohwr.org/project/general-cores.git
[submodule "ip_cores/etherbone-core"]
path = ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
url = https://ohwr.org/project/etherbone-core.git
[submodule "ip_cores/gn4124-core"]
path = ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
url = https://ohwr.org/project/gn4124-core.git
[submodule "ip_cores/vme64x-core"]
path = ip_cores/vme64x-core
url = git://ohwr.org/hdl-core-lib/vme64x-core.git
url = https://ohwr.org/project/vme64x-core.git
This diff is collapsed.
try:
if board in ["spec", "svec", "vfchd", "common"]:
if board in ["spec", "spec7", "svec", "vfchd", "common"]:
modules = {"local" : [ board ] }
except NameError:
pass
......@@ -311,6 +311,7 @@ begin -- architecture struct
cmp_xwrc_platform : xwrc_platform_xilinx
generic map (
g_fpga_family => "artix7",
g_direct_dmtd => TRUE,
g_with_external_clock_input => g_with_external_clock_input,
g_use_default_plls => TRUE,
g_simulation => g_simulation)
......@@ -428,7 +429,7 @@ begin -- architecture struct
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => g_with_external_clock_input,
g_board_name => "CLB2",
g_board_name => "CLB3",
g_phys_uart => TRUE,
g_virtual_uart => TRUE,
g_aux_clks => g_aux_clks,
......
......@@ -75,6 +75,10 @@ package wr_board_pkg is
application_size : integer
) return integer;
function f_pick_clk_ref_rate (
pcs_16bit_in : boolean
) return integer;
function f_vectorize_diag (
diag_in : t_generic_word_array;
diag_vector_size : integer)
......@@ -88,12 +92,14 @@ package wr_board_pkg is
function f_find_default_lm32_firmware (
dpram_initf : string;
simulation : integer;
pcs_16_bit : boolean)
pcs_16_bit : boolean;
verbose : boolean := TRUE)
return string;
component xwrc_board_common is
generic (
g_simulation : integer := 0;
g_verbose : boolean := TRUE;
g_with_external_clock_input : boolean := TRUE;
g_board_name : string := "NA ";
g_flash_secsz_kb : integer := 256; -- default for M25P128
......@@ -136,6 +142,16 @@ package wr_board_pkg is
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
pll_status_i : in std_logic := '0';
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic := '0';
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic := '0';
pll_clk_sel_o : out std_logic;
phy8_o : out t_phy_8bits_from_wrc;
phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
phy16_o : out t_phy_16bits_from_wrc;
......@@ -286,6 +302,18 @@ package body wr_board_pkg is
end if;
end f_pick_diag_size;
-- guess clk_ref (WR reference Clock) rate based on PCS word width
function f_pick_clk_ref_rate (
pcs_16bit_in : boolean
) return integer is
begin
if(pcs_16bit_in = TRUE) then
return 62500000;
else
return 125000000;
end if;
end f_pick_clk_ref_rate;
function f_vectorize_diag (
diag_in : t_generic_word_array;
diag_vector_size : integer)
......@@ -319,7 +347,8 @@ package body wr_board_pkg is
function f_find_default_lm32_firmware (
dpram_initf : string;
simulation : integer;
pcs_16_bit : boolean)
pcs_16_bit : boolean;
verbose : boolean := TRUE)
return string is
begin
if((dpram_initf = "default_altera" or dpram_initf = "default_xilinx") and
......@@ -329,28 +358,38 @@ package body wr_board_pkg is
"pcs_16_bit." severity FAILURE;
return "";
elsif (dpram_initf /= "default_altera" and dpram_initf /= "default_xilinx") then
report "[Board:Software for LM32 in WR Core] Using user-provided LM32 " &
"firmware ("&dpram_initf&")." severity NOTE;
if verbose = TRUE then
report "[Board:Software for LM32 in WR Core] Using user-provided LM32 " &
"firmware ("&dpram_initf&")." severity NOTE;
end if;
return dpram_initf;
elsif (simulation = 0 and dpram_initf = "default_altera" and pcs_16_bit = FALSE and
dpram_initf_default_altera_phy8 /= "") then
report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
"(altera, phy8)." severity NOTE;
if verbose = TRUE then
report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
"(altera, phy8)." severity NOTE;
end if;
return dpram_initf_default_altera_phy8;
elsif (simulation = 0 and dpram_initf = "default_xilinx" and pcs_16_bit = FALSE and
dpram_initf_default_xilinx_phy8 /= "") then
report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
"(xilnix, phy8)" severity NOTE;
if verbose = TRUE then
report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
"(xilnix, phy8)" severity NOTE;
end if;
return dpram_initf_default_xilinx_phy8;
elsif (simulation = 1 and dpram_initf = "default_altera" and pcs_16_bit = FALSE and
dpram_initf_default_altera_phy8_sim /= "") then
report "Board:[Software for LM32 in WR Core] Using release LM32 firmware " &
"(altera, phy8, sim)." severity NOTE;
if verbose = TRUE then
report "Board:[Software for LM32 in WR Core] Using release LM32 firmware " &
"(altera, phy8, sim)." severity NOTE;
end if;
return dpram_initf_default_altera_phy8_sim;
elsif (simulation = 1 and dpram_initf = "default_xilinx" and pcs_16_bit = FALSE and
dpram_initf_default_xilinx_phy8_sim /= "") then
report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
"(xilinx, phy8, sim)." severity NOTE;
if verbose = TRUE then
report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
"(xilinx, phy8, sim)." severity NOTE;
end if;
return dpram_initf_default_xilinx_phy8_sim;
else
assert FALSE
......
......@@ -49,6 +49,7 @@ use work.wr_board_pkg.all;
entity xwrc_board_common is
generic(
g_simulation : integer := 0;
g_verbose : boolean := TRUE;
g_with_external_clock_input : boolean := TRUE;
g_board_name : string := "NA ";
g_flash_secsz_kb : integer := 256; -- default for M25P128
......@@ -115,6 +116,22 @@ entity xwrc_board_common is
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
-----------------------------------------
-- AD9516 PLL Control signals
-----------------------------------------
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic;
-- SPEC7 Select clk_sys source (either always running clk_dmtd or
-- 125 MHz from AD9516 after PLL initialisation.)
pll_clk_sel_o : out std_logic;
---------------------------------------------------------------------------
-- PHY I/f
---------------------------------------------------------------------------
......@@ -364,6 +381,7 @@ begin -- architecture struct
cmp_xwr_core : xwr_core
generic map (
g_simulation => g_simulation,
g_verbose => g_verbose,
g_with_external_clock_input => g_with_external_clock_input,
g_board_name => g_board_name,
g_flash_secsz_kb => g_flash_secsz_kb,
......@@ -373,7 +391,7 @@ begin -- architecture struct
g_aux_clks => g_aux_clks,
g_ep_rxbuf_size => g_ep_rxbuf_size,
g_tx_runt_padding => g_tx_runt_padding,
g_dpram_initf => f_find_default_lm32_firmware(g_dpram_initf, g_simulation, g_pcs_16bit),
g_dpram_initf => f_find_default_lm32_firmware(g_dpram_initf, g_simulation, g_pcs_16bit, FALSE),
g_dpram_size => g_dpram_size,
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
......@@ -402,6 +420,16 @@ begin -- architecture struct
dac_hpll_data_o => dac_hpll_data_o,
dac_dpll_load_p1_o => dac_dpll_load_p1_o,
dac_dpll_data_o => dac_dpll_data_o,
pll_status_i => pll_status_i,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
pll_refsel_o => pll_refsel_o,
pll_lock_i => pll_lock_i,
pll_clk_sel_o => pll_clk_sel_o,
phy_ref_clk_i => '0',
phy_tx_data_o => open,
phy_tx_k_o => open,
......@@ -489,7 +517,8 @@ begin -- architecture struct
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
g_simulation => g_simulation)
g_simulation => g_simulation,
g_clk_ref_rate => f_pick_clk_ref_rate(g_pcs_16bit))
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......
files = [
"wr_cute_pkg.vhd",
"xwrc_board_cute.vhd",
]
modules = {
"local" : [
"../common",
]
}
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for CUTE package
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_cute_pkg.vhd
-- Author(s) : Hongming Li <lihm.thu@foxmail.com>
-- Company : Tsinghua Univ. (DEP)
-- Created : 2018-07-14
-- Last update: 2018-07-14
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wr_board_pkg.all;
use work.streamers_pkg.all;
package wr_cute_pkg is
component xwrc_board_cute is
generic(
g_simulation : integer := 0;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 0;
g_fabric_iface : t_board_fabric_iface := plain;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_dpram_initf : string := "default_xilinx";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0;
-- CUTE special
g_cute_version : string := "2.2";
g_sfp0_enable : integer := 1;
g_sfp1_enable : integer := 0;
g_phy_refclk_sel : integer := 0;
g_multiboot_enable : boolean := false);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
clk_20m_vcxo_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp0_p_i : in std_logic :='0';
clk_125m_gtp0_n_i : in std_logic :='0';
clk_125m_gtp1_p_i : in std_logic :='0';
clk_125m_gtp1_n_i : in std_logic :='0';
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
clk_10m_ext_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
plldac_clr_n_o : out std_logic;
plldac_load_n_o : out std_logic;
plldac_sync_n_o : out std_logic;
sfp0_txp_o : out std_logic;
sfp0_txn_o : out std_logic;
sfp0_rxp_i : in std_logic := '0';
sfp0_rxn_i : in std_logic := '0';
sfp0_det_i : in std_logic := '0';
sfp0_sda_i : in std_logic := '1';
sfp0_sda_o : out std_logic;
sfp0_scl_i : in std_logic := '1';
sfp0_scl_o : out std_logic;
sfp0_rate_select_o : out std_logic;
sfp0_tx_fault_i : in std_logic := '0';
sfp0_tx_disable_o : out std_logic;
sfp0_los_i : in std_logic := '0';
sfp1_txp_o : out std_logic;
sfp1_txn_o : out std_logic;
sfp1_rxp_i : in std_logic := '0';
sfp1_rxn_i : in std_logic := '0';
sfp1_det_i : in std_logic := '0';
sfp1_sda_i : in std_logic := '1';
sfp1_sda_o : out std_logic;
sfp1_scl_i : in std_logic := '1';
sfp1_scl_o : out std_logic;
sfp1_rate_select_o : out std_logic;
sfp1_tx_fault_i : in std_logic := '0';
sfp1_tx_disable_o : out std_logic;
sfp1_los_i : in std_logic := '0';
eeprom_sda_i : in std_logic := '1';
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic := '1';
eeprom_scl_o : out std_logic;
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic := '1';
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_i : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
pps_csync_o : out std_logic;
link_ok_o : out std_logic);
end component xwrc_board_cute;
constant c_xwb_tcpip_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000001103", -- thu
device_id => x"c0413599",
version => x"00000001",
date => x"20160424",
name => "wr-tcp-ip-stack ")));
end wr_cute_pkg;
This diff is collapsed.
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2018-11-28
-- Last update: 2019-04-23
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
......@@ -49,9 +49,9 @@ package wr_spec_pkg is
component xwrc_board_spec is
generic (
g_simulation : integer := 0;
g_verbose : boolean := TRUE;
g_with_external_clock_input : boolean := TRUE;
g_aux_clks : integer := 0;
g_aux_pll_config : t_px_pll_cfg := c_PX_DEFAULT_PLL_CFG;
g_fabric_iface : t_board_fabric_iface := plain;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
......@@ -60,7 +60,8 @@ package wr_spec_pkg is
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0);
g_diag_rw_size : integer := 0;
g_aux_pll_cfg : t_auxpll_cfg_array := c_AUXPLL_CFG_ARRAY_DEFAULT);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
......@@ -74,10 +75,10 @@ package wr_spec_pkg is
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
clk_pll_aux_o : out std_logic;
clk_pll_aux_o : out std_logic_vector(3 downto 0);
rst_pll_aux_n_o : out std_logic_vector(3 downto 0);
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
rst_pll_aux_n_o : out std_logic;
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic;
......@@ -159,6 +160,7 @@ package wr_spec_pkg is
component wrc_board_spec is
generic (
g_simulation : integer := 0;
g_verbose : integer := 1;
g_with_external_clock_input : integer := 1;
g_aux_clks : integer := 0;
g_fabric_iface : string := "PLAINFBRC";
......
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2018-11-28
-- Last update: 2019-04-23
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -57,6 +57,8 @@ entity wrc_board_spec is
generic(
-- set to 1 to speed up some initialization processes during simulation
g_simulation : integer := 0;
-- set to 0 to reduce information messages during simulation
g_verbose : integer := 1;
-- Select whether to include external ref clock input
g_with_external_clock_input : integer := 1;
-- Number of aux clocks syntonized by WRPC to WR timebase
......@@ -433,6 +435,7 @@ begin -- architecture struct
cmp_xwrc_board_spec : xwrc_board_spec
generic map (
g_simulation => g_simulation,
g_verbose => f_int2bool(g_verbose),
g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
g_aux_clks => g_aux_clks,
g_fabric_iface => f_str2iface_type(g_fabric_iface),
......
......@@ -7,14 +7,14 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2018-11-28
-- Last update: 2019-04-23
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
-- needed to operate the core on the SPEC board.
-- http://www.ohwr.org/projects/spec/
-------------------------------------------------------------------------------
-- Copyright (c) 2017-2018 CERN
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
......@@ -57,20 +57,20 @@ entity xwrc_board_spec is
generic(
-- set to 1 to speed up some initialization processes during simulation
g_simulation : integer := 0;
-- set to false to reduce information messages during simulation
g_verbose : boolean := TRUE;
-- Select whether to include external ref clock input
g_with_external_clock_input : boolean := TRUE;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks : integer := 0;
-- Config for the auxiliary PLL output
g_aux_pll_config : t_px_pll_cfg := c_PX_DEFAULT_PLL_CFG;
-- plain = expose WRC fabric interface
-- streamers = attach WRC streamers to fabric interface
-- etherbone = attach Etherbone slave to fabric interface
g_fabric_iface : t_board_fabric_iface := plain;
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "default_xilinx";
-- identification (id and ver) of the layout of words in the generic diag interface
......@@ -78,7 +78,10 @@ entity xwrc_board_spec is
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0);
g_diag_rw_size : integer := 0;
-- User-defined PLL_BASE outputs config
g_aux_pll_cfg : t_auxpll_cfg_array := c_AUXPLL_CFG_ARRAY_DEFAULT
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
......@@ -104,13 +107,13 @@ entity xwrc_board_spec is
clk_sys_62m5_o : out std_logic;
-- 125MHz ref clock output
clk_ref_125m_o : out std_logic;
-- Auxiliary clock output from PLL, configured through g_aux_pll_config.
-- Not to be confused with clk_aux_i and/or g_aux_clks parameter.
clk_pll_aux_o : out std_logic;
-- Configurable (with g_aux_pll_cfg) clock outputs from the main PLL_BASE
clk_pll_aux_o : out std_logic_vector(3 downto 0);
-- active low reset outputs, synchronous to clk_pll_aux_o clocks
rst_pll_aux_n_o : out std_logic_vector(3 downto 0);
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
rst_pll_aux_n_o : out std_logic;
---------------------------------------------------------------------------
-- Shared SPI interface to DACs
......@@ -276,14 +279,14 @@ architecture struct of xwrc_board_spec is
signal clk_pll_dmtd : std_logic;
signal pll_locked : std_logic;
signal clk_10m_ext : std_logic;
signal clk_pll_aux : std_logic;
signal clk_pll_aux : std_logic_vector(3 downto 0);
-- Reset logic
signal areset_edge_ppulse : std_logic;
signal rst_62m5_n : std_logic;
signal rstlogic_arst : std_logic;
signal rstlogic_clk_in : std_logic_vector(2 downto 0);
signal rstlogic_rst_out : std_logic_vector(2 downto 0);
signal rstlogic_clk_in : std_logic_vector(5 downto 0);
signal rstlogic_rst_out : std_logic_vector(5 downto 0);
-- PLL DAC ARB
signal dac_hpll_load_p1 : std_logic;
......@@ -326,7 +329,8 @@ begin -- architecture struct
g_fpga_family => "spartan6",
g_with_external_clock_input => g_with_external_clock_input,
g_use_default_plls => TRUE,
g_aux_pll_config => g_aux_pll_config,
g_aux_pll_cfg => g_aux_pll_cfg,
g_phy_refclk_sel => 4,
g_simulation => g_simulation)
port map (
areset_n_i => areset_n_i,
......@@ -363,7 +367,7 @@ begin -- architecture struct
-- Reset logic
-----------------------------------------------------------------------------
-- Detect when areset_edge_n_i goes high (end of reset) and use this edge to
-- generate rstlogic_arst_n. This is needed to connect optional reset like PCIe
-- generate rstlogic_arst. This is needed to connect optional reset like PCIe
-- reset. When baord runs standalone, we need to ignore PCIe reset being
-- constantly low.
cmp_arst_edge: gc_sync_ffs
......@@ -379,13 +383,13 @@ begin -- architecture struct
rstlogic_arst <= (not pll_locked) and (not areset_n_i) and areset_edge_ppulse;
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in(0) <= clk_pll_62m5;
rstlogic_clk_in(1) <= clk_pll_125m;
rstlogic_clk_in(2) <= clk_pll_aux;
rstlogic_clk_in(0) <= clk_pll_62m5;
rstlogic_clk_in(1) <= clk_pll_125m;
rstlogic_clk_in(5 downto 2) <= clk_pll_aux;
cmp_rstlogic_reset : gc_reset_multi_aasd
generic map (
g_CLOCKS => 3, -- 62.5MHz, 125MHz, plus aux clk
g_CLOCKS => 6, -- 62.5MHz, 125MHz, + 4x pll_aux
g_RST_LEN => 16) -- 16 clock cycles
port map (
arst_i => rstlogic_arst,
......@@ -397,7 +401,7 @@ begin -- architecture struct
rst_sys_62m5_n_o <= rst_62m5_n;
rst_ref_125m_n_o <= rstlogic_rst_out(1);
rst_pll_aux_n_o <= rstlogic_rst_out(2);
rst_pll_aux_n_o <= rstlogic_rst_out(5 downto 2);
-----------------------------------------------------------------------------
-- 2x SPI DAC
......@@ -426,6 +430,7 @@ begin -- architecture struct
cmp_board_common : xwrc_board_common
generic map (
g_simulation => g_simulation,
g_verbose => g_verbose,
g_with_external_clock_input => g_with_external_clock_input,
g_board_name => "SPEC",
g_flash_secsz_kb => 64, -- sector size for M25P32
......
files = [
"wr_spec7_pkg.vhd",
"xwrc_board_spec7.vhd",
]
modules = {
"local" : [
"../common",
]
}
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......@@ -7,10 +7,10 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2018-11-28
-- Last update: 2019-04-23
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017-2018 CERN
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
......@@ -49,9 +49,9 @@ package wr_svec_pkg is
component xwrc_board_svec is
generic (
g_simulation : integer := 0;
g_verbose : boolean := TRUE;
g_with_external_clock_input : boolean := TRUE;
g_aux_clks : integer := 0;
g_aux_pll_config : t_px_pll_cfg := c_PX_DEFAULT_PLL_CFG;
g_fabric_iface : t_board_fabric_iface := plain;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
......@@ -60,7 +60,8 @@ package wr_svec_pkg is
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0);
g_diag_rw_size : integer := 0;
g_aux_pll_cfg : t_auxpll_cfg_array := c_AUXPLL_CFG_ARRAY_DEFAULT);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
......@@ -74,10 +75,10 @@ package wr_svec_pkg is
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
clk_pll_aux_o : out std_logic;
clk_pll_aux_o : out std_logic_vector(3 downto 0);
rst_pll_aux_n_o : out std_logic_vector(3 downto 0);
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
rst_pll_aux_n_o : out std_logic;
pll20dac_din_o : out std_logic;
pll20dac_sclk_o : out std_logic;
pll20dac_sync_n_o : out std_logic;
......@@ -158,6 +159,7 @@ package wr_svec_pkg is
component wrc_board_svec is
generic (
g_simulation : integer := 0;
g_verbose : integer := 1;
g_with_external_clock_input : integer := 1;
g_aux_clks : integer := 0;
g_fabric_iface : string := "plainfbrc";
......
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2018-06-22
-- Last update: 2019-02-01
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -56,6 +56,8 @@ entity wrc_board_svec is
generic(
-- set to 1 to speed up some initialization processes during simulation
g_simulation : integer := 0;
-- set to 0 to reduce information messages during simulation
g_verbose : integer := 1;
-- Select whether to include external ref clock input
g_with_external_clock_input : integer := 1;
-- Number of aux clocks syntonized by WRPC to WR timebase
......@@ -428,6 +430,7 @@ begin -- architecture struct
cmp_xwrc_board_svec : xwrc_board_svec
generic map (
g_simulation => g_simulation,
g_verbose => f_int2bool(g_verbose),
g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
g_aux_clks => g_aux_clks,
g_fabric_iface => f_str2iface_type(g_fabric_iface),
......
......@@ -7,14 +7,14 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2018-11-28
-- Last update: 2019-04-23
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
-- needed to operate the core on the SVEC board.
-- http://www.ohwr.org/projects/svec/
-------------------------------------------------------------------------------
-- Copyright (c) 2017-2018 CERN
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
......@@ -57,20 +57,20 @@ entity xwrc_board_svec is
generic(
-- set to 1 to speed up some initialization processes during simulation
g_simulation : integer := 0;
-- set to false to reduce information messages during simulation
g_verbose : boolean := TRUE;
-- Select whether to include external ref clock input
g_with_external_clock_input : boolean := TRUE;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks : integer := 0;
-- Config for the auxiliary PLL output
g_aux_pll_config : t_px_pll_cfg := c_PX_DEFAULT_PLL_CFG;
-- plain = expose WRC fabric interface
-- streamers = attach WRC streamers to fabric interface
-- etherbone = attach Etherbone slave to fabric interface
g_fabric_iface : t_board_fabric_iface := plain;
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "default_xilinx";
-- identification (id and ver) of the layout of words in the generic diag interface
......@@ -78,7 +78,9 @@ entity xwrc_board_svec is
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0
g_diag_rw_size : integer := 0;
-- User-defined PLL_BASE outputs config
g_aux_pll_cfg : t_auxpll_cfg_array := c_AUXPLL_CFG_ARRAY_DEFAULT
);
port (
---------------------------------------------------------------------------
......@@ -105,13 +107,13 @@ entity xwrc_board_svec is
clk_sys_62m5_o : out std_logic;
-- 125MHz ref clock output
clk_ref_125m_o : out std_logic;
-- Auxiliary clock output from PLL, configured through g_aux_pll_config.
-- Not to be confused with clk_aux_i and/or g_aux_clks parameter.
clk_pll_aux_o : out std_logic;
-- active low reset outputs, synchronous to their respective clocks
-- Configurable (with g_aux_pll_cfg) clock outputs from the main PLL_BASE
clk_pll_aux_o : out std_logic_vector(3 downto 0);
-- active low reset outputs, synchronous to clk_pll_aux_o clocks
rst_pll_aux_n_o : out std_logic_vector(3 downto 0);
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
rst_pll_aux_n_o : out std_logic;
---------------------------------------------------------------------------
-- SPI interfaces to DACs
......@@ -274,14 +276,14 @@ architecture struct of xwrc_board_svec is
signal clk_pll_dmtd : std_logic;
signal pll_locked : std_logic;
signal clk_10m_ext : std_logic;
signal clk_pll_aux : std_logic;
signal clk_pll_aux : std_logic_vector(3 downto 0);
-- Reset logic
signal areset_edge_ppulse : std_logic;
signal rst_62m5_n : std_logic;
signal rstlogic_arst : std_logic;
signal rstlogic_clk_in : std_logic_vector(2 downto 0);
signal rstlogic_rst_out : std_logic_vector(2 downto 0);
signal rstlogic_clk_in : std_logic_vector(5 downto 0);
signal rstlogic_rst_out : std_logic_vector(5 downto 0);
-- PLL DAC ARB
signal dac_sync_n : std_logic_vector(1 downto 0);
......@@ -327,7 +329,7 @@ begin -- architecture struct
g_fpga_family => "spartan6",
g_with_external_clock_input => g_with_external_clock_input,
g_use_default_plls => TRUE,
g_aux_pll_config => g_aux_pll_config,
g_aux_pll_cfg => g_aux_pll_cfg,
g_simulation => g_simulation)
port map (
areset_n_i => areset_n_i,
......@@ -364,8 +366,8 @@ begin -- architecture struct
-- Reset logic
-----------------------------------------------------------------------------
-- Detect when areset_edge_n_i goes high (end of reset) and use this edge to
-- generate rstlogic_arst_n. This is needed to connect optional reset like PCIe
-- reset. When board runs standalone, we need to ignore PCIe reset being
-- generate rstlogic_arst. This is needed to connect optional reset like PCIe
-- reset. When baord runs standalone, we need to ignore PCIe reset being
-- constantly low.
cmp_arst_edge : gc_sync_ffs
generic map (
......@@ -380,13 +382,13 @@ begin -- architecture struct
rstlogic_arst <= (not pll_locked) and (not areset_n_i) and areset_edge_ppulse;
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in(0) <= clk_pll_62m5;
rstlogic_clk_in(1) <= clk_pll_125m;
rstlogic_clk_in(2) <= clk_pll_aux;
rstlogic_clk_in(0) <= clk_pll_62m5;
rstlogic_clk_in(1) <= clk_pll_125m;
rstlogic_clk_in(5 downto 2) <= clk_pll_aux;
cmp_rstlogic_reset : gc_reset_multi_aasd
generic map (
g_CLOCKS => 3, -- 62.5MHz, 125MHz, plus aux clk
g_CLOCKS => 6, -- 62.5MHz, 125MHz, + 4x pll_aux
g_RST_LEN => 16) -- 16 clock cycles
port map (
arst_i => rstlogic_arst,
......@@ -398,7 +400,7 @@ begin -- architecture struct
rst_sys_62m5_n_o <= rst_62m5_n;
rst_ref_125m_n_o <= rstlogic_rst_out(1);
rst_pll_aux_n_o <= rstlogic_rst_out(2);
rst_pll_aux_n_o <= rstlogic_rst_out(5 downto 2);
-----------------------------------------------------------------------------
-- 2x SPI DAC
......@@ -433,6 +435,7 @@ begin -- architecture struct
cmp_board_common : xwrc_board_common
generic map (
g_simulation => g_simulation,
g_verbose => g_verbose,
g_with_external_clock_input => g_with_external_clock_input,
g_board_name => "SVEC",
g_flash_secsz_kb => 256, -- default for M25P128
......
Subproject commit 556e4c16302532ac5cb60150c18add695ea1b337
Subproject commit f73bc3d2959bdaab52adf910d99ed90cabab11ab
Subproject commit 10cd74b06a094c5b6c1a566676785e1814001404
Subproject commit b57528861e0ee8351b87dc3d4ec4da6a118b4a48
......@@ -13,5 +13,7 @@ modules = {
"wr_tlu",
"wrc_core",
"wr_streamers",
"wr_nic",
"wr_txtsu",
]
}
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......@@ -3,5 +3,7 @@ files = ["dmtd_phase_meas.vhd",
"multi_dmtd_with_deglitcher.vhd",
"hpll_period_detect.vhd",
"pulse_gen.vhd",
"pulse_stamper.vhd" ]
"oserdes_4_to_1.vhd",
"pulse_stamper.vhd",
"pulse_stamper_sync.vhd",
"dmtd_sampler.vhd" ]
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......@@ -84,6 +84,31 @@ architecture rtl of pulse_stamper is
signal pulse_sys_p1 : std_logic;
signal pulse_back : std_logic_vector(2 downto 0);
-- One of two clocks is used in WR for timestamping: 125MHz or 62.5MHz
-- This functions translates the cycle count into 125MHz-clock cycles
-- in the case when 62.5MHz clock is used. As a result, timestamps are
-- always in the same "clock domain". This is important, e.g. for streamers,
-- in applicatinos where one WR Node works with 62.5MHz WR clock and
-- another in 125MHz.
function f_8ns_cycle_cnt (in_cyc: std_logic_vector; ref_clk: integer)
return std_logic_vector is
variable out_cyc : std_logic_vector(27 downto 0);
begin
if (ref_clk = 125000000) then
out_cyc := in_cyc;
elsif(ref_clk = 62500000) then
out_cyc := in_cyc(26 downto 0) & '0';
else
assert FALSE report
"The only ref_clk_rate supported: 62.5MHz and 125MHz"
severity FAILURE;
end if;
return out_cyc;
end f_8ns_cycle_cnt;
begin -- architecture rtl
-- Synchronization of external pulse into the clk_ref_i clock domain
......@@ -150,7 +175,7 @@ begin -- architecture rtl
tag_valid_o <= '0';
elsif pulse_sys_p1='1' then
tag_tai_o <= tag_utc_ref;
tag_cycles_o <= tag_cycles_ref;
tag_cycles_o <= f_8ns_cycle_cnt(tag_cycles_ref,g_ref_clk_rate);
tag_valid_o <= '1';
else
tag_valid_o <='0';
......
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files = [
"spec_serial_dac_arb.vhd",
"spec_serial_dac.vhd"
"spec_serial_dac.vhd",
"cute_serial_dac_arb.vhd",
"cute_serial_dac.vhd"
]
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