...
 
Commits (2)
......@@ -151,6 +151,7 @@ package wr_board_pkg is
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic := '0';
pll_clk_sel_o : out std_logic;
phy8_o : out t_phy_8bits_from_wrc;
phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
phy16_o : out t_phy_16bits_from_wrc;
......
......@@ -128,7 +128,10 @@ entity xwrc_board_common is
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic;
-- SPEC7 Select clk_sys source (either always running clk_dmtd or
-- 125 MHz from AD9516 after PLL initialisation.)
pll_clk_sel_o : out std_logic;
---------------------------------------------------------------------------
-- PHY I/f
---------------------------------------------------------------------------
......@@ -426,6 +429,7 @@ begin -- architecture struct
pll_reset_n_o => pll_reset_n_o,
pll_refsel_o => pll_refsel_o,
pll_lock_i => pll_lock_i,
pll_clk_sel_o => pll_clk_sel_o,
phy_ref_clk_i => '0',
phy_tx_data_o => open,
phy_tx_k_o => open,
......
......@@ -271,6 +271,7 @@ architecture struct of xwrc_board_spec7 is
-- IBUFDS
signal clk_125m_dmtd_buf : std_logic;
signal clk_sys_62m5 : std_logic;
signal clk_dmtd : std_logic;
-- PLLs, clocks
......@@ -278,6 +279,7 @@ architecture struct of xwrc_board_spec7 is
signal clk_ref_62m5 : std_logic;
signal pll_locked : std_logic;
signal clk_10m_ext : std_logic;
signal pll_clk_sel : std_logic;
-- Reset logic
signal areset_edge_ppulse : std_logic;
......@@ -353,8 +355,18 @@ begin -- architecture struct
ext_ref_mul_stopped_o => ext_ref_mul_stopped,
ext_ref_rst_i => ext_ref_rst);
-- The AD9516 on the SPEC7 needs to be initialized before it outputs
-- clk_125m_gtx_p/n_i (which is
clk_sys_62m5_o <= clk_pll_62m5;
cmp_bufgmux: BUFGMUX
port map (
O => clk_sys_62m5,
I0 => clk_dmtd,
I1 => clk_pll_62m5,
S => pll_clk_sel
);
clk_sys_62m5_o <= clk_sys_62m5;
clk_ref_62m5_o <= clk_ref_62m5;
-----------------------------------------------------------------------------
......@@ -368,16 +380,21 @@ begin -- architecture struct
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_pll_62m5,
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => areset_edge_n_i,
ppulse_o => areset_edge_ppulse);
-- logic AND of all async reset sources (active low)
rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse);
-- Note: pll_locked = pll_dmtd_locked and pll_sys_locked. SPEC7 uses
-- direct_dmtd thus pll_dmtd_locked is always '1'. SPEC7 initial clk_sys_62m5
-- is clk_dmtd (selected by BUFGMUX) and clk_pll_62m5 is not yet driven by AD9516
-- so pll_sys_locked = '0' and can't be used for synchronous reset generation.
--rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse);
rstlogic_arst_n <= areset_n_i and (not areset_edge_ppulse);
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in(0) <= clk_pll_62m5;
rstlogic_clk_in(0) <= clk_sys_62m5;
rstlogic_clk_in(1) <= clk_ref_62m5;
cmp_rstlogic_reset : gc_reset
......@@ -408,7 +425,7 @@ begin -- architecture struct
g_num_cs_select => 1,
g_sclk_polarity => 0)
port map (
clk_i => clk_pll_62m5,
clk_i => clk_sys_62m5,
rst_n_i => rst_62m5_n,
value_i => dac_dmtd_data,
cs_sel_i => "1",
......@@ -425,7 +442,7 @@ begin -- architecture struct
g_num_cs_select => 1,
g_sclk_polarity => 0)
port map (
clk_i => clk_pll_62m5,
clk_i => clk_sys_62m5,
rst_n_i => rst_62m5_n,
value_i => dac_refclk_data,
cs_sel_i => "1",
......@@ -467,7 +484,7 @@ begin -- architecture struct
g_fabric_iface => g_fabric_iface
)
port map (
clk_sys_i => clk_pll_62m5,
clk_sys_i => clk_sys_62m5,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_ref_62m5,
clk_aux_i => clk_aux_i,
......@@ -491,6 +508,7 @@ begin -- architecture struct
pll_reset_n_o => pll_reset_n_o,
pll_refsel_o => pll_refsel_o,
pll_lock_i => pll_lock_i,
pll_clk_sel_o => pll_clk_sel,
phy16_o => phy16_from_wrc,
phy16_i => phy16_to_wrc,
scl_o => eeprom_scl_o,
......
......@@ -149,6 +149,9 @@ entity wr_core is
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic;
-- SPEC7 Select clk_sys source (either always running clk_dmtd or
-- 125 MHz from AD9516 after PLL initialisation.)
pll_clk_sel_o : out std_logic;
-- PHY I/f
phy_ref_clk_i : in std_logic;
......@@ -952,6 +955,7 @@ begin
pll_reset_n_o => pll_reset_n_o,
pll_refsel_o => pll_refsel_o,
pll_lock_i => pll_lock_i,
pll_clk_sel_o => pll_clk_sel_o,
slave_i => periph_slave_i,
slave_o => periph_slave_o,
......
......@@ -96,6 +96,9 @@ entity wrc_periph is
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic;
-- SPEC7 Select clk_sys source (either always running clk_dmtd or
-- 125 MHz from AD9516 after PLL initialisation.)
pll_clk_sel_o : out std_logic;
slave_i : in t_wishbone_slave_in_array(0 to 4);
slave_o : out t_wishbone_slave_out_array(0 to 4);
......@@ -552,11 +555,19 @@ begin
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(sysc_regs_o.gpsr_pll_reset_o = '1') then
pll_reset_n_o <= '0';
elsif(sysc_regs_o.gpcr_pll_reset_o = '1') then
pll_reset_n_o <= '1';
end if;
if(sysc_regs_o.gpsr_pll_clk_sel_o = '1') then
pll_clk_sel_o <= '0';
elsif(sysc_regs_o.gpcr_pll_clk_sel_o = '1') then
pll_clk_sel_o <= '1';
end if;
sysc_regs_i.gpsr_pll_lock_i <= pll_lock_i;
sysc_regs_i.gpsr_pll_status_i <= pll_status_i;
end if;
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : 10/30/19 09:08:37
-- Created : 11/22/19 16:40:26
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -103,6 +103,7 @@ package sysc_wbgen2_pkg is
gpsr_spi_mosi_o : std_logic;
gpsr_spi_mosi_load_o : std_logic;
gpsr_pll_reset_o : std_logic;
gpsr_pll_clk_sel_o : std_logic;
gpcr_led_stat_o : std_logic;
gpcr_led_link_o : std_logic;
gpcr_fmc_scl_o : std_logic;
......@@ -113,6 +114,7 @@ package sysc_wbgen2_pkg is
gpcr_spi_cs_o : std_logic;
gpcr_spi_mosi_o : std_logic;
gpcr_pll_reset_o : std_logic;
gpcr_pll_clk_sel_o : std_logic;
tcr_enable_o : std_logic;
diag_cr_adr_o : std_logic_vector(15 downto 0);
diag_cr_adr_load_o : std_logic;
......@@ -164,6 +166,7 @@ package sysc_wbgen2_pkg is
gpsr_spi_mosi_o => '0',
gpsr_spi_mosi_load_o => '0',
gpsr_pll_reset_o => '0',
gpsr_pll_clk_sel_o => '0',
gpcr_led_stat_o => '0',
gpcr_led_link_o => '0',
gpcr_fmc_scl_o => '0',
......@@ -174,6 +177,7 @@ package sysc_wbgen2_pkg is
gpcr_spi_cs_o => '0',
gpcr_spi_mosi_o => '0',
gpcr_pll_reset_o => '0',
gpcr_pll_clk_sel_o => '0',
tcr_enable_o => '0',
diag_cr_adr_o => (others => '0'),
diag_cr_adr_load_o => '0',
......
......@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : 10/30/19 09:08:37
* Created : 11/22/19 16:40:26
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -95,6 +95,9 @@
/* definitions for field: PLL_STATUS in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_PLL_STATUS WBGEN2_GEN_MASK(16, 1)
/* definitions for field: PLL_CLK_SEL in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_PLL_CLK_SEL WBGEN2_GEN_MASK(17, 1)
/* definitions for register: GPIO Clear Register */
/* definitions for field: Status LED in reg: GPIO Clear Register */
......@@ -127,6 +130,9 @@
/* definitions for field: PLL_RESET in reg: GPIO Clear Register */
#define SYSC_GPCR_PLL_RESET WBGEN2_GEN_MASK(14, 1)
/* definitions for field: PLL_CLK_SEL in reg: GPIO Clear Register */
#define SYSC_GPCR_PLL_CLK_SEL WBGEN2_GEN_MASK(17, 1)
/* definitions for register: Hardware Feature Register */
/* definitions for field: Memory size in reg: Hardware Feature Register */
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_wb.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : 10/30/19 09:08:37
-- Created : 11/22/19 16:40:26
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -46,6 +46,8 @@ signal sysc_gpsr_net_rst_dly0 : std_logic ;
signal sysc_gpsr_net_rst_int : std_logic ;
signal sysc_gpsr_pll_reset_dly0 : std_logic ;
signal sysc_gpsr_pll_reset_int : std_logic ;
signal sysc_gpsr_pll_clk_sel_dly0 : std_logic ;
signal sysc_gpsr_pll_clk_sel_int : std_logic ;
signal sysc_gpcr_led_stat_dly0 : std_logic ;
signal sysc_gpcr_led_stat_int : std_logic ;
signal sysc_gpcr_led_link_dly0 : std_logic ;
......@@ -66,6 +68,8 @@ signal sysc_gpcr_spi_mosi_dly0 : std_logic ;
signal sysc_gpcr_spi_mosi_int : std_logic ;
signal sysc_gpcr_pll_reset_dly0 : std_logic ;
signal sysc_gpcr_pll_reset_int : std_logic ;
signal sysc_gpcr_pll_clk_sel_dly0 : std_logic ;
signal sysc_gpcr_pll_clk_sel_int : std_logic ;
signal sysc_tcr_enable_int : std_logic ;
signal sysc_diag_cr_rw_int : std_logic ;
signal sysc_wdiag_ctrl_data_valid_int : std_logic ;
......@@ -129,6 +133,7 @@ begin
regs_o.gpsr_spi_ncs_load_o <= '0';
regs_o.gpsr_spi_mosi_load_o <= '0';
sysc_gpsr_pll_reset_int <= '0';
sysc_gpsr_pll_clk_sel_int <= '0';
sysc_gpcr_led_stat_int <= '0';
sysc_gpcr_led_link_int <= '0';
sysc_gpcr_fmc_scl_int <= '0';
......@@ -139,6 +144,7 @@ begin
sysc_gpcr_spi_cs_int <= '0';
sysc_gpcr_spi_mosi_int <= '0';
sysc_gpcr_pll_reset_int <= '0';
sysc_gpcr_pll_clk_sel_int <= '0';
sysc_tcr_enable_int <= '0';
regs_o.diag_cr_adr_load_o <= '0';
sysc_diag_cr_rw_int <= '0';
......@@ -182,6 +188,7 @@ begin
regs_o.gpsr_spi_ncs_load_o <= '0';
regs_o.gpsr_spi_mosi_load_o <= '0';
sysc_gpsr_pll_reset_int <= '0';
sysc_gpsr_pll_clk_sel_int <= '0';
sysc_gpcr_led_stat_int <= '0';
sysc_gpcr_led_link_int <= '0';
sysc_gpcr_fmc_scl_int <= '0';
......@@ -192,6 +199,7 @@ begin
sysc_gpcr_spi_cs_int <= '0';
sysc_gpcr_spi_mosi_int <= '0';
sysc_gpcr_pll_reset_int <= '0';
sysc_gpcr_pll_clk_sel_int <= '0';
regs_o.diag_cr_adr_load_o <= '0';
regs_o.diag_dat_load_o <= '0';
ack_in_progress <= '0';
......@@ -262,6 +270,7 @@ begin
regs_o.gpsr_spi_ncs_load_o <= '1';
regs_o.gpsr_spi_mosi_load_o <= '1';
sysc_gpsr_pll_reset_int <= wrdata_reg(14);
sysc_gpsr_pll_clk_sel_int <= wrdata_reg(17);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
......@@ -280,7 +289,7 @@ begin
rddata_reg(14) <= '0';
rddata_reg(15) <= regs_i.gpsr_pll_lock_i;
rddata_reg(16) <= regs_i.gpsr_pll_status_i;
rddata_reg(17) <= 'X';
rddata_reg(17) <= '0';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
......@@ -309,6 +318,7 @@ begin
sysc_gpcr_spi_cs_int <= wrdata_reg(11);
sysc_gpcr_spi_mosi_int <= wrdata_reg(12);
sysc_gpcr_pll_reset_int <= wrdata_reg(14);
sysc_gpcr_pll_clk_sel_int <= wrdata_reg(17);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
......@@ -320,6 +330,7 @@ begin
rddata_reg(11) <= '0';
rddata_reg(12) <= '0';
rddata_reg(14) <= '0';
rddata_reg(17) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -825,6 +836,19 @@ begin
-- PLL_LOCK
-- PLL_STATUS
-- PLL_CLK_SEL
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
sysc_gpsr_pll_clk_sel_dly0 <= '0';
regs_o.gpsr_pll_clk_sel_o <= '0';
elsif rising_edge(clk_sys_i) then
sysc_gpsr_pll_clk_sel_dly0 <= sysc_gpsr_pll_clk_sel_int;
regs_o.gpsr_pll_clk_sel_o <= sysc_gpsr_pll_clk_sel_int and (not sysc_gpsr_pll_clk_sel_dly0);
end if;
end process;
-- Status LED
process (clk_sys_i, rst_n_i)
begin
......@@ -955,6 +979,19 @@ begin
end process;
-- PLL_CLK_SEL
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
sysc_gpcr_pll_clk_sel_dly0 <= '0';
regs_o.gpcr_pll_clk_sel_o <= '0';
elsif rising_edge(clk_sys_i) then
sysc_gpcr_pll_clk_sel_dly0 <= sysc_gpcr_pll_clk_sel_int;
regs_o.gpcr_pll_clk_sel_o <= sysc_gpcr_pll_clk_sel_int and (not sysc_gpcr_pll_clk_sel_dly0);
end if;
end process;
-- Memory size
-- Storage type
-- Storage sector size
......
......@@ -204,6 +204,14 @@ peripheral {
load = LOAD_EXT;
align = 16;
};
field {
name = "PLL_CLK_SEL";
prefix = "pll_clk_sel";
description = "write 1: SPEC7, Select clk_sys source from AD9516";
type = MONOSTABLE;
align = 17;
};
};
reg {
......@@ -287,6 +295,14 @@ peripheral {
type = MONOSTABLE;
align = 14;
};
field {
name = "PLL_CLK_SEL";
prefix = "pll_clk_sel";
description = "write 1: SPEC7, Select clk_sys source from free running clk_dmtd";
type = MONOSTABLE;
align = 17;
};
};
reg {
......
......@@ -287,6 +287,7 @@ package wrcore_pkg is
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic;
pll_clk_sel_o : out std_logic;
slave_i : in t_wishbone_slave_in_array(0 to 4);
slave_o : out t_wishbone_slave_out_array(0 to 4);
uart_rxd_i : in std_logic;
......@@ -420,7 +421,8 @@ package wrcore_pkg is
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic := '0';
pll_clk_sel_o : out std_logic;
-----------------------------------------
-- PHY I/f
-----------------------------------------
......@@ -648,6 +650,7 @@ package wrcore_pkg is
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic := '0';
pll_clk_sel_o : out std_logic;
-----------------------------------------
--UART
......
......@@ -149,6 +149,9 @@ entity xwr_core is
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic;
-- SPEC7 Select clk_sys source (either always running clk_dmtd or
-- 125 MHz from AD9516 after PLL initialisation.)
pll_clk_sel_o : out std_logic;
-----------------------------------------
-- PHY I/f
......@@ -340,6 +343,7 @@ begin
pll_reset_n_o => pll_reset_n_o,
pll_refsel_o => pll_refsel_o,
pll_lock_i => pll_lock_i,
pll_clk_sel_o => pll_clk_sel_o,
phy_ref_clk_i => phy_ref_clk_i,
phy_tx_data_o => phy_tx_data_o,
......
......@@ -38,6 +38,8 @@
`define SYSC_GPSR_PLL_LOCK 32'h00008000
`define SYSC_GPSR_PLL_STATUS_OFFSET 16
`define SYSC_GPSR_PLL_STATUS 32'h00010000
`define SYSC_GPSR_PLL_CLK_SEL_OFFSET 17
`define SYSC_GPSR_PLL_CLK_SEL 32'h00020000
`define ADDR_SYSC_GPCR 7'h8
`define SYSC_GPCR_LED_STAT_OFFSET 0
`define SYSC_GPCR_LED_STAT 32'h00000001
......@@ -59,6 +61,8 @@
`define SYSC_GPCR_SPI_MOSI 32'h00001000
`define SYSC_GPCR_PLL_RESET_OFFSET 14
`define SYSC_GPCR_PLL_RESET 32'h00004000
`define SYSC_GPCR_PLL_CLK_SEL_OFFSET 17
`define SYSC_GPCR_PLL_CLK_SEL 32'h00020000
`define ADDR_SYSC_HWFR 7'hc
`define SYSC_HWFR_MEMSIZE_OFFSET 0
`define SYSC_HWFR_MEMSIZE 32'h0000000f
......
......@@ -147,6 +147,8 @@ entity spec7_write_top is
led_link_o : out std_logic;
reset_n_i : in std_logic;
suicide_n_o : out std_logic;
wdog_n_o : out std_logic;
------------------------------------------------------------------------------
-- Digital I/O Bulls-Eye connections
......@@ -273,6 +275,10 @@ architecture top of spec7_write_top is
begin -- architecture top
-- Never trigger PS_POR or PROGRAM_B
suicide_n_o <= '1';
wdog_n_o <= '1';
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master)
-----------------------------------------------------------------------------
......
......@@ -182,6 +182,13 @@ set_property IOSTANDARD LVCMOS25 [get_ports led_pps]
set_property PACKAGE_PIN AA20 [get_ports reset_n_i]
set_property IOSTANDARD LVCMOS25 [get_ports reset_n_i]
# Suicide & Watchdog
# Bank 13 (HR) VCCO - 2.5 V
set_property PACKAGE_PIN AC22 [get_ports suicide_n_o]
set_property IOSTANDARD LVCMOS25 [get_ports suicide_n_o]
set_property PACKAGE_PIN AC21 [get_ports wdog_n_o]
set_property IOSTANDARD LVCMOS25 [get_ports wdog_n_o]
# SI570
# Bank 12 (HR) VCCO - 2.5 V
#set_property PACKAGE_PIN AD14 [get_ports si570_clk_n]
......