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Avoid the generation of a latch during synthesis

Peter Jansweijer requested to merge peter_vivado_critical_warning into wrpc-v5

Vivado reports a critical warning "unconstrained_internal_endpoints". This is due to the fact that a latch (primitive LDCE, see Branch_peter_vivado_critical_warning.pdf) is inferred so there is no timing check path from the input signals to the next flip-flop clocked with clk_sys_i.

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