• Peter Jansweijer's avatar
    clbv2 reference design files · d2f24245
    Peter Jansweijer authored
    added clbv2_ref_design files
    added initial clbv2_ref_design ucf file
    removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization
    removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization, phy16
    Merge branch 'peter_clbv2_ref_design' of ohwr.org:hdl-core-lib/wr-cores into peter_clbv2_ref_design
    clk_20m_vcxo_i free running clock for reset gen. (thus no need for separate 125 MHz fpga input; remove clk_125m_pllref_p/n_i)
    updates kintex7 phy name to reflect new peter_xilinx_phys convention
    last commit also needs artix7 support in xwrc_platform_xilinx.vhd
    CLBv2: reference clock is 62.5 MHz for 16 bit PHYs. Changed naming convention accordingly.
    CLBv2: point proper bram file
    CLBv2: implementation (including bmm)
    CLBv2 reference design cleaned
    CLBv2: updated (hdlmake made) Xilinx ISE project file
    d2f24245
Name
Last commit
Last update
bin Loading commit data...
board Loading commit data...
ip_cores Loading commit data...
modules Loading commit data...
platform Loading commit data...
sim Loading commit data...
syn Loading commit data...
testbench Loading commit data...
top Loading commit data...
.gitignore Loading commit data...
.gitmodules Loading commit data...
Manifest.py Loading commit data...