WhiteRabbit PTP core on VFC-HD
The WhiteRabbit (WR) PTP core project provides support for the VFC-HD board, an FMC carrier board based on an Arria V FPGA from Altera.
By using this module, the user gains the benefit of instantiating all the necessary components of the WR PTP core (including the core itself, the PHY, PLLs, etc.) in one go, without having to delve into the implementation details, using a setup that has been tested and is known to work well on the VFC-HD board.
For users who need more control and flexibility over the process, it is suggested to use this code as a reference, and to consider using the Altera Arria V platform (which is also used internally in this module) for instantiating the PHY and (optionally) the PLLs.
Gateware
The main ingredient of the WR PTP core is the FPGA gateware. The WR PTP core in the form of a parametrisable VHDL module, to be instantiated in your own design.
Getting it
The FPGA gateware is available on the dlamprid-vfchd branch of the wr-cores repository (soon to be merged in proposed_master branch).
To get it, use:
git clone -b dlamprid-vfchd git:https://www.ohwr.org/hdl-core-lib/wr-cores.git
cd wr-cores; git submodule update --init
Using it
The top-level VHDL module, which you can include in your own VFC-HD project, is located under board/vfchd/xwrc_board_vfchd.vhd. A VHDL package with the definition of the module can be found under board/wr_board_pkg.vhd.
Module Generics
There are five generics provided for the parametrisation of the module.
name | type | default | description |
g_simulation | integer | 0 | This can be set to 1 to enable faster simulation, by speeding up some of the initialisation processes. |
g_pcs16_bit | boolean | false | The VFC-HD makes use of the Altera Arria V platform for WhiteRabbit, which provides the possibility to configure the PCS of the PHY either as 8bit or 16bit. The default is to use the 8bit PCS, but this generic can be used to override it. |
g_fabric_iface | string | "plain" | The WR PTP core provides a fabric" interface towards the FPGA. The default value for this generic will leave the fabric interface as is. If instead it is set to "streamers", a WhiteRabbit streamer module will be attached to it. In the future, it is foreseen to have a third option here, for instantiating an "Etherbone core. |
g_streamer_width | integer | 32 | In case g_fabric_iface = "streamers" , then this generic defines the data width for the streamer interface. Otherwise, it is ignored. |
g_dpram_initf | string | "default" | This generic can point to the path of the Altera memory initialisation file (.mif) containing the software binary for the embedded CPU of the WR PTP core. If provided, it will be included in the final FPGA bitstream and the embedded CPU will be properly initialised every time the FPGA is programmed with the bitstream. |
Module Ports
The following table lists all the input/output ports of the module. Note
that depending on the values of the module generics (g_fabric_iface
in
particular), not all ports are required.
name | direction | type | description |
Clocks/resets | |||
clk_board_125m_i | in | std_logic | 125 MHz clock input from the VFC-HD board (OSC2 output). |
clk_board_20m_i | in | std_logic | 20 MHz clock input from the VFC-HD board (OSC3 output). |
areset_n_i | in | std_logic | Reset input, active low. Can be asynchronous.) |
clk_sys_62m5_o | out | std_logic | 62.5MHz system clock output. |
clk_ref_125m_o | out | std_logic | 125MHz WR reference clock output. |
rst_sys_62m5_o | out | std_logic | Active high reset output, synchronous to clk_sys_62m5_o. |
SPI interfaces to DACs | |||
dac_ref_sync_n_o | out | std_logic | SPI CSn for main (ref) VCXO |
dac_dmtd_sync_n_o | out | std_logic | SPI CSn for helper (DMTD) VCXO |
dac_din_o | out | std_logic | SPI MOSI |
dac_sclk_o | out | std_logic | SPI CLK |
SFP I/O for transceiver and SFP management info from VFC-HD | |||
sfp_tx_o | out | std_logic | SFP TX |
sfp_rx_i | in | std_logic | SFP RX |
sfp_det_valid_i | in | std_logic |
High if both of the following are true: 1. SFP is detected (plugged in) 2. The part number has been successfully read after the SFP detection |
sfp_data_i | in | std_logic_vector | The VFC-HD board implements I2C multiplexers to provide access to the numerous SFP interfaces (as well as other I2C-controlled peripherals). The VFC-HD project provides an additional module (in Verilog) which takes care of accessing the SFP information and making it available to the WR PTP code, in the form of a 16 byte vendor Part Number (128 bits std_logic_vector, ASCII encoded, first character byte in bits 127 downto 120). |
I2C EEPROM | |||
eeprom_sda_b | inout | std_logic | Bidirectional I2C SDA line. |
eeprom_scl_o | out | std_logic | Normally, this should also be bidirectional, but VFC-HD defines SCL as output, which works because the EEPROM is the only device connected on this I2C bus. |
Onewire interface | |||
onewire_i | in | std_logic | Data input from the onewire interface. |
onewire_oen_o | out | std_logic | Output enable to the onewire interface. When this is asserted, the instantiating module should drive the onewire data output to ground. |
External WB interface | |||
wb_adr_i | in | std_logic_vector | Wishbone slave interface, operating in "Pipelined" mode, with word granularity. It provides access to all the Wishbone peripherals inside the WR PTP core. VHDL records are not used here, to facilitate integration of the module into Verilog-based projects (such as the VFC-HD). |
wb_dat_i | in | std_logic_vector | |
wb_dat_o | out | std_logic_vector | |
wb_sel_i | in | std_logic_vector | |
wb_we_i | in | std_logic | |
wb_cyc_i | in | std_logic | |
wb_stb_i | in | std_logic | |
wb_ack_o | out | std_logic | |
wb_int_o | out | std_logic | |
wb_err_o | out | std_logic | |
wb_rty_o | out | std_logic | |
wb_stall_o | out | std_logic | |
WR fabric interface | |||
wrf_src_adr_o | out | std_logic_vector | Pipelined Wishbone master interface. It passes all the Ethernet frames received from a physical link to a slave interface implemented in a user-defined module. VHDL records are not used here, to facilitate integration of the module into Verilog-based projects (such as the VFC-HD). |
wrf_src_dat_o | out | std_logic_vector | |
wrf_src_cyc_o | out | std_logic | |
wrf_src_stb_o | out | std_logic | |
wrf_src_we_o | out | std_logic | |
wrf_src_sel_o | out | std_logic_vector | |
wrf_src_ack_i | in | std_logic | |
wrf_src_stall_i | in | std_logic | |
wrf_src_err_i | in | std_logic | |
wrf_src_rty_i | in | std_logic | |
wrf_snk_adr_i | in | std_logic_vector | Pipelined Wishbone slave interface. It receives Ethernet frames from a master interface implemented in a user-defined module, and sends them to a physical link. VHDL records are not used here, to facilitate integration of the module into Verilog-based projects (such as the VFC-HD). |
wrf_snk_dat_i | in | std_logic_vector | |
wrf_snk_cyc_i | in | std_logic | |
wrf_snk_stb_i | in | std_logic | |
wrf_snk_we_i | in | std_logic | |
wrf_snk_sel_i | in | std_logic_vector | |
wrf_snk_ack_o | out | std_logic | |
wrf_snk_stall_o | out | std_logic | |
wrf_snk_err_o | out | std_logic | |
wrf_snk_rty_o | out | std_logic | |
WR streamers | |||
wrs_tx_data_i | in | std_logic_vector | Data word to be sent over the physical link. The width of the vector is equal to g_streamer_width parameter. |
wrs_tx_valid_i | in | std_logic | An '1' indicates that the tx_data_i contains a valid data word. |
wrs_tx_dreq_o | out | std_logic | Synchronous data request: when '1', the user may send a data word in the following clock cycle. |
wrs_tx_last_i | in | std_logic | An '1' indicates the last data word in a larger block of samples. |
wrs_tx_flush_i | in | std_logic | When asserted, the streamer will immediately send out all the data that is stored in its TX buffer. |
wrs_rx_first_o | out | std_logic | An '1' indicates the first data word of the data block on wrs_rx_data_o. |
wrs_rx_last_o | out | std_logic | An '1' indicates the last data word of the data block on wrs_rx_data_o. |
wrs_rx_data_o | out | std_logic_vector | Data word received from the physical link. The width of the vector is equal to g_streamer_width parameter. |
wrs_rx_valid_o | out | std_logic | An '1' indicates that rx_data_o is outputting a valid data word. |
wrs_rx_dreq_i | in | std_logic | Synchronous data request input: when '1', the streamer may output another data word in the subsequent clock cycle. |
WRPC timing interface and status | |||
pps_p_o | out | std_logic | 1-PPS (Pulse Per Second) signal generated in the clk_ref_125m_o clock domain and aligned to WR time, pulse generated when the cycle counter is 0 (beginning of each full TAI second). |
tm_time_valid_o | out | std_logic | If 1, the timecode generated by the WRPC is valid. |
tm_tai_o | out | std_logic_vector | TAI part of the timecode (40 bits). |
tm_cycles_o | out | std_logic_vector | Fractional part of each second represented by the state of counter clocked with the frequency 125 MHz (values from 0 to 124999999, each count is 8 ns). |
led_link_o | out | std_logic | signal for driving Ethernet Link LED. |
led_act_o | out | std_logic | signal for driving Ethernet Act LED. |
Software for the embedded CPU of the WR PTP core
The WR PTP core also instantiates an embedded softcore CPU (LM32), which requires its own software for proper operation.
Getting it
The embedded software for the WR PTP core is available on the eeprom_scan branch of the wrpc-sw repository (soon to be merged in proposed_master branch).
To get it, use:
git clone -b eeprom_scan git:https://www.ohwr.org/hdl-core-lib/wr-cores/wrpc-sw.git
cd wrpc-sw; git submodule update --init
Using it
Building and running the embedded software is described in the White Rabbit PTP Core User's Manual.
The embedded software can be built with the default settings, although it might be beneficial for testing and debugging to enable IP support (CONFIG_IP option), SNMP (SNMP option) and the auxiliary diagnostics interface (CONFIG_AUX_DIAG option).
The resulting binary can be either added to your HDL design, or injected to the CPU during runtime.
Software tools
Several software tools are provided, to facilitate the programming and monitoring of the WR PTP core on the VFC-HD.
These software tools are available on the master branch of the VFC-HD repository.
To get them, use:
git clone https://gitlab.cern.ch/dlamprid/VFC-HD.git
The tools themselves are located in the Sw/WrPtp
folder of the
repository.
A Makefile is provided for compiling the C sources on CERN Front-End
Computers. For other configurations, the only dependency for these tools
is on libvmebus
, which in turn depends on the vmebridge
kernel
driver (currently only supporting the TSI148 VME to PCI-X
bridge).
Both the driver and the library are available on the master branch of the vmebridge repository.
To get them, use:
git clone https://gitlab.cern.ch/cohtdrivers/vmebridge.git
The repository also includes documentation on the driver and the library.
Virtual UART
Sw/WrPtp/vfchd-uart.c
This tool provides access to the virtual UART of the WR PTP core. This is very useful for controlling and monitoring of the WR PTP core, since the VFC-HD does not provide a physical UART.
The tool expects one argument, the slot where the VFC-HD card is located inside the VME crate.
Embedded software loader
Sw/WrPtp/vfchd-wrc_loader.c
This tool allows the user to inject code to the WR PTP core embedded CPU during runtime.
The tool expects two arguments, the slot where the VFC-HD card is located inside the VME crate and the path to the software binary for the embedded CPU.
WR EEPROM loader
Sw/WrPtp/vfchd-eeprom_loader.c
This tool allows the user to write to the I2C EEPROM of the WR PTP core, which is used for storing calibration values, initialisation scripts, etc.
This tool is useful on a new VFC-HD board, or when the EEPROM is corrupt, in order to "format" it for use by the WR PTP core. Once the EEPROM has the proper format, the WR PTP core will automatically use it to read/write values. The user can also read/write values via the virtual UART.
The tool expects two arguments, the slot where the VFC-HD card is located inside the VME crate and the path to the EEPROM image to load. An empty image, ready to be written to the EEPROM with this tool, is available
Support
To get support for the integration of the WR PTP core into your VFC-HD application, you can reach the WR developers on the white-rabbit-dev mailing list.
To get support for the VFC-HD board itself you can use one of the contacts mentioned in the VFC-HD project wiki.
19 December 2016