Interface of Transmit and Receive Streamer modules
The Transmit and Receive Streamers are xtx_streamer.vhd and xrx_streamer.vhd located in modules/wr_streamers folder of wr-cores .
Transceiver configuration:
VHDL generics to specify Tx and Rx pair configuration:
-
Common to Tx and Rx
-
g_data_width
- Generic defines the width of input/output data in multiples of 16 bits (n*16). It must be identical for the Tx and Rx Streamer. -
g_escape_code_disable
- Generic, when it isTRUE
, the escape code is not used and only a single block can be sent. In this case, for the receiver to interpret such a frame correctly, it needs to have this same generic set to true, in addition to settingg_expected_words_number
generic to the expected number of words in the single block. -
g_tx_buffer_size
/g_rx_buffer_size
- Generic defines size of Tx/Rx buffer, in data words. In the case of the Tx streamer, it is recommended that this value exceeds 2*g_tx_threshold (Description to follow).
-
-
Tx specific
-
g_tx_threshold
- Generic defines minimum number of data words in the buffer of the Tx Streamer that will trigger transmission of an Ethernet Frame. -
g_tx_max_words_per_frame
- Generic defines maximum number of data words in a single Ethernet Frame. It also defines the maximum block size. The way this generic is currently implemented is explained in issue #1595. Test 4 of the simulation also shows how this generic behaves in practice. -
g_tx_timeout
- Generic defines transmission timeout (in clk_sys_i cycles), after which the content of the buffer in the Tx Streamer is sent regardless of the amount of data that is currently stored in the buffer, so that data in the buffer does not get stuck. -
g_simulation
andg_sim_startup_cnt
- Simulation specific generics. Used in order to avoid long simulation delays due to external module startup.
-
-
Rx specific
-
g_expected_words_number
- generic defines the number of words that is expected by the receiver. This is a legacy feature, when only a fixed number of words is ever received. By setting it to a non-zero value, and combined with setting theg_escape_code_disable
generic in both tx and rx toTRUE
, this feature can be enabled (Though not recommended).
-
Networking configuration (Tx and Rx Streamer):
Information on network configuration is provided in VHDL records,
respectively t_tx_streamer_cfg
and t_rx_streamer_cfg
. This interface
allows application-specific logic to provide network configuration
directly. This network configuration provided directly in the VHDL
records can be overriden by configuration provided in wishbone
registers, see wishbone memory
map
(External configuration).
t_tx_streamer_cfg
contains the following fields:
-
mac_local
- local MAC address. Leave at 0 when using with the WR MAC/Core, as it will insert its own source MAC. -
mac_target
- Destination MAC address from Tx module. -
ethertype
- Ethertype of streamer frames. Default value is accepted by the standard configuration of the WR PTP Core. -
qtag_ena
- Enables tagging with VLAN tags. -
qtag_vid
- The ID of the VLAN used to tag. -
qtag_prio
- Ethernet frame priority.
t_rx_streamer_cfg
contains:
-
mac_local
- Same description as in Tx. -
mac_remote
- Source MAC address to Rx module. -
ethertype
- Same description as in Tx. -
accept_broadcasts
- This is set to 1 if Rx must accept all broadcast packets, otherwise clear in order to accept only unicast packets. -
filter_remote
- Filtering source MAC adress of streamer frames on reception. 1 To accept packets from any source. 0 to accept only those from device specified inmac_remote
. -
fixed_latency
- Network latency can be configured to a fixed value. The receiver does not output received data until desired latency has elapsed to emulate a network with constant latency. Set to 0 to disable. The fixed network latency is ensured between
** the beginning of transmission of Ethernet frame (SOF) carrying WR Streamer words and
* the time the first word transported in this Etherent frame is
presented (rx_valid_
and rx_first_p1_o
are HIGH)
Note: The configured value of fixed network latency guarantees a
fixed latency internally (inside the FPGA) with a jitter of + /- one
clock cycle (+/-8ns). The latency observed by the application might see
a static offset to the configured value. During lab tests, when fixed
latency was measured from transmission to reception of BTrain frame, a
static offset of 30ns and 40ns was seen for two different FPGAs, when
observing the transmission latency on a scope. This static offset should
be repeatable and measurable (per board, per bitstream) and can be
accounted for during system calibration when a strict fixed-latency must
be
observed.
WR timing input (optional, to allow latency measurement, Tx and Rx Streamer):
-
clk_ref_i
- White Rabbit reference clock. -
tm_time_valid_i
- Time valid flag. -
tm_tai_i
- TAI seconds. -
tm_cycles_i
- Fractional part of the second (in number of clk_ref_i cycles). -
link_ok_i
- Status of the link, in principle the transmitter can be done only if link is OK.
FIFO-like interface (Tx and Rx Streamer):
-
The figure and tables below provide information on interfaces that are used to write data words to the Tx Streamer and read data words from the Rx Streamer.
-
These signal assertions are shown in a waveform example.
Tx Streamer*
| * I/F name | Description *|
| tx_data_i
| Input data word of generic width to be sent by the
Tx Streamer|
| tx_valid_i
| HIGH indicates that the tx_data_i contains a valid
data word* |
| tx_dreq_o
| Synchronous data request: HIGH indicates that the Tx
Streamer can accommodate a data word in the following clock cycle
|
| tx_last_p1_i
| Last data word signal. Asserted for 1 clock cycle
and indicates the last data word in a block |
| tx_flush_p1_i
| Flush input. When asserted for 1 clock cycle, the
streamer will immediately send out all the data that is stored in its TX
buffer, ignoring g_tx_timeout. |
| tx_reset_seq_i
| Reset sequence number. When asserted, the internal
sequence number generator used to detect loss of frames is reset to 0.
Advanced feature. |
| tx_frame_p1_o
| Asserted for one clock cycle to signify successful
streamer frame transmission. |
Rx Streamer*
| * I/F name | Description *|
| rx_dreq_i
| Synchronous data request input: when HIGH, the streamer
can output another data word in the subsequent clock cycle. |
| rx_data_o
| Output data word of a generic width received by the
Rx Streamer |
| rx_valid_o
| HIGH indicted that rx_data_o is outputting a valid
data word*. |
| rx_first_p1_o
| HIGH indicates the 1st data word of the
block* on rx_data_o. |
| rx_last_p1_o
| HIGH indicates the last word of the data block on
rx_data_o. |
| rx_frame_p1_o
| Asserted for one clock cycle to signify successful
streamer frame reception|
| rx_lost_p1_o
| Lost output: HIGH indicates that one or more
blocks* or frames have been lost. |
| rx_lost_blocks_p1_o
| Indicates that one or more blocks within one
frame are missing |
| rx_lost_frames_p1_o
| Indicates that one or more frames are missing,
the number of frames is provided |
| rx_lost_frames_cnt_o
| The number of lost frames. 0xF...F means that
the counter overflowed |
| rx_latency_o
| Latency measurement output: indicates the transport
latency (between the TX streamer in remote device and this streamer), in
clk_ref_i
clock cycles. |
| rx_latency_valid_o
| HIGH when the latency on rx_latency_o is
valid. |
More information:
- White Rabbit PTP Core Hands-on Training materials that uses WR Streamers (see these slides from day 1 and day 2)
- Applications:
23 May 2017