WR Forward Error Correction (FEC) core is responsible for reliable data
delivery by introducing redundancy into the data. We use concatenated
Reed-Solomon and Hamming codes.
FEC code is transparent to the other modules (between which it sits,
i.e. WRCore and EtherBone). It communicates with outside world with
pipelined Wishbone (WB) interface.
In fact, WR FEC core consists of two separate modules:
1. FEC encoder:
- It expects to receive Ethernet Frame (which size could be greater then standard). The max size of the input payload is to be decided, for the time being we assume max of 1500 bytes, but according to the "WR and robustenss" doc (www.ohwr.org/project/white-rabbit/wikis/Documents/White-Rabbit-and-Robustness:-Draft-for-Comments), it could be 5000 bytes
- It is activated by writing the size of the payload-to-be-encoded to appropriate WB address (parameter/to-be-decided) at the beginning of the data transfer.
- If not activated, input data is passed directly to the output.
- The architecture of the current implementation is depicted in the
figure - this is optimized for speed. However, the usage of RAM is
definitely not optimal
FECencoder.jpg!
2. FEC
decoder
-