Altera Arria V Platform Support (generics and ports)
Module Generics
There are four generics provided for the parametrisation of the module.
name | type | default | description |
---|---|---|---|
g_fpga_family | string | "arria5" | Define the family/model of Altera FPGA. Recognized values are "arria5" (more will be added). |
g_with_external_clock_input | boolean | false | Select whether to include the external 10MHz referece clock input (used in WR Grandmaster mode). |
g_use_default_plls | boolean | true | Set to FALSE if you want to instantiate your own PLLs. |
g_pcs16_bit | boolean | false | Some FPGA families provide the possibility to configure the PCS of the PHY either as 8bit or 16bit. The default is to use the 8bit PCS, but this generic can be used to override it. |
Module Ports
The following table lists all the input/output ports of the module. Note
that depending on the values of the module generics
(g_use_default_plls
and g_with_external_clock_input
in particular),
not all ports are required.
name | direction | type | description |
---|---|---|---|
Clocks/resets | |||
areset_n_i | in | std_logic | Reset input, active low. Can be asynchronous. |
clk_10m_ext_i | in | std_logic | External reference 10MHz clock input. |
clk_20m_i | in | std_logic | 20 MHz and 125MHz clock inputs to PLLs. |
clk_125m_i | in | std_logic | |
clk_62m5_dmtd_i | in | std_logic | 62.5MHz DMTD offset clock, controlled by helper DAC. |
62.5MHz Main system clock controlled by main DAC. | |||
125MHz Reference clock controlled by main DAC. |
| |clk_62m5_sys_i|in|std_logic| |clk_125m_ref_i|in|std_logic| |clk_125m_ext_mul_i|in|std_logic|125MHz derived from 10MHz external reference. | |SFP I/O for transceiver| |pad_tx_o|out|std_logic|SFP TX| |pad_rx_i|in|std_logic|SFP RX| |Interface to the WR PTP core: PLL outputs| |clk_62m5_sys_o|out|std_logic|62.5MHz clock output, to be connected to the clk_sys_i input of the WR PTP core| |clk_125m_ref_o|out|std_logic|125MHz clock output, to be connected to the clk_ref_i input of the WR PTP core| |clk_62m5_dmtd_o|out|std_logic|62.5MHz clock output, to be connected to the clk_dmtd_i input of the WR PTP core| |pll_locked_o|out|std_logic|PLL locked indication. This can be skipped if you are instantiating your own PLLs outside of the platform.| |Interface to the WR PTP core: PHY| |phy_ready_o|out|std_logic|All std_logic_vector widths depends on the value of the g_pcs_16bit parameter.| |phy_loopen_i|in|std_logic| |phy_rst_i|in|std_logic| |phy_tx_clk_o|out|std_logic| |phy_tx_data_i|in|std_logic_vector| |phy_tx_k_i|in|std_logic_vector| |phy_tx_disparity_o|out|std_logic| |phy_tx_enc_err_o|out|std_logic| |phy_rx_rbclk_o|out|std_logic| |phy_rx_data_o|out|std_logic_vector| |phy_rx_k_o|out|std_logic_vector| |phy_rx_enc_err_o|out|std_logic| |phy_rx_bitslide_o|out|std_logic_vector| |**Interface to the WR PTP core: External reference **| |ext_ref_mul_o|out|std_logic|125MHz clock output, derived from the 10MHz external reference| |ext_ref_mul_locked_o|out|std_logic|External reference PLL locked indication. This can be skipped if you are instantiating your own PLLs outside of the platform.| |ext_ref_rst_i|in|std_logic|External reference reset input, active high, used to reset the external reference PLL if necessary. This can be skipped if you are instantiating your own PLLs outside of the platform.|
20 December 2016