-- -------------------------------------------------------------
--
-- Module: cic_1024x
--
-- Generated by MATLAB(R) 7.10 and the Filter Design HDL Coder 2.6.
--
-- Generated on: 2013-05-06 18:04:46
--
-- -------------------------------------------------------------

-- -------------------------------------------------------------
-- HDL Code Generation Options:
--
-- TargetLanguage: VHDL
-- ResetType: Synchronous
-- ClockEnableInputPort: en_i
-- ClockEnableOutputPort: ce_out_o
-- ClockInputPort: clk_i
-- ResetInputPort: rst_i
-- UseRisingEdge: on
-- EDAScriptGeneration: off
-- AddPipelineRegisters: on
-- InputPort: x_i
-- OutputPort: y_o
-- Name: cic_1024x
-- TestBenchStimulus: step ramp chirp noise 
--
-- Filter Settings:
--
-- Discrete-Time FIR Multirate Filter (real)
-- -----------------------------------------
-- Filter Structure        : Cascaded Integrator-Comb Interpolator
-- Interpolation Factor    : 1024
-- Differential Delay      : 1
-- Number of Sections      : 7
-- Stable                  : Yes
-- Linear Phase            : No
--
-- Input                   : s18,15
-- Output                  : s78,15
-- Filter Internals        : Full Precision
--   Integrator Section 1  : s19,15
--   Integrator Section 2  : s20,15
--   Integrator Section 3  : s21,15
--   Integrator Section 4  : s22,15
--   Integrator Section 5  : s23,15
--   Integrator Section 6  : s24,15
--   Integrator Section 7  : s24,15
--   Comb Section 1        : s24,15
--   Comb Section 2        : s33,15
--   Comb Section 3        : s42,15
--   Comb Section 4        : s51,15
--   Comb Section 5        : s60,15
--   Comb Section 6        : s69,15
--   Comb Section 7        : s78,15
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
ENTITY cic_1024x IS
   PORT( clk_i                           :   IN    std_logic; 
         en_i                            :   IN    std_logic; 
         rst_i                           :   IN    std_logic; 
         x_i                             :   IN    std_logic_vector(17 DOWNTO 0); -- sfix18_En15
         y_o                             :   OUT   std_logic_vector(77 DOWNTO 0); -- sfix78_En15
         ce_out_o                        :   OUT   std_logic  
         );

END cic_1024x;


----------------------------------------------------------------
--Module Architecture: cic_1024x
----------------------------------------------------------------
ARCHITECTURE rtl OF cic_1024x IS
  -- Local Functions
  -- Type Definitions
  -- Constants
  CONSTANT zeroconst                      : signed(23 DOWNTO 0) := to_signed(0, 24); -- sfix24_En15
  -- Signals
  SIGNAL cur_count                        : unsigned(9 DOWNTO 0); -- ufix10
  SIGNAL phase_0                          : std_logic; -- boolean
  --   
  SIGNAL input_register                   : signed(17 DOWNTO 0); -- sfix18_En15
  --   -- Section 1 Signals 
  SIGNAL section_in1                      : signed(17 DOWNTO 0); -- sfix18_En15
  SIGNAL section_cast1                    : signed(18 DOWNTO 0); -- sfix19_En15
  SIGNAL diff1                            : signed(18 DOWNTO 0); -- sfix19_En15
  SIGNAL section_out1                     : signed(18 DOWNTO 0); -- sfix19_En15
  SIGNAL sub_cast                         : signed(18 DOWNTO 0); -- sfix19_En15
  SIGNAL sub_cast_1                       : signed(18 DOWNTO 0); -- sfix19_En15
  SIGNAL sub_temp                         : signed(19 DOWNTO 0); -- sfix20_En15
  SIGNAL cic_pipeline1                    : signed(18 DOWNTO 0); -- sfix19_En15
  --   -- Section 2 Signals 
  SIGNAL section_in2                      : signed(18 DOWNTO 0); -- sfix19_En15
  SIGNAL section_cast2                    : signed(19 DOWNTO 0); -- sfix20_En15
  SIGNAL diff2                            : signed(19 DOWNTO 0); -- sfix20_En15
  SIGNAL section_out2                     : signed(19 DOWNTO 0); -- sfix20_En15
  SIGNAL sub_cast_2                       : signed(19 DOWNTO 0); -- sfix20_En15
  SIGNAL sub_cast_3                       : signed(19 DOWNTO 0); -- sfix20_En15
  SIGNAL sub_temp_1                       : signed(20 DOWNTO 0); -- sfix21_En15
  SIGNAL cic_pipeline2                    : signed(19 DOWNTO 0); -- sfix20_En15
  --   -- Section 3 Signals 
  SIGNAL section_in3                      : signed(19 DOWNTO 0); -- sfix20_En15
  SIGNAL section_cast3                    : signed(20 DOWNTO 0); -- sfix21_En15
  SIGNAL diff3                            : signed(20 DOWNTO 0); -- sfix21_En15
  SIGNAL section_out3                     : signed(20 DOWNTO 0); -- sfix21_En15
  SIGNAL sub_cast_4                       : signed(20 DOWNTO 0); -- sfix21_En15
  SIGNAL sub_cast_5                       : signed(20 DOWNTO 0); -- sfix21_En15
  SIGNAL sub_temp_2                       : signed(21 DOWNTO 0); -- sfix22_En15
  SIGNAL cic_pipeline3                    : signed(20 DOWNTO 0); -- sfix21_En15
  --   -- Section 4 Signals 
  SIGNAL section_in4                      : signed(20 DOWNTO 0); -- sfix21_En15
  SIGNAL section_cast4                    : signed(21 DOWNTO 0); -- sfix22_En15
  SIGNAL diff4                            : signed(21 DOWNTO 0); -- sfix22_En15
  SIGNAL section_out4                     : signed(21 DOWNTO 0); -- sfix22_En15
  SIGNAL sub_cast_6                       : signed(21 DOWNTO 0); -- sfix22_En15
  SIGNAL sub_cast_7                       : signed(21 DOWNTO 0); -- sfix22_En15
  SIGNAL sub_temp_3                       : signed(22 DOWNTO 0); -- sfix23_En15
  SIGNAL cic_pipeline4                    : signed(21 DOWNTO 0); -- sfix22_En15
  --   -- Section 5 Signals 
  SIGNAL section_in5                      : signed(21 DOWNTO 0); -- sfix22_En15
  SIGNAL section_cast5                    : signed(22 DOWNTO 0); -- sfix23_En15
  SIGNAL diff5                            : signed(22 DOWNTO 0); -- sfix23_En15
  SIGNAL section_out5                     : signed(22 DOWNTO 0); -- sfix23_En15
  SIGNAL sub_cast_8                       : signed(22 DOWNTO 0); -- sfix23_En15
  SIGNAL sub_cast_9                       : signed(22 DOWNTO 0); -- sfix23_En15
  SIGNAL sub_temp_4                       : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL cic_pipeline5                    : signed(22 DOWNTO 0); -- sfix23_En15
  --   -- Section 6 Signals 
  SIGNAL section_in6                      : signed(22 DOWNTO 0); -- sfix23_En15
  SIGNAL section_cast6                    : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL diff6                            : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL section_out6                     : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL sub_cast_10                      : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL sub_cast_11                      : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL sub_temp_5                       : signed(24 DOWNTO 0); -- sfix25_En15
  SIGNAL cic_pipeline6                    : signed(23 DOWNTO 0); -- sfix24_En15
  --   -- Section 7 Signals 
  SIGNAL section_in7                      : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL diff7                            : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL section_out7                     : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL sub_cast_12                      : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL sub_cast_13                      : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL sub_temp_6                       : signed(24 DOWNTO 0); -- sfix25_En15
  SIGNAL cic_pipeline7                    : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL upsampling                       : signed(23 DOWNTO 0); -- sfix24_En15
  --   -- Section 8 Signals 
  SIGNAL section_in8                      : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL sum1                             : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL section_out8                     : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL add_cast                         : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL add_cast_1                       : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL add_temp                         : signed(24 DOWNTO 0); -- sfix25_En15
  --   -- Section 9 Signals 
  SIGNAL section_in9                      : signed(23 DOWNTO 0); -- sfix24_En15
  SIGNAL section_cast9                    : signed(32 DOWNTO 0); -- sfix33_En15
  SIGNAL sum2                             : signed(32 DOWNTO 0); -- sfix33_En15
  SIGNAL section_out9                     : signed(32 DOWNTO 0); -- sfix33_En15
  SIGNAL add_cast_2                       : signed(32 DOWNTO 0); -- sfix33_En15
  SIGNAL add_cast_3                       : signed(32 DOWNTO 0); -- sfix33_En15
  SIGNAL add_temp_1                       : signed(33 DOWNTO 0); -- sfix34_En15
  --   -- Section 10 Signals 
  SIGNAL section_in10                     : signed(32 DOWNTO 0); -- sfix33_En15
  SIGNAL section_cast10                   : signed(41 DOWNTO 0); -- sfix42_En15
  SIGNAL sum3                             : signed(41 DOWNTO 0); -- sfix42_En15
  SIGNAL section_out10                    : signed(41 DOWNTO 0); -- sfix42_En15
  SIGNAL add_cast_4                       : signed(41 DOWNTO 0); -- sfix42_En15
  SIGNAL add_cast_5                       : signed(41 DOWNTO 0); -- sfix42_En15
  SIGNAL add_temp_2                       : signed(42 DOWNTO 0); -- sfix43_En15
  --   -- Section 11 Signals 
  SIGNAL section_in11                     : signed(41 DOWNTO 0); -- sfix42_En15
  SIGNAL section_cast11                   : signed(50 DOWNTO 0); -- sfix51_En15
  SIGNAL sum4                             : signed(50 DOWNTO 0); -- sfix51_En15
  SIGNAL section_out11                    : signed(50 DOWNTO 0); -- sfix51_En15
  SIGNAL add_cast_6                       : signed(50 DOWNTO 0); -- sfix51_En15
  SIGNAL add_cast_7                       : signed(50 DOWNTO 0); -- sfix51_En15
  SIGNAL add_temp_3                       : signed(51 DOWNTO 0); -- sfix52_En15
  --   -- Section 12 Signals 
  SIGNAL section_in12                     : signed(50 DOWNTO 0); -- sfix51_En15
  SIGNAL section_cast12                   : signed(59 DOWNTO 0); -- sfix60_En15
  SIGNAL sum5                             : signed(59 DOWNTO 0); -- sfix60_En15
  SIGNAL section_out12                    : signed(59 DOWNTO 0); -- sfix60_En15
  SIGNAL add_cast_8                       : signed(59 DOWNTO 0); -- sfix60_En15
  SIGNAL add_cast_9                       : signed(59 DOWNTO 0); -- sfix60_En15
  SIGNAL add_temp_4                       : signed(60 DOWNTO 0); -- sfix61_En15
  --   -- Section 13 Signals 
  SIGNAL section_in13                     : signed(59 DOWNTO 0); -- sfix60_En15
  SIGNAL section_cast13                   : signed(68 DOWNTO 0); -- sfix69_En15
  SIGNAL sum6                             : signed(68 DOWNTO 0); -- sfix69_En15
  SIGNAL section_out13                    : signed(68 DOWNTO 0); -- sfix69_En15
  SIGNAL add_cast_10                      : signed(68 DOWNTO 0); -- sfix69_En15
  SIGNAL add_cast_11                      : signed(68 DOWNTO 0); -- sfix69_En15
  SIGNAL add_temp_5                       : signed(69 DOWNTO 0); -- sfix70_En15
  --   -- Section 14 Signals 
  SIGNAL section_in14                     : signed(68 DOWNTO 0); -- sfix69_En15
  SIGNAL section_cast14                   : signed(77 DOWNTO 0); -- sfix78_En15
  SIGNAL sum7                             : signed(77 DOWNTO 0); -- sfix78_En15
  SIGNAL section_out14                    : signed(77 DOWNTO 0); -- sfix78_En15
  SIGNAL add_cast_12                      : signed(77 DOWNTO 0); -- sfix78_En15
  SIGNAL add_cast_13                      : signed(77 DOWNTO 0); -- sfix78_En15
  SIGNAL add_temp_6                       : signed(78 DOWNTO 0); -- sfix79_En15
  --   
  SIGNAL output_register                  : signed(77 DOWNTO 0); -- sfix78_En15


BEGIN

  -- Block Statements
  --   ------------------ CE Output Generation ------------------

  ce_output : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        cur_count <= to_unsigned(0, 10);
      ELSIF en_i = '1' THEN
        IF cur_count = to_unsigned(1023, 10) THEN
          cur_count <= to_unsigned(0, 10);
        ELSE
          cur_count <= cur_count + 1;
        END IF;
      END IF;
    END IF; 
  END PROCESS ce_output;

  phase_0 <= '1' WHEN cur_count = to_unsigned(0, 10) AND en_i = '1' ELSE '0';

  --   ------------------ Input Register ------------------

  input_reg_process : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        input_register <= (OTHERS => '0');
      ELSIF phase_0 = '1' THEN
        input_register <= signed(x_i);
      END IF;
    END IF; 
  END PROCESS input_reg_process;

  --   ------------------ Section # 1 : Comb ------------------

  section_in1 <= input_register;

  section_cast1 <= resize(section_in1, 19);

  sub_cast <= section_cast1;
  sub_cast_1 <= diff1;
  sub_temp <= resize(sub_cast, 20) - resize(sub_cast_1, 20);
  section_out1 <= sub_temp(18 DOWNTO 0);

  comb_delay_section1 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        diff1 <= (OTHERS => '0');
      ELSIF phase_0 = '1' THEN
        diff1 <= section_cast1;
      END IF;
    END IF; 
  END PROCESS comb_delay_section1;

  cic_pipeline_process_section1 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        cic_pipeline1 <= (OTHERS => '0');
      ELSIF phase_0 = '1' THEN
        cic_pipeline1 <= section_out1;
      END IF;
    END IF; 
  END PROCESS cic_pipeline_process_section1;

  --   ------------------ Section # 2 : Comb ------------------

  section_in2 <= cic_pipeline1;

  section_cast2 <= resize(section_in2, 20);

  sub_cast_2 <= section_cast2;
  sub_cast_3 <= diff2;
  sub_temp_1 <= resize(sub_cast_2, 21) - resize(sub_cast_3, 21);
  section_out2 <= sub_temp_1(19 DOWNTO 0);

  comb_delay_section2 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        diff2 <= (OTHERS => '0');
      ELSIF phase_0 = '1' THEN
        diff2 <= section_cast2;
      END IF;
    END IF; 
  END PROCESS comb_delay_section2;

  cic_pipeline_process_section2 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        cic_pipeline2 <= (OTHERS => '0');
      ELSIF phase_0 = '1' THEN
        cic_pipeline2 <= section_out2;
      END IF;
    END IF; 
  END PROCESS cic_pipeline_process_section2;

  --   ------------------ Section # 3 : Comb ------------------

  section_in3 <= cic_pipeline2;

  section_cast3 <= resize(section_in3, 21);

  sub_cast_4 <= section_cast3;
  sub_cast_5 <= diff3;
  sub_temp_2 <= resize(sub_cast_4, 22) - resize(sub_cast_5, 22);
  section_out3 <= sub_temp_2(20 DOWNTO 0);

  comb_delay_section3 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        diff3 <= (OTHERS => '0');
      ELSIF phase_0 = '1' THEN
        diff3 <= section_cast3;
      END IF;
    END IF; 
  END PROCESS comb_delay_section3;

  cic_pipeline_process_section3 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        cic_pipeline3 <= (OTHERS => '0');
      ELSIF phase_0 = '1' THEN
        cic_pipeline3 <= section_out3;
      END IF;
    END IF; 
  END PROCESS cic_pipeline_process_section3;

  --   ------------------ Section # 4 : Comb ------------------

  section_in4 <= cic_pipeline3;

  section_cast4 <= resize(section_in4, 22);

  sub_cast_6 <= section_cast4;
  sub_cast_7 <= diff4;
  sub_temp_3 <= resize(sub_cast_6, 23) - resize(sub_cast_7, 23);
  section_out4 <= sub_temp_3(21 DOWNTO 0);

  comb_delay_section4 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        diff4 <= (OTHERS => '0');
      ELSIF phase_0 = '1' THEN
        diff4 <= section_cast4;
      END IF;
    END IF; 
  END PROCESS comb_delay_section4;

  cic_pipeline_process_section4 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        cic_pipeline4 <= (OTHERS => '0');
      ELSIF phase_0 = '1' THEN
        cic_pipeline4 <= section_out4;
      END IF;
    END IF; 
  END PROCESS cic_pipeline_process_section4;

  --   ------------------ Section # 5 : Comb ------------------

  section_in5 <= cic_pipeline4;

  section_cast5 <= resize(section_in5, 23);

  sub_cast_8 <= section_cast5;
  sub_cast_9 <= diff5;
  sub_temp_4 <= resize(sub_cast_8, 24) - resize(sub_cast_9, 24);
  section_out5 <= sub_temp_4(22 DOWNTO 0);

  comb_delay_section5 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        diff5 <= (OTHERS => '0');
      ELSIF phase_0 = '1' THEN
        diff5 <= section_cast5;
      END IF;
    END IF; 
  END PROCESS comb_delay_section5;

  cic_pipeline_process_section5 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        cic_pipeline5 <= (OTHERS => '0');
      ELSIF phase_0 = '1' THEN
        cic_pipeline5 <= section_out5;
      END IF;
    END IF; 
  END PROCESS cic_pipeline_process_section5;

  --   ------------------ Section # 6 : Comb ------------------

  section_in6 <= cic_pipeline5;

  section_cast6 <= resize(section_in6, 24);

  sub_cast_10 <= section_cast6;
  sub_cast_11 <= diff6;
  sub_temp_5 <= resize(sub_cast_10, 25) - resize(sub_cast_11, 25);
  section_out6 <= sub_temp_5(23 DOWNTO 0);

  comb_delay_section6 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        diff6 <= (OTHERS => '0');
      ELSIF phase_0 = '1' THEN
        diff6 <= section_cast6;
      END IF;
    END IF; 
  END PROCESS comb_delay_section6;

  cic_pipeline_process_section6 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        cic_pipeline6 <= (OTHERS => '0');
      ELSIF phase_0 = '1' THEN
        cic_pipeline6 <= section_out6;
      END IF;
    END IF; 
  END PROCESS cic_pipeline_process_section6;

  --   ------------------ Section # 7 : Comb ------------------

  section_in7 <= cic_pipeline6;

  sub_cast_12 <= section_in7;
  sub_cast_13 <= diff7;
  sub_temp_6 <= resize(sub_cast_12, 25) - resize(sub_cast_13, 25);
  section_out7 <= sub_temp_6(23 DOWNTO 0);

  comb_delay_section7 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        diff7 <= (OTHERS => '0');
      ELSIF phase_0 = '1' THEN
        diff7 <= section_in7;
      END IF;
    END IF; 
  END PROCESS comb_delay_section7;

  cic_pipeline_process_section7 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        cic_pipeline7 <= (OTHERS => '0');
      ELSIF phase_0 = '1' THEN
        cic_pipeline7 <= section_out7;
      END IF;
    END IF; 
  END PROCESS cic_pipeline_process_section7;

  upsampling <= cic_pipeline7 WHEN ( phase_0 = '1' ) ELSE
                zeroconst;
  --   ------------------ Section # 8 : Integrator ------------------

  section_in8 <= upsampling;

  add_cast <= section_in8;
  add_cast_1 <= section_out8;
  add_temp <= resize(add_cast, 25) + resize(add_cast_1, 25);
  sum1 <= add_temp(23 DOWNTO 0);

  integrator_delay_section8 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        section_out8 <= (OTHERS => '0');
      ELSIF en_i = '1' THEN
        section_out8 <= sum1;
      END IF;
    END IF; 
  END PROCESS integrator_delay_section8;

  --   ------------------ Section # 9 : Integrator ------------------

  section_in9 <= section_out8;

  section_cast9 <= resize(section_in9, 33);

  add_cast_2 <= section_cast9;
  add_cast_3 <= section_out9;
  add_temp_1 <= resize(add_cast_2, 34) + resize(add_cast_3, 34);
  sum2 <= add_temp_1(32 DOWNTO 0);

  integrator_delay_section9 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        section_out9 <= (OTHERS => '0');
      ELSIF en_i = '1' THEN
        section_out9 <= sum2;
      END IF;
    END IF; 
  END PROCESS integrator_delay_section9;

  --   ------------------ Section # 10 : Integrator ------------------

  section_in10 <= section_out9;

  section_cast10 <= resize(section_in10, 42);

  add_cast_4 <= section_cast10;
  add_cast_5 <= section_out10;
  add_temp_2 <= resize(add_cast_4, 43) + resize(add_cast_5, 43);
  sum3 <= add_temp_2(41 DOWNTO 0);

  integrator_delay_section10 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        section_out10 <= (OTHERS => '0');
      ELSIF en_i = '1' THEN
        section_out10 <= sum3;
      END IF;
    END IF; 
  END PROCESS integrator_delay_section10;

  --   ------------------ Section # 11 : Integrator ------------------

  section_in11 <= section_out10;

  section_cast11 <= resize(section_in11, 51);

  add_cast_6 <= section_cast11;
  add_cast_7 <= section_out11;
  add_temp_3 <= resize(add_cast_6, 52) + resize(add_cast_7, 52);
  sum4 <= add_temp_3(50 DOWNTO 0);

  integrator_delay_section11 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        section_out11 <= (OTHERS => '0');
      ELSIF en_i = '1' THEN
        section_out11 <= sum4;
      END IF;
    END IF; 
  END PROCESS integrator_delay_section11;

  --   ------------------ Section # 12 : Integrator ------------------

  section_in12 <= section_out11;

  section_cast12 <= resize(section_in12, 60);

  add_cast_8 <= section_cast12;
  add_cast_9 <= section_out12;
  add_temp_4 <= resize(add_cast_8, 61) + resize(add_cast_9, 61);
  sum5 <= add_temp_4(59 DOWNTO 0);

  integrator_delay_section12 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        section_out12 <= (OTHERS => '0');
      ELSIF en_i = '1' THEN
        section_out12 <= sum5;
      END IF;
    END IF; 
  END PROCESS integrator_delay_section12;

  --   ------------------ Section # 13 : Integrator ------------------

  section_in13 <= section_out12;

  section_cast13 <= resize(section_in13, 69);

  add_cast_10 <= section_cast13;
  add_cast_11 <= section_out13;
  add_temp_5 <= resize(add_cast_10, 70) + resize(add_cast_11, 70);
  sum6 <= add_temp_5(68 DOWNTO 0);

  integrator_delay_section13 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        section_out13 <= (OTHERS => '0');
      ELSIF en_i = '1' THEN
        section_out13 <= sum6;
      END IF;
    END IF; 
  END PROCESS integrator_delay_section13;

  --   ------------------ Section # 14 : Integrator ------------------

  section_in14 <= section_out13;

  section_cast14 <= resize(section_in14, 78);

  add_cast_12 <= section_cast14;
  add_cast_13 <= section_out14;
  add_temp_6 <= resize(add_cast_12, 79) + resize(add_cast_13, 79);
  sum7 <= add_temp_6(77 DOWNTO 0);

  integrator_delay_section14 : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        section_out14 <= (OTHERS => '0');
      ELSIF en_i = '1' THEN
        section_out14 <= sum7;
      END IF;
    END IF; 
  END PROCESS integrator_delay_section14;

  --   ------------------ Output Register ------------------

  output_reg_process : PROCESS (clk_i)
  BEGIN
    IF rising_edge(clk_i) THEN
      IF rst_i = '1' THEN
        output_register <= (OTHERS => '0');
      ELSIF en_i = '1' THEN
        output_register <= section_out14;
      END IF;
    END IF; 
  END PROCESS output_reg_process;

  -- Assignment Statements
  ce_out_o <= phase_0;
  y_o <= std_logic_vector(output_register);
END rtl;
