Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
D
Distributed Direct Digital Synthesis over White Rabbit D3S
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Distributed Direct Digital Synthesis over White Rabbit D3S
Repository
2e8c4217bdd812ffcf96c159dbb2e0f547db4a51
Switch branch/tag
wr-d3s
software
fdelay_bus.c
Find file
Blame
History
Permalink
software: initial DDS PLL version, seems to lock to a 10 MHz reference
· 03fefdbe
root
authored
May 07, 2013
03fefdbe
fdelay_bus.c
2.25 KB
Edit
Web IDE
Replace fdelay_bus.c
×
Attach a file by drag & drop or
click to upload
Commit message
Replace fdelay_bus.c
Replace file
Cancel
A new branch will be created in your fork and a new merge request will be started.
