software: initial DDS PLL version, seems to lock to a 10 MHz reference
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software/Makefile
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software/ad9516.c
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software/fdelay_bus.c
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software/filters.c
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software/filters.h
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software/fir_compensator.dat
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software/load.sh
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software/pll_regs.py
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software/regs/ad9516_init.h
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software/regs/dds_regs.h
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software/speclib/Makefile
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software/speclib/spec-cl.c
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software/speclib/speclib.c
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software/speclib/speclib.h
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software/speclib/specmem.c
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software/speclib/wb_uart.h
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