Commit 18fa03ce authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

initial version of (more-or-less) working VHDL

parent cf566000
`define ADDR_DDS_CR 6'h0
`define ADDR_DDS_CR 7'h0
`define DDS_CR_TEST_OFFSET 0
`define DDS_CR_TEST 32'h00000001
`define DDS_CR_SLAVE_OFFSET 1
......@@ -7,9 +7,13 @@
`define DDS_CR_MASTER 32'h00000004
`define DDS_CR_ADC_BB_ENABLE_OFFSET 3
`define DDS_CR_ADC_BB_ENABLE 32'h00000008
`define DDS_CR_CLK_ID_OFFSET 4
`define DDS_CR_CLK_ID 32'h000ffff0
`define ADDR_DDS_GPIOR 6'h4
`define DDS_CR_WR_LINK_OFFSET 4
`define DDS_CR_WR_LINK 32'h00000010
`define DDS_CR_WR_TIME_OFFSET 5
`define DDS_CR_WR_TIME 32'h00000020
`define DDS_CR_CLK_ID_OFFSET 16
`define DDS_CR_CLK_ID 32'hffff0000
`define ADDR_DDS_GPIOR 7'h4
`define DDS_GPIOR_PLL_SYS_CS_N_OFFSET 0
`define DDS_GPIOR_PLL_SYS_CS_N 32'h00000001
`define DDS_GPIOR_PLL_SYS_RESET_N_OFFSET 1
......@@ -44,15 +48,15 @@
`define DDS_GPIOR_ADC_SCK 32'h00008000
`define DDS_GPIOR_ADC_SDO_OFFSET 16
`define DDS_GPIOR_ADC_SDO 32'h00010000
`define ADDR_DDS_FREQ_HI 6'h8
`define ADDR_DDS_FREQ_LO 6'hc
`define ADDR_DDS_GAIN 6'h10
`define ADDR_DDS_RSTR 6'h14
`define ADDR_DDS_FREQ_HI 7'h8
`define ADDR_DDS_FREQ_LO 7'hc
`define ADDR_DDS_GAIN 7'h10
`define ADDR_DDS_RSTR 7'h14
`define DDS_RSTR_PLL_RST_OFFSET 0
`define DDS_RSTR_PLL_RST 32'h00000001
`define DDS_RSTR_SW_RST_OFFSET 1
`define DDS_RSTR_SW_RST 32'h00000002
`define ADDR_DDS_I2CR 6'h18
`define ADDR_DDS_I2CR 7'h18
`define DDS_I2CR_SCL_OUT_OFFSET 0
`define DDS_I2CR_SCL_OUT 32'h00000001
`define DDS_I2CR_SDA_OUT_OFFSET 1
......@@ -61,23 +65,47 @@
`define DDS_I2CR_SCL_IN 32'h00000004
`define DDS_I2CR_SDA_IN_OFFSET 3
`define DDS_I2CR_SDA_IN 32'h00000008
`define ADDR_DDS_PIR 6'h1c
`define ADDR_DDS_PIR 7'h1c
`define DDS_PIR_KP_OFFSET 0
`define DDS_PIR_KP 32'h0000ffff
`define DDS_PIR_KI_OFFSET 16
`define DDS_PIR_KI 32'hffff0000
`define ADDR_DDS_PD_FIFO_R0 6'h20
`define ADDR_DDS_DLYR 7'h20
`define DDS_DLYR_DELAY_OFFSET 0
`define DDS_DLYR_DELAY 32'h0000ffff
`define ADDR_DDS_PHASER 7'h24
`define DDS_PHASER_PHASE_OFFSET 0
`define DDS_PHASER_PHASE 32'h0000ffff
`define ADDR_DDS_MACL 7'h28
`define DDS_MACL_MACL_OFFSET 0
`define DDS_MACL_MACL 32'hffffffff
`define ADDR_DDS_MACH 7'h2c
`define DDS_MACH_MACH_OFFSET 0
`define DDS_MACH_MACH 32'h0000ffff
`define ADDR_DDS_HIT_CNT 7'h30
`define DDS_HIT_CNT_HIT_CNT_OFFSET 0
`define DDS_HIT_CNT_HIT_CNT 32'h00ffffff
`define ADDR_DDS_MISS_CNT 7'h34
`define DDS_MISS_CNT_MISS_CNT_OFFSET 0
`define DDS_MISS_CNT_MISS_CNT 32'h00ffffff
`define ADDR_DDS_RX_CNT 7'h38
`define DDS_RX_CNT_RX_CNT_OFFSET 0
`define DDS_RX_CNT_RX_CNT 32'h00ffffff
`define ADDR_DDS_TX_CNT 7'h3c
`define DDS_TX_CNT_TX_CNT_OFFSET 0
`define DDS_TX_CNT_TX_CNT 32'h00ffffff
`define ADDR_DDS_PD_FIFO_R0 7'h40
`define DDS_PD_FIFO_R0_DATA_OFFSET 0
`define DDS_PD_FIFO_R0_DATA 32'h0000ffff
`define ADDR_DDS_PD_FIFO_CSR 6'h24
`define ADDR_DDS_PD_FIFO_CSR 7'h44
`define DDS_PD_FIFO_CSR_FULL_OFFSET 16
`define DDS_PD_FIFO_CSR_FULL 32'h00010000
`define DDS_PD_FIFO_CSR_EMPTY_OFFSET 17
`define DDS_PD_FIFO_CSR_EMPTY 32'h00020000
`define ADDR_DDS_TUNE_FIFO_R0 6'h28
`define ADDR_DDS_TUNE_FIFO_R0 7'h48
`define DDS_TUNE_FIFO_R0_DATA_OFFSET 0
`define DDS_TUNE_FIFO_R0_DATA 32'hffffffff
`define ADDR_DDS_TUNE_FIFO_CSR 6'h2c
`define ADDR_DDS_TUNE_FIFO_CSR 7'h4c
`define DDS_TUNE_FIFO_CSR_FULL_OFFSET 16
`define DDS_TUNE_FIFO_CSR_FULL 32'h00010000
`define DDS_TUNE_FIFO_CSR_EMPTY_OFFSET 17
......
files = ["dds_stage.v", "pi_control.v", "dds_quad_channel.v", "mdsp.v", "dds_wb_slave.vhd", "dds_wbgen2_pkg.vhd", "max5870_serializer.vhd", "dds_core.vhd", "cic_1024x.vhd", "spi_master.vhd", "ad7980_if.vhd","timestamp_adder.vhd" ]
files = ["dds_stage.v", "pi_control.v", "dds_quad_channel.v", "mdsp.v", "dds_wb_slave.vhd", "dds_wbgen2_pkg.vhd", "max5870_serializer.vhd", "dds_core.vhd", "cic_1024x.vhd", "spi_master.vhd", "ad7980_if.vhd","timestamp_adder.vhd","dds_tx_path.vhd","dds_rx_path.vhd","timestamp_compare.vhd","pll_init.v" ]
modules = {"local":"streamers"}
This diff is collapsed.
This diff is collapsed.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.streamers_pkg.all;
use work.wr_fabric_pkg.all;
use work.gencores_pkg.all;
use work.dds_wbgen2_pkg.all;
entity dds_tx_path is
generic(
g_acc_bits : integer);
port (
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_sys_i : in std_logic;
rst_n_ref_i : in std_logic;
tune_i : in std_logic_vector(17 downto 0);
cic_ce_i : in std_logic;
acc_i : in std_logic_vector(g_acc_bits-1 downto 0);
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
tm_time_valid_i : in std_logic;
tm_tai_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
regs_i : in t_dds_out_registers;
regs_o : out t_dds_in_registers
);
end dds_tx_path;
architecture behavioral of dds_tx_path is
type t_state is (WAIT_SAMPLE, TX_TIMESTAMP, TX_TUNE, TX_ACC, TX_PAD);
signal tx_data : std_logic_vector(63 downto 0);
signal tx_valid : std_logic;
signal tx_dreq : std_logic;
signal tx_last : std_logic;
signal mac_target : std_logic_vector(47 downto 0);
signal acc_snap : std_logic_vector(g_acc_bits-1 downto 0);
signal tune_snap : std_logic_vector(17 downto 0);
signal tai_snap : std_logic_vector(39 downto 0);
signal cycles_snap : std_logic_vector(27 downto 0);
signal new_sample : std_logic;
signal new_sample_sys, tune_valid : std_logic;
signal state : t_state;
signal tx_cnt : unsigned(23 downto 0);
begin -- behavioral
regs_o.tx_cnt_tx_cnt_i <= std_logic_vector(tx_cnt);
p_take_tags : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_ref_i = '0' then
new_sample <= '0';
tune_valid <= '0';
else
tune_valid <= cic_ce_i;
if(tune_valid = '1' and tm_time_valid_i = '1') then
new_sample <= '1';
acc_snap <= acc_i;
tune_snap <= tune_i;
tai_snap <= tm_tai_i;
cycles_snap <= tm_cycles_i;
else
new_sample <= '0';
end if;
end if;
end if;
end process;
U_Sync : gc_pulse_synchronizer
port map (
clk_in_i => clk_ref_i,
clk_out_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
d_p_i => new_sample,
q_p_o => new_sample_sys);
U_Streamer : xtx_streamer
generic map (
g_data_width => 64,
g_tx_threshold => 4,
g_tx_max_words_per_frame => 128,
g_tx_timeout => 64)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
src_i => src_i,
src_o => src_o,
clk_ref_i => clk_ref_i,
tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_tai_i,
tm_cycles_i => tm_cycles_i,
tx_data_i => tx_data,
tx_valid_i => tx_valid,
tx_dreq_o => tx_dreq,
tx_last_i => tx_last,
cfg_mac_target_i => mac_target);
mac_target <= regs_i.mach_mach_o & regs_i.macl_macl_o;
p_tx_fsm : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_sys_i = '0' or regs_i.cr_master_o = '0' then
state <= WAIT_SAMPLE;
tx_valid <= '0';
tx_last <= '0';
tx_data <= (others => '0');
tx_cnt <= (others => '0');
else
case state is
when WAIT_SAMPLE =>
tx_valid <= '0';
tx_last <= '0';
if(regs_i.cr_master_o = '1' and new_sample_sys = '1') then
state <= TX_TIMESTAMP;
end if;
when TX_TIMESTAMP =>
tx_cnt <= tx_cnt + 1;
if(tx_dreq = '1') then
tx_data(27 downto 0) <= cycles_snap;
tx_data(63 downto 32) <= tai_snap(31 downto 0);
tx_valid <= '1';
tx_last <= '0';
state <= TX_ACC;
else
tx_valid <= '0';
end if;
when TX_ACC =>
if(tx_dreq = '1') then
tx_data(g_acc_bits-1 downto 0) <= acc_snap;
tx_valid <= '1';
tx_last <= '0';
state <= TX_TUNE;
else
tx_valid <= '0';
end if;
when TX_TUNE =>
if(tx_dreq = '1') then
tx_data(17 downto 0) <= tune_snap;
tx_data(47 downto 32) <= regs_i.cr_clk_id_o;
tx_valid <= '1';
tx_last <= '0';
state <= TX_PAD;
else
tx_valid <= '0';
end if;
when TX_PAD =>
if(tx_dreq = '1') then
tx_valid <= '1';
tx_last <= '1';
state <= WAIT_SAMPLE;
else
tx_valid <= '0';
end if;
end case;
end if;
end if;
end process;
end behavioral;
This diff is collapsed.
......@@ -39,6 +39,23 @@ peripheral {
type = MONOSTABLE;
};
field {
name = "WR Link status";
prefix = "WR_LINK";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
type = BIT;
};
field {
name = "WR Time status";
prefix = "WR_TIME";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
type = BIT;
};
field {
name = "Broadcast Clock ID";
description = "Send/Receive clocks matching given ID";
......@@ -46,6 +63,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
align = 16;
size = 16;
};
......@@ -348,4 +366,112 @@ peripheral {
size = 16;
};
};
reg {
name = "Delay Adjust Register";
prefix = "DLYR";
field {
name = "Delay";
prefix = "DELAY";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 16;
};
};
reg {
name = "Phase Shift Adjust Register";
prefix = "PHASER";
field {
name = "PHASE";
prefix = "PHASE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 16;
};
};
reg {
name = "MAC Lo reg";
prefix = "MACL";
field {
name = "MACL";
prefix = "MACL";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 32;
};
};
reg {
name = "MAC Hi reg";
prefix = "MACH";
field {
name = "MACH";
prefix = "MACH";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 16;
};
};
reg {
name = "Hit Count Reg";
prefix = "HIT_CNT";
field {
clock = "clk_ref_i";
name = "HIT_CNT";
prefix = "HIT_CNT";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
type = SLV;
size = 24;
};
};
reg {
name = "Miss Count Reg";
prefix = "MISS_CNT";
field {
clock = "clk_ref_i";
name = "MISS_CNT";
prefix = "MISS_CNT";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
type = SLV;
size = 24;
};
};
reg {
name = "RX Count Reg";
prefix = "RX_CNT";
field {
name = "RX_CNT";
prefix = "RX_CNT";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
type = SLV;
size = 24;
};
};
reg {
name = "TX Count Reg";
prefix = "TX_CNT";
field {
name = "TX_CNT";
prefix = "TX_CNT";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
type = SLV;
size = 24;
};
};
};
\ No newline at end of file
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : dds_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from dds_wb_slave.wb
-- Created : Fri May 10 01:11:43 2013
-- Created : Mon May 13 01:42:01 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dds_wb_slave.wb
......@@ -21,6 +21,8 @@ package dds_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_dds_in_registers is record
cr_wr_link_i : std_logic;
cr_wr_time_i : std_logic;
gpior_pll_sdio_i : std_logic;
gpior_pll_vcxo_sdo_i : std_logic;
gpior_adc_sdo_i : std_logic;
......@@ -29,9 +31,15 @@ package dds_wbgen2_pkg is
tune_fifo_rd_req_i : std_logic;
i2cr_scl_in_i : std_logic;
i2cr_sda_in_i : std_logic;
hit_cnt_hit_cnt_i : std_logic_vector(23 downto 0);
miss_cnt_miss_cnt_i : std_logic_vector(23 downto 0);
rx_cnt_rx_cnt_i : std_logic_vector(23 downto 0);
tx_cnt_tx_cnt_i : std_logic_vector(23 downto 0);
end record;
constant c_dds_in_registers_init_value: t_dds_in_registers := (
cr_wr_link_i => '0',
cr_wr_time_i => '0',
gpior_pll_sdio_i => '0',
gpior_pll_vcxo_sdo_i => '0',
gpior_adc_sdo_i => '0',
......@@ -39,7 +47,11 @@ package dds_wbgen2_pkg is
pd_fifo_data_i => (others => '0'),
tune_fifo_rd_req_i => '0',
i2cr_scl_in_i => '0',
i2cr_sda_in_i => '0'
i2cr_sda_in_i => '0',
hit_cnt_hit_cnt_i => (others => '0'),
miss_cnt_miss_cnt_i => (others => '0'),
rx_cnt_rx_cnt_i => (others => '0'),
tx_cnt_tx_cnt_i => (others => '0')
);
-- Output registers (WB slave -> user design)
......@@ -79,6 +91,10 @@ package dds_wbgen2_pkg is
i2cr_sda_out_o : std_logic;
pir_kp_o : std_logic_vector(15 downto 0);
pir_ki_o : std_logic_vector(15 downto 0);
dlyr_delay_o : std_logic_vector(15 downto 0);
phaser_phase_o : std_logic_vector(15 downto 0);
macl_macl_o : std_logic_vector(31 downto 0);
mach_mach_o : std_logic_vector(15 downto 0);
end record;
constant c_dds_out_registers_init_value: t_dds_out_registers := (
......@@ -115,7 +131,11 @@ package dds_wbgen2_pkg is
i2cr_scl_out_o => '0',
i2cr_sda_out_o => '0',
pir_kp_o => (others => '0'),
pir_ki_o => (others => '0')
pir_ki_o => (others => '0'),
dlyr_delay_o => (others => '0'),
phaser_phase_o => (others => '0'),
macl_macl_o => (others => '0'),
mach_mach_o => (others => '0')
);
function "or" (left, right: t_dds_in_registers) return t_dds_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......@@ -146,6 +166,8 @@ end function;
function "or" (left, right: t_dds_in_registers) return t_dds_in_registers is
variable tmp: t_dds_in_registers;
begin
tmp.cr_wr_link_i := f_x_to_zero(left.cr_wr_link_i) or f_x_to_zero(right.cr_wr_link_i);
tmp.cr_wr_time_i := f_x_to_zero(left.cr_wr_time_i) or f_x_to_zero(right.cr_wr_time_i);
tmp.gpior_pll_sdio_i := f_x_to_zero(left.gpior_pll_sdio_i) or f_x_to_zero(right.gpior_pll_sdio_i);
tmp.gpior_pll_vcxo_sdo_i := f_x_to_zero(left.gpior_pll_vcxo_sdo_i) or f_x_to_zero(right.gpior_pll_vcxo_sdo_i);
tmp.gpior_adc_sdo_i := f_x_to_zero(left.gpior_adc_sdo_i) or f_x_to_zero(right.gpior_adc_sdo_i);
......@@ -154,6 +176,10 @@ tmp.pd_fifo_data_i := f_x_to_zero(left.pd_fifo_data_i) or f_x_to_zero(right.pd_f
tmp.tune_fifo_rd_req_i := f_x_to_zero(left.tune_fifo_rd_req_i) or f_x_to_zero(right.tune_fifo_rd_req_i);
tmp.i2cr_scl_in_i := f_x_to_zero(left.i2cr_scl_in_i) or f_x_to_zero(right.i2cr_scl_in_i);
tmp.i2cr_sda_in_i := f_x_to_zero(left.i2cr_sda_in_i) or f_x_to_zero(right.i2cr_sda_in_i);
tmp.hit_cnt_hit_cnt_i := f_x_to_zero(left.hit_cnt_hit_cnt_i) or f_x_to_zero(right.hit_cnt_hit_cnt_i);
tmp.miss_cnt_miss_cnt_i := f_x_to_zero(left.miss_cnt_miss_cnt_i) or f_x_to_zero(right.miss_cnt_miss_cnt_i);
tmp.rx_cnt_rx_cnt_i := f_x_to_zero(left.rx_cnt_rx_cnt_i) or f_x_to_zero(right.rx_cnt_rx_cnt_i);
tmp.tx_cnt_tx_cnt_i := f_x_to_zero(left.tx_cnt_tx_cnt_i) or f_x_to_zero(right.tx_cnt_tx_cnt_i);
return tmp;
end function;
end package body;
`timescale 1ns/1ns
module pll_init
(
input clk_i,
input rst_n_i,
output reg done_o,
output reg cs_n_o,
output reg mosi_o,
output reg sck_o
);
reg [2:0] pll_init_seq[0:8191];
initial begin : initialize_lut
integer i;
for(i=0;i<2048;i=i+1)
begin
pll_init_seq[4*i] = 3'h7;
pll_init_seq[4*i+1] = 3'h7;
pll_init_seq[4*i+2] = 3'h7;
pll_init_seq[4*i+3] = 3'h7;
end
`include "pll_init_data.v"
end // block: initialize_lut
parameter g_simulation = 0;
localparam g_bit_time = g_simulation ? 1: 300;
localparam g_done_delay = g_simulation ? 300: 300000;
reg [23:0] cnt;
reg [12:0] addr;
reg [1:0] state;
`define ST_IDLE 0
`define ST_BOOT_PLL 1
`define ST_INIT_DELAY 2
`define ST_DONE 3
wire [2:0] ram_in;
assign ram_in = pll_init_seq[addr];
always@(posedge clk_i or negedge rst_n_i)
if(!rst_n_i)
begin
state <= `ST_IDLE;
addr <= 0;
cnt <= 0;
done_o <= 0;
end else begin
case (state)
`ST_IDLE: begin
state <= `ST_BOOT_PLL;
addr <= 0;
cnt <= 0;
end
`ST_BOOT_PLL: begin
cs_n_o <= ram_in[0];
sck_o <= ram_in[1];
mosi_o <= ram_in[2];
cnt <= cnt + 1;
if(cnt == g_bit_time)begin
addr <= addr + 1;
cnt <= 0;
if(addr == 8191)
state <= `ST_INIT_DELAY;
end
else
cnt <= cnt + 1;
end // case: `ST_BOOT_PLL
`ST_INIT_DELAY: begin
cnt <= cnt + 1;
if(cnt == g_done_delay)
state <= `ST_DONE;
end
`ST_DONE:
done_o <= 1;
endcase // case (state)
end // else: !if(!rst_n_i)
endmodule // pll_init
This diff is collapsed.
......@@ -179,7 +179,7 @@ architecture rtl of xtx_streamer is
type t_tx_state is (IDLE, SOF, ETH_HEADER, SUBFRAME_HEADER, PAYLOAD, CRC_WORD, PADDING, EOF);
constant c_min_packet_size : integer := 32;
constant c_min_packet_size : integer := 30;
signal tx_threshold_hit : std_logic;
signal tx_timeout_hit : std_logic;
......
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timestamp_compare is
generic
(
-- sizes of the respective bitfields of the input/output timestamps
g_cycles_bits : integer := 28;
g_tai_bits : integer := 40;
-- upper bound of the coarse part
g_ref_clk_rate : integer := 125000000
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
valid_i : in std_logic; -- when HI, a_* and b_* contain valid timestamps
-- Input timestamps
a_tai_i : in std_logic_vector(g_tai_bits-1 downto 0);
a_cycles_i : in std_logic_vector(g_cycles_bits-1 downto 0);
b_tai_i : in std_logic_vector(g_tai_bits-1 downto 0);
b_cycles_i : in std_logic_vector(g_cycles_bits-1 downto 0);
-- Normalized sum output (valid when valid_o == 1)
valid_o : out std_logic;
equal_o : out std_logic;
a_less_o : out std_logic;
a_great_o : out std_logic
);
end timestamp_compare;
architecture rtl of timestamp_compare is
signal tai_less, tai_equal : std_logic;
signal cycles_less, cycles_equal : std_logic;
signal stage1 : std_logic;
begin -- rtl
p_stage1 : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
stage1 <= '0';
else
stage1 <= valid_i;
if(unsigned(a_tai_i) < unsigned(b_tai_i)) then
tai_less <= '1';
else
tai_less <= '0';
end if;
if(unsigned(a_tai_i) = unsigned(b_tai_i)) then
tai_equal <= '1';
else
tai_equal <= '0';
end if;
if(unsigned(a_cycles_i) < unsigned(b_cycles_i)) then
cycles_less <= '1';
else
cycles_less <= '0';
end if;
if(unsigned(a_cycles_i) = unsigned(b_cycles_i)) then
cycles_equal <= '1';
else
cycles_equal <= '0';
end if;
end if;
end if;
end process;
p_stage2 : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
valid_o <= '0';
else
equal_o <= tai_equal and cycles_equal;
a_less_o <= tai_less or (tai_equal and cycles_less);
a_great_o <= (not (tai_equal or tai_less)) or (tai_equal and (not (cycles_less or cycles_equal)));
valid_o <= stage1;
end if;
end if;
end process;
end rtl;
......@@ -9,6 +9,6 @@ syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_rf_demo.xise"
modules = { "local" : [ "../../top" ] }
modules = { "local" : [ "../../top/spec" ] }