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Distributed Direct Digital Synthesis over White Rabbit D3S
Commit 1bd30289 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl: initial commit

parent dc92d265
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dds_regs.vh 0 → 100644
View file @ 1bd30289
`define ADDR_DDS_CR 6'h0
`define DDS_CR_TEST_OFFSET 0
`define DDS_CR_TEST 32'h00000001
`define DDS_CR_SLAVE_OFFSET 1
`define DDS_CR_SLAVE 32'h00000002
`define DDS_CR_MASTER_OFFSET 2
`define DDS_CR_MASTER 32'h00000004
`define DDS_CR_ADC_BB_ENABLE_OFFSET 3
`define DDS_CR_ADC_BB_ENABLE 32'h00000008
`define DDS_CR_CLK_ID_OFFSET 4
`define DDS_CR_CLK_ID 32'h000ffff0
`define ADDR_DDS_GPIOR 6'h4
`define DDS_GPIOR_PLL_SYS_CS_N_OFFSET 0
`define DDS_GPIOR_PLL_SYS_CS_N 32'h00000001
`define DDS_GPIOR_PLL_SYS_RESET_N_OFFSET 1
`define DDS_GPIOR_PLL_SYS_RESET_N 32'h00000002
`define DDS_GPIOR_PLL_SCLK_OFFSET 2
`define DDS_GPIOR_PLL_SCLK 32'h00000004
`define DDS_GPIOR_PLL_SDIO_OFFSET 3
`define DDS_GPIOR_PLL_SDIO 32'h00000008
`define DDS_GPIOR_PLL_SDIO_DIR_OFFSET 4
`define DDS_GPIOR_PLL_SDIO_DIR 32'h00000010
`define DDS_GPIOR_PLL_VCXO_RESET_N_OFFSET 5
`define DDS_GPIOR_PLL_VCXO_RESET_N 32'h00000020
`define DDS_GPIOR_PLL_VCXO_CS_N_OFFSET 6
`define DDS_GPIOR_PLL_VCXO_CS_N 32'h00000040
`define DDS_GPIOR_PLL_VCXO_FUNCTION_OFFSET 7
`define DDS_GPIOR_PLL_VCXO_FUNCTION 32'h00000080
`define DDS_GPIOR_PLL_VCXO_SDO_OFFSET 8
`define DDS_GPIOR_PLL_VCXO_SDO 32'h00000100
`define DDS_GPIOR_ADF_CE_OFFSET 9
`define DDS_GPIOR_ADF_CE 32'h00000200
`define DDS_GPIOR_ADF_CLK_OFFSET 10
`define DDS_GPIOR_ADF_CLK 32'h00000400
`define DDS_GPIOR_ADF_LE_OFFSET 11
`define DDS_GPIOR_ADF_LE 32'h00000800
`define DDS_GPIOR_ADF_DATA_OFFSET 12
`define DDS_GPIOR_ADF_DATA 32'h00001000
`define DDS_GPIOR_ADC_SDI_OFFSET 13
`define DDS_GPIOR_ADC_SDI 32'h00002000
`define DDS_GPIOR_ADC_CNV_OFFSET 14
`define DDS_GPIOR_ADC_CNV 32'h00004000
`define DDS_GPIOR_ADC_SCK_OFFSET 15
`define DDS_GPIOR_ADC_SCK 32'h00008000
`define DDS_GPIOR_ADC_SDO_OFFSET 16
`define DDS_GPIOR_ADC_SDO 32'h00010000
`define ADDR_DDS_FREQ_HI 6'h8
`define ADDR_DDS_FREQ_LO 6'hc
`define ADDR_DDS_GAIN 6'h10
`define ADDR_DDS_RSTR 6'h14
`define DDS_RSTR_PLL_RST_OFFSET 0
`define DDS_RSTR_PLL_RST 32'h00000001
`define DDS_RSTR_SW_RST_OFFSET 1
`define DDS_RSTR_SW_RST 32'h00000002
`define ADDR_DDS_I2CR 6'h18
`define DDS_I2CR_SCL_OUT_OFFSET 0
`define DDS_I2CR_SCL_OUT 32'h00000001
`define DDS_I2CR_SDA_OUT_OFFSET 1
`define DDS_I2CR_SDA_OUT 32'h00000002
`define DDS_I2CR_SCL_IN_OFFSET 2
`define DDS_I2CR_SCL_IN 32'h00000004
`define DDS_I2CR_SDA_IN_OFFSET 3
`define DDS_I2CR_SDA_IN 32'h00000008
`define ADDR_DDS_PIR 6'h1c
`define DDS_PIR_KP_OFFSET 0
`define DDS_PIR_KP 32'h0000ffff
`define DDS_PIR_KI_OFFSET 16
`define DDS_PIR_KI 32'hffff0000
`define ADDR_DDS_PD_FIFO_R0 6'h20
`define DDS_PD_FIFO_R0_DATA_OFFSET 0
`define DDS_PD_FIFO_R0_DATA 32'h0000ffff
`define ADDR_DDS_PD_FIFO_CSR 6'h24
`define DDS_PD_FIFO_CSR_FULL_OFFSET 16
`define DDS_PD_FIFO_CSR_FULL 32'h00010000
`define DDS_PD_FIFO_CSR_EMPTY_OFFSET 17
`define DDS_PD_FIFO_CSR_EMPTY 32'h00020000
`define ADDR_DDS_TUNE_FIFO_R0 6'h28
`define DDS_TUNE_FIFO_R0_DATA_OFFSET 0
`define DDS_TUNE_FIFO_R0_DATA 32'hffffffff
`define ADDR_DDS_TUNE_FIFO_CSR 6'h2c
`define DDS_TUNE_FIFO_CSR_FULL_OFFSET 16
`define DDS_TUNE_FIFO_CSR_FULL 32'h00010000
`define DDS_TUNE_FIFO_CSR_EMPTY_OFFSET 17
`define DDS_TUNE_FIFO_CSR_EMPTY 32'h00020000
rtl/Manifest.py
View file @ 1bd30289
files = ["dds_single_channel.v","lfsr_gen.vhd" ]
files = ["dds_stage.v", "pi_control.v", "dds_quad_channel.v", "mdsp.v", "dds_wb_slave.vhd", "dds_wbgen2_pkg.vhd", "max5870_serializer.vhd", "dds_core.vhd", "cic_1024x.vhd", "spi_master.vhd", "ad7980_if.vhd","timestamp_adder.vhd" ]
modules = {"local":"streamers"}
rtl/ad7980_if.vhd 0 → 100644
View file @ 1bd30289
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dds_wbgen2_pkg.all;
entity ad7980_if is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
trig_i : in std_logic;
d_o : out std_logic_vector(15 downto 0);
d_valid_o : out std_logic;
adc_sdo_i : in std_logic;
adc_sck_o : out std_logic;
adc_cnv_o : out std_logic;
adc_sdi_o : out std_logic
);
end ad7980_if;
architecture rtl of ad7980_if is
component spi_master
generic (
g_div_ratio_log2 : integer;
g_num_data_bits : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
start_i : in std_logic;
cpol_i : in std_logic;
data_i : in std_logic_vector(g_num_data_bits - 1 downto 0);
drdy_o : out std_logic;
ready_o : out std_logic;
data_o : out std_logic_vector(g_num_data_bits - 1 downto 0);
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic);
end component;
signal count : unsigned(7 downto 0);
signal do_acq : std_logic;
type t_state is (WAIT_TRIG, START_CNV, READBACK);
signal state : t_state;
signal d_rdy : std_logic;
begin -- rtl
U_SPI_Master : spi_master
generic map (
g_div_ratio_log2 => 3,
g_num_data_bits => 16)
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
start_i => do_acq,
cpol_i => '0',
data_i => x"0000",
data_o => d_o,
drdy_o => d_rdy,
spi_sclk_o => adc_sck_o,
spi_miso_i => adc_sdo_i);
d_valid_o <= d_rdy;
adc_sdi_o <= '1';
p_acquire : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count <= (others => '0');
adc_cnv_o <= '0';
do_acq <= '0';
state <= WAIT_TRIG;
else
case state is
when WAIT_TRIG =>
if(trig_i = '1') then
count <= (others => '0');
adc_cnv_o <= '1';
state <= START_CNV;
end if;
when START_CNV =>
count<= count +1;
if(count = 100) then
adc_cnv_o <= '0';
do_acq <= '1';
state <= READBACK;
end if;
when READBACK =>
do_acq <= '0';
if(d_rdy = '1') then
state <= WAIT_TRIG;
end if;
end case;
end if;
end if;
end process;
end rtl;
rtl/build_wb.sh 0 → 100755
View file @ 1bd30289
#!/bin/bash
wbgen2 -V dds_wb_slave.vhd -H record -p dds_wbgen2_pkg.vhd -K ../dds_regs.vh -s defines -C dds_regs.h -D doc/dds_regs.html dds_wb_slave.wb
rtl/cic_1024x.vhd 0 → 100644
View file @ 1bd30289
-- -------------------------------------------------------------
--
-- Module: cic_1024x
--
-- Generated by MATLAB(R) 7.10 and the Filter Design HDL Coder 2.6.
--
-- Generated on: 2013-05-06 18:04:46
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- HDL Code Generation Options:
--
-- TargetLanguage: VHDL
-- ResetType: Synchronous
-- ClockEnableInputPort: en_i
-- ClockEnableOutputPort: ce_out_o
-- ClockInputPort: clk_i
-- ResetInputPort: rst_i
-- UseRisingEdge: on
-- EDAScriptGeneration: off
-- AddPipelineRegisters: on
-- InputPort: x_i
-- OutputPort: y_o
-- Name: cic_1024x
-- TestBenchStimulus: step ramp chirp noise
--
-- Filter Settings:
--
-- Discrete-Time FIR Multirate Filter (real)
-- -----------------------------------------
-- Filter Structure : Cascaded Integrator-Comb Interpolator
-- Interpolation Factor : 1024
-- Differential Delay : 1
-- Number of Sections : 7
-- Stable : Yes
-- Linear Phase : No
--
-- Input : s18,15
-- Output : s78,15
-- Filter Internals : Full Precision
-- Integrator Section 1 : s19,15
-- Integrator Section 2 : s20,15
-- Integrator Section 3 : s21,15
-- Integrator Section 4 : s22,15
-- Integrator Section 5 : s23,15
-- Integrator Section 6 : s24,15
-- Integrator Section 7 : s24,15
-- Comb Section 1 : s24,15
-- Comb Section 2 : s33,15
-- Comb Section 3 : s42,15
-- Comb Section 4 : s51,15
-- Comb Section 5 : s60,15
-- Comb Section 6 : s69,15
-- Comb Section 7 : s78,15
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
ENTITY cic_1024x IS
PORT( clk_i : IN std_logic;
en_i : IN std_logic;
rst_i : IN std_logic;
x_i : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En15
y_o : OUT std_logic_vector(77 DOWNTO 0); -- sfix78_En15
ce_out_o : OUT std_logic
);
END cic_1024x;
----------------------------------------------------------------
--Module Architecture: cic_1024x
----------------------------------------------------------------
ARCHITECTURE rtl OF cic_1024x IS
-- Local Functions
-- Type Definitions
-- Constants
CONSTANT zeroconst : signed(23 DOWNTO 0) := to_signed(0, 24); -- sfix24_En15
-- Signals
SIGNAL cur_count : unsigned(9 DOWNTO 0); -- ufix10
SIGNAL phase_0 : std_logic; -- boolean
--
SIGNAL input_register : signed(17 DOWNTO 0); -- sfix18_En15
-- -- Section 1 Signals
SIGNAL section_in1 : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL section_cast1 : signed(18 DOWNTO 0); -- sfix19_En15
SIGNAL diff1 : signed(18 DOWNTO 0); -- sfix19_En15
SIGNAL section_out1 : signed(18 DOWNTO 0); -- sfix19_En15
SIGNAL sub_cast : signed(18 DOWNTO 0); -- sfix19_En15
SIGNAL sub_cast_1 : signed(18 DOWNTO 0); -- sfix19_En15
SIGNAL sub_temp : signed(19 DOWNTO 0); -- sfix20_En15
SIGNAL cic_pipeline1 : signed(18 DOWNTO 0); -- sfix19_En15
-- -- Section 2 Signals
SIGNAL section_in2 : signed(18 DOWNTO 0); -- sfix19_En15
SIGNAL section_cast2 : signed(19 DOWNTO 0); -- sfix20_En15
SIGNAL diff2 : signed(19 DOWNTO 0); -- sfix20_En15
SIGNAL section_out2 : signed(19 DOWNTO 0); -- sfix20_En15
SIGNAL sub_cast_2 : signed(19 DOWNTO 0); -- sfix20_En15
SIGNAL sub_cast_3 : signed(19 DOWNTO 0); -- sfix20_En15
SIGNAL sub_temp_1 : signed(20 DOWNTO 0); -- sfix21_En15
SIGNAL cic_pipeline2 : signed(19 DOWNTO 0); -- sfix20_En15
-- -- Section 3 Signals
SIGNAL section_in3 : signed(19 DOWNTO 0); -- sfix20_En15
SIGNAL section_cast3 : signed(20 DOWNTO 0); -- sfix21_En15
SIGNAL diff3 : signed(20 DOWNTO 0); -- sfix21_En15
SIGNAL section_out3 : signed(20 DOWNTO 0); -- sfix21_En15
SIGNAL sub_cast_4 : signed(20 DOWNTO 0); -- sfix21_En15
SIGNAL sub_cast_5 : signed(20 DOWNTO 0); -- sfix21_En15
SIGNAL sub_temp_2 : signed(21 DOWNTO 0); -- sfix22_En15
SIGNAL cic_pipeline3 : signed(20 DOWNTO 0); -- sfix21_En15
-- -- Section 4 Signals
SIGNAL section_in4 : signed(20 DOWNTO 0); -- sfix21_En15
SIGNAL section_cast4 : signed(21 DOWNTO 0); -- sfix22_En15
SIGNAL diff4 : signed(21 DOWNTO 0); -- sfix22_En15
SIGNAL section_out4 : signed(21 DOWNTO 0); -- sfix22_En15
SIGNAL sub_cast_6 : signed(21 DOWNTO 0); -- sfix22_En15
SIGNAL sub_cast_7 : signed(21 DOWNTO 0); -- sfix22_En15
SIGNAL sub_temp_3 : signed(22 DOWNTO 0); -- sfix23_En15
SIGNAL cic_pipeline4 : signed(21 DOWNTO 0); -- sfix22_En15
-- -- Section 5 Signals
SIGNAL section_in5 : signed(21 DOWNTO 0); -- sfix22_En15
SIGNAL section_cast5 : signed(22 DOWNTO 0); -- sfix23_En15
SIGNAL diff5 : signed(22 DOWNTO 0); -- sfix23_En15
SIGNAL section_out5 : signed(22 DOWNTO 0); -- sfix23_En15
SIGNAL sub_cast_8 : signed(22 DOWNTO 0); -- sfix23_En15
SIGNAL sub_cast_9 : signed(22 DOWNTO 0); -- sfix23_En15
SIGNAL sub_temp_4 : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL cic_pipeline5 : signed(22 DOWNTO 0); -- sfix23_En15
-- -- Section 6 Signals
SIGNAL section_in6 : signed(22 DOWNTO 0); -- sfix23_En15
SIGNAL section_cast6 : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL diff6 : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL section_out6 : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL sub_cast_10 : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL sub_cast_11 : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL sub_temp_5 : signed(24 DOWNTO 0); -- sfix25_En15
SIGNAL cic_pipeline6 : signed(23 DOWNTO 0); -- sfix24_En15
-- -- Section 7 Signals
SIGNAL section_in7 : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL diff7 : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL section_out7 : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL sub_cast_12 : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL sub_cast_13 : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL sub_temp_6 : signed(24 DOWNTO 0); -- sfix25_En15
SIGNAL cic_pipeline7 : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL upsampling : signed(23 DOWNTO 0); -- sfix24_En15
-- -- Section 8 Signals
SIGNAL section_in8 : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL sum1 : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL section_out8 : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL add_cast : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL add_cast_1 : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL add_temp : signed(24 DOWNTO 0); -- sfix25_En15
-- -- Section 9 Signals
SIGNAL section_in9 : signed(23 DOWNTO 0); -- sfix24_En15
SIGNAL section_cast9 : signed(32 DOWNTO 0); -- sfix33_En15
SIGNAL sum2 : signed(32 DOWNTO 0); -- sfix33_En15
SIGNAL section_out9 : signed(32 DOWNTO 0); -- sfix33_En15
SIGNAL add_cast_2 : signed(32 DOWNTO 0); -- sfix33_En15
SIGNAL add_cast_3 : signed(32 DOWNTO 0); -- sfix33_En15
SIGNAL add_temp_1 : signed(33 DOWNTO 0); -- sfix34_En15
-- -- Section 10 Signals
SIGNAL section_in10 : signed(32 DOWNTO 0); -- sfix33_En15
SIGNAL section_cast10 : signed(41 DOWNTO 0); -- sfix42_En15
SIGNAL sum3 : signed(41 DOWNTO 0); -- sfix42_En15
SIGNAL section_out10 : signed(41 DOWNTO 0); -- sfix42_En15
SIGNAL add_cast_4 : signed(41 DOWNTO 0); -- sfix42_En15
SIGNAL add_cast_5 : signed(41 DOWNTO 0); -- sfix42_En15
SIGNAL add_temp_2 : signed(42 DOWNTO 0); -- sfix43_En15
-- -- Section 11 Signals
SIGNAL section_in11 : signed(41 DOWNTO 0); -- sfix42_En15
SIGNAL section_cast11 : signed(50 DOWNTO 0); -- sfix51_En15
SIGNAL sum4 : signed(50 DOWNTO 0); -- sfix51_En15
SIGNAL section_out11 : signed(50 DOWNTO 0); -- sfix51_En15
SIGNAL add_cast_6 : signed(50 DOWNTO 0); -- sfix51_En15
SIGNAL add_cast_7 : signed(50 DOWNTO 0); -- sfix51_En15
SIGNAL add_temp_3 : signed(51 DOWNTO 0); -- sfix52_En15
-- -- Section 12 Signals
SIGNAL section_in12 : signed(50 DOWNTO 0); -- sfix51_En15
SIGNAL section_cast12 : signed(59 DOWNTO 0); -- sfix60_En15
SIGNAL sum5 : signed(59 DOWNTO 0); -- sfix60_En15
SIGNAL section_out12 : signed(59 DOWNTO 0); -- sfix60_En15
SIGNAL add_cast_8 : signed(59 DOWNTO 0); -- sfix60_En15
SIGNAL add_cast_9 : signed(59 DOWNTO 0); -- sfix60_En15
SIGNAL add_temp_4 : signed(60 DOWNTO 0); -- sfix61_En15
-- -- Section 13 Signals
SIGNAL section_in13 : signed(59 DOWNTO 0); -- sfix60_En15
SIGNAL section_cast13 : signed(68 DOWNTO 0); -- sfix69_En15
SIGNAL sum6 : signed(68 DOWNTO 0); -- sfix69_En15
SIGNAL section_out13 : signed(68 DOWNTO 0); -- sfix69_En15
SIGNAL add_cast_10 : signed(68 DOWNTO 0); -- sfix69_En15
SIGNAL add_cast_11 : signed(68 DOWNTO 0); -- sfix69_En15
SIGNAL add_temp_5 : signed(69 DOWNTO 0); -- sfix70_En15
-- -- Section 14 Signals
SIGNAL section_in14 : signed(68 DOWNTO 0); -- sfix69_En15
SIGNAL section_cast14 : signed(77 DOWNTO 0); -- sfix78_En15
SIGNAL sum7 : signed(77 DOWNTO 0); -- sfix78_En15
SIGNAL section_out14 : signed(77 DOWNTO 0); -- sfix78_En15
SIGNAL add_cast_12 : signed(77 DOWNTO 0); -- sfix78_En15
SIGNAL add_cast_13 : signed(77 DOWNTO 0); -- sfix78_En15
SIGNAL add_temp_6 : signed(78 DOWNTO 0); -- sfix79_En15
--
SIGNAL output_register : signed(77 DOWNTO 0); -- sfix78_En15
BEGIN
-- Block Statements
-- ------------------ CE Output Generation ------------------
ce_output : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
cur_count <= to_unsigned(0, 10);
ELSIF en_i = '1' THEN
IF cur_count = to_unsigned(1023, 10) THEN
cur_count <= to_unsigned(0, 10);
ELSE
cur_count <= cur_count + 1;
END IF;
END IF;
END IF;
END PROCESS ce_output;
phase_0 <= '1' WHEN cur_count = to_unsigned(0, 10) AND en_i = '1' ELSE '0';
-- ------------------ Input Register ------------------
input_reg_process : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
input_register <= (OTHERS => '0');
ELSIF phase_0 = '1' THEN
input_register <= signed(x_i);
END IF;
END IF;
END PROCESS input_reg_process;
-- ------------------ Section # 1 : Comb ------------------
section_in1 <= input_register;
section_cast1 <= resize(section_in1, 19);
sub_cast <= section_cast1;
sub_cast_1 <= diff1;
sub_temp <= resize(sub_cast, 20) - resize(sub_cast_1, 20);
section_out1 <= sub_temp(18 DOWNTO 0);
comb_delay_section1 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
diff1 <= (OTHERS => '0');
ELSIF phase_0 = '1' THEN
diff1 <= section_cast1;
END IF;
END IF;
END PROCESS comb_delay_section1;
cic_pipeline_process_section1 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
cic_pipeline1 <= (OTHERS => '0');
ELSIF phase_0 = '1' THEN
cic_pipeline1 <= section_out1;
END IF;
END IF;
END PROCESS cic_pipeline_process_section1;
-- ------------------ Section # 2 : Comb ------------------
section_in2 <= cic_pipeline1;
section_cast2 <= resize(section_in2, 20);
sub_cast_2 <= section_cast2;
sub_cast_3 <= diff2;
sub_temp_1 <= resize(sub_cast_2, 21) - resize(sub_cast_3, 21);
section_out2 <= sub_temp_1(19 DOWNTO 0);
comb_delay_section2 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
diff2 <= (OTHERS => '0');
ELSIF phase_0 = '1' THEN
diff2 <= section_cast2;
END IF;
END IF;
END PROCESS comb_delay_section2;
cic_pipeline_process_section2 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
cic_pipeline2 <= (OTHERS => '0');
ELSIF phase_0 = '1' THEN
cic_pipeline2 <= section_out2;
END IF;
END IF;
END PROCESS cic_pipeline_process_section2;
-- ------------------ Section # 3 : Comb ------------------
section_in3 <= cic_pipeline2;
section_cast3 <= resize(section_in3, 21);
sub_cast_4 <= section_cast3;
sub_cast_5 <= diff3;
sub_temp_2 <= resize(sub_cast_4, 22) - resize(sub_cast_5, 22);
section_out3 <= sub_temp_2(20 DOWNTO 0);
comb_delay_section3 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
diff3 <= (OTHERS => '0');
ELSIF phase_0 = '1' THEN
diff3 <= section_cast3;
END IF;
END IF;
END PROCESS comb_delay_section3;
cic_pipeline_process_section3 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
cic_pipeline3 <= (OTHERS => '0');
ELSIF phase_0 = '1' THEN
cic_pipeline3 <= section_out3;
END IF;
END IF;
END PROCESS cic_pipeline_process_section3;
-- ------------------ Section # 4 : Comb ------------------
section_in4 <= cic_pipeline3;
section_cast4 <= resize(section_in4, 22);
sub_cast_6 <= section_cast4;
sub_cast_7 <= diff4;
sub_temp_3 <= resize(sub_cast_6, 23) - resize(sub_cast_7, 23);
section_out4 <= sub_temp_3(21 DOWNTO 0);
comb_delay_section4 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
diff4 <= (OTHERS => '0');
ELSIF phase_0 = '1' THEN
diff4 <= section_cast4;
END IF;
END IF;
END PROCESS comb_delay_section4;
cic_pipeline_process_section4 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
cic_pipeline4 <= (OTHERS => '0');
ELSIF phase_0 = '1' THEN
cic_pipeline4 <= section_out4;
END IF;
END IF;
END PROCESS cic_pipeline_process_section4;
-- ------------------ Section # 5 : Comb ------------------
section_in5 <= cic_pipeline4;
section_cast5 <= resize(section_in5, 23);
sub_cast_8 <= section_cast5;
sub_cast_9 <= diff5;
sub_temp_4 <= resize(sub_cast_8, 24) - resize(sub_cast_9, 24);
section_out5 <= sub_temp_4(22 DOWNTO 0);
comb_delay_section5 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
diff5 <= (OTHERS => '0');
ELSIF phase_0 = '1' THEN
diff5 <= section_cast5;
END IF;
END IF;
END PROCESS comb_delay_section5;
cic_pipeline_process_section5 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
cic_pipeline5 <= (OTHERS => '0');
ELSIF phase_0 = '1' THEN
cic_pipeline5 <= section_out5;
END IF;
END IF;
END PROCESS cic_pipeline_process_section5;
-- ------------------ Section # 6 : Comb ------------------
section_in6 <= cic_pipeline5;
section_cast6 <= resize(section_in6, 24);
sub_cast_10 <= section_cast6;
sub_cast_11 <= diff6;
sub_temp_5 <= resize(sub_cast_10, 25) - resize(sub_cast_11, 25);
section_out6 <= sub_temp_5(23 DOWNTO 0);
comb_delay_section6 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
diff6 <= (OTHERS => '0');
ELSIF phase_0 = '1' THEN
diff6 <= section_cast6;
END IF;
END IF;
END PROCESS comb_delay_section6;
cic_pipeline_process_section6 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
cic_pipeline6 <= (OTHERS => '0');
ELSIF phase_0 = '1' THEN
cic_pipeline6 <= section_out6;
END IF;
END IF;
END PROCESS cic_pipeline_process_section6;
-- ------------------ Section # 7 : Comb ------------------
section_in7 <= cic_pipeline6;
sub_cast_12 <= section_in7;
sub_cast_13 <= diff7;
sub_temp_6 <= resize(sub_cast_12, 25) - resize(sub_cast_13, 25);
section_out7 <= sub_temp_6(23 DOWNTO 0);
comb_delay_section7 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
diff7 <= (OTHERS => '0');
ELSIF phase_0 = '1' THEN
diff7 <= section_in7;
END IF;
END IF;
END PROCESS comb_delay_section7;
cic_pipeline_process_section7 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
cic_pipeline7 <= (OTHERS => '0');
ELSIF phase_0 = '1' THEN
cic_pipeline7 <= section_out7;
END IF;
END IF;
END PROCESS cic_pipeline_process_section7;
upsampling <= cic_pipeline7 WHEN ( phase_0 = '1' ) ELSE
zeroconst;
-- ------------------ Section # 8 : Integrator ------------------
section_in8 <= upsampling;
add_cast <= section_in8;
add_cast_1 <= section_out8;
add_temp <= resize(add_cast, 25) + resize(add_cast_1, 25);
sum1 <= add_temp(23 DOWNTO 0);
integrator_delay_section8 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
section_out8 <= (OTHERS => '0');
ELSIF en_i = '1' THEN
section_out8 <= sum1;
END IF;
END IF;
END PROCESS integrator_delay_section8;
-- ------------------ Section # 9 : Integrator ------------------
section_in9 <= section_out8;
section_cast9 <= resize(section_in9, 33);
add_cast_2 <= section_cast9;
add_cast_3 <= section_out9;
add_temp_1 <= resize(add_cast_2, 34) + resize(add_cast_3, 34);
sum2 <= add_temp_1(32 DOWNTO 0);
integrator_delay_section9 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
section_out9 <= (OTHERS => '0');
ELSIF en_i = '1' THEN
section_out9 <= sum2;
END IF;
END IF;
END PROCESS integrator_delay_section9;
-- ------------------ Section # 10 : Integrator ------------------
section_in10 <= section_out9;
section_cast10 <= resize(section_in10, 42);
add_cast_4 <= section_cast10;
add_cast_5 <= section_out10;
add_temp_2 <= resize(add_cast_4, 43) + resize(add_cast_5, 43);
sum3 <= add_temp_2(41 DOWNTO 0);
integrator_delay_section10 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
section_out10 <= (OTHERS => '0');
ELSIF en_i = '1' THEN
section_out10 <= sum3;
END IF;
END IF;
END PROCESS integrator_delay_section10;
-- ------------------ Section # 11 : Integrator ------------------
section_in11 <= section_out10;
section_cast11 <= resize(section_in11, 51);
add_cast_6 <= section_cast11;
add_cast_7 <= section_out11;
add_temp_3 <= resize(add_cast_6, 52) + resize(add_cast_7, 52);
sum4 <= add_temp_3(50 DOWNTO 0);
integrator_delay_section11 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
section_out11 <= (OTHERS => '0');
ELSIF en_i = '1' THEN
section_out11 <= sum4;
END IF;
END IF;
END PROCESS integrator_delay_section11;
-- ------------------ Section # 12 : Integrator ------------------
section_in12 <= section_out11;
section_cast12 <= resize(section_in12, 60);
add_cast_8 <= section_cast12;
add_cast_9 <= section_out12;
add_temp_4 <= resize(add_cast_8, 61) + resize(add_cast_9, 61);
sum5 <= add_temp_4(59 DOWNTO 0);
integrator_delay_section12 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
section_out12 <= (OTHERS => '0');
ELSIF en_i = '1' THEN
section_out12 <= sum5;
END IF;
END IF;
END PROCESS integrator_delay_section12;
-- ------------------ Section # 13 : Integrator ------------------
section_in13 <= section_out12;
section_cast13 <= resize(section_in13, 69);
add_cast_10 <= section_cast13;
add_cast_11 <= section_out13;
add_temp_5 <= resize(add_cast_10, 70) + resize(add_cast_11, 70);
sum6 <= add_temp_5(68 DOWNTO 0);
integrator_delay_section13 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
section_out13 <= (OTHERS => '0');
ELSIF en_i = '1' THEN
section_out13 <= sum6;
END IF;
END IF;
END PROCESS integrator_delay_section13;
-- ------------------ Section # 14 : Integrator ------------------
section_in14 <= section_out13;
section_cast14 <= resize(section_in14, 78);
add_cast_12 <= section_cast14;
add_cast_13 <= section_out14;
add_temp_6 <= resize(add_cast_12, 79) + resize(add_cast_13, 79);
sum7 <= add_temp_6(77 DOWNTO 0);
integrator_delay_section14 : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
section_out14 <= (OTHERS => '0');
ELSIF en_i = '1' THEN
section_out14 <= sum7;
END IF;
END IF;
END PROCESS integrator_delay_section14;
-- ------------------ Output Register ------------------
output_reg_process : PROCESS (clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
output_register <= (OTHERS => '0');
ELSIF en_i = '1' THEN
output_register <= section_out14;
END IF;
END IF;
END PROCESS output_reg_process;
-- Assignment Statements
ce_out_o <= phase_0;
y_o <= std_logic_vector(output_register);
END rtl;
rtl/dds_core.vhd 0 → 100644
View file @ 1bd30289
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
use work.dds_wbgen2_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
use work.streamers_pkg.all;
entity dds_core is
port (
-- Clocks & resets
clk_sys_i : in std_logic;
clk_dds_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
-- Timing (WRC)
tm_time_valid_i : in std_logic;
tm_tai_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
-- DDS Dac I/F (Maxim)
dac_n_o : out std_logic_vector(13 downto 0);
dac_p_o : out std_logic_vector(13 downto 0);
dac_pwdn_o : out std_logic;
-- AD9516 (SYS) and AD9510 (VCXO cleaner) PLL control
clk_dds_locked_i : in std_logic;
pll_vcxo_cs_n_o : out std_logic;
pll_vcxo_function_o : out std_logic;
pll_vcxo_sdo_i : in std_logic;
pll_vcxo_status_i : in std_logic;
pll_sys_cs_n_o : out std_logic;
pll_sys_refmon_i : in std_logic;
pll_sys_ld_i : in std_logic;
pll_sys_reset_n_o : out std_logic;
pll_sys_status_i : in std_logic;
pll_sys_sync_n_o : out std_logic;
pll_sclk_o : out std_logic;
pll_sdio_b : inout std_logic;
-- Phase Detector & ADC
pd_ce_o : out std_logic;
pd_lockdet_i : in std_logic;
pd_clk_o : out std_logic;
pd_data_b : inout std_logic;
pd_le_o : out std_logic;
adc_sdo_i : in std_logic;
adc_sck_o : out std_logic;
adc_cnv_o : out std_logic;
adc_sdi_o : out std_logic;
si57x_oe_o : out std_logic;
si57x_sda_b : inout std_logic;
si57x_scl_b : inout std_logic;
-- WB & WRF
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
swrst_o : out std_logic;
fpll_reset_o : out std_logic
);
end dds_core;
architecture behavioral of dds_core is
constant c_cnx_base_addr : t_wishbone_address_array(1 downto 0) :=
(x"00000000", -- WB regs
x"00004000" -- MDSP core
);
constant c_cnx_base_mask : t_wishbone_address_array(1 downto 0) :=
(x"00004000",
x"00004000");
function resize(x : std_logic_vector; new_size : integer)
return std_logic_vector is
variable tmp : std_logic_vector(new_size-1 downto 0);
begin
if(new_size <= x'length) then
tmp := x(new_size-1 downto 0);
else
tmp := std_logic_vector(to_unsigned(0, x'length-new_size)) & x;
end if;
return tmp;
end function;
component dds_wb_slave
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
clk_ref_i : in std_logic;
regs_i : in t_dds_in_registers;
regs_o : out t_dds_out_registers);
end component;
component ad7980_if
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
trig_i : in std_logic;
d_o : out std_logic_vector(15 downto 0);
d_valid_o : out std_logic;
adc_sdo_i : in std_logic;
adc_sck_o : out std_logic;
adc_cnv_o : out std_logic;
adc_sdi_o : out std_logic);
end component;
component max5870_serializer
generic (
sys_w : integer := 14;
dev_w : integer := 56);
port (
DATA_OUT_FROM_DEVICE : in std_logic_vector(dev_w-1 downto 0);
DATA_OUT_TO_PINS_P : out std_logic_vector(sys_w-1 downto 0);
DATA_OUT_TO_PINS_N : out std_logic_vector(sys_w-1 downto 0);
CLK_IN : in std_logic;
CLK_DIV_IN : in std_logic;
LOCKED_IN : in std_logic;
LOCKED_OUT : out std_logic;
CLK_RESET : in std_logic;
IO_RESET : in std_logic);
end component;
component dds_quad_channel
generic(
g_acc_frac_bits : integer := 32;
g_lut_size_log2 : integer := 10;
g_output_bits : integer := 14);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
acc_i : in std_logic_vector(g_lut_size_log2 + g_acc_frac_bits downto 0);
acc_o : out std_logic_vector(g_lut_size_log2 + g_acc_frac_bits downto 0);
dreq_i : in std_logic;
tune_i : in std_logic_vector(g_lut_size_log2 + g_acc_frac_bits downto 0);
tune_load_i : in std_logic;
acc_load_i : in std_logic;
y0_o : out std_logic_vector(g_output_bits-1 downto 0);
y1_o : out std_logic_vector(g_output_bits-1 downto 0);
y2_o : out std_logic_vector(g_output_bits-1 downto 0);
y3_o : out std_logic_vector(g_output_bits-1 downto 0)
);
end component;
component pi_control
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
d_valid_i : in std_logic;
d_i : in std_logic_vector(15 downto 0);
q_valid_o : out std_logic;
q_o : out std_logic_vector(15 downto 0);
ki_i : in std_logic_vector(15 downto 0);
kp_i : in std_logic_vector(15 downto 0)
);
end component;
component cic_1024x
port (
clk_i : in std_logic;
en_i : in std_logic;
rst_i : in std_logic;
x_i : in std_logic_vector(17 downto 0);
y_o : out std_logic_vector(77 downto 0);
ce_out_o : out std_logic);
end component;
component mdsp
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
x_req_o : out std_logic;
x_valid_i : in std_logic;
x_i : in std_logic_vector(23 downto 0);
y_valid_o : out std_logic;
y_req_i : in std_logic;
y_o : out std_logic_vector(23 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_stall_o : out std_logic;
wb_ack_o : out std_logic
);
end component;
signal dac_data_par : std_logic_vector(14 * 4 - 1 downto 0);
signal cnx_out : t_wishbone_master_out_array(0 to 1);
signal cnx_in : t_wishbone_master_in_array(0 to 1);
signal synth_tune, synth_tune_d0, synth_tune_d1, synth_tune_bias, synth_acc_in, synth_acc_out : std_logic_vector(42 downto 0);
signal synth_tune_load, synth_acc_load : std_logic;
signal synth_y0, synth_y1, synth_y2, synth_y3 : std_logic_vector(13 downto 0);
signal regs_in : t_dds_in_registers;
signal regs_out : t_dds_out_registers;
signal swrst, swrst_n, rst_n_ref, rst_ref : std_logic;
signal cic_out : std_logic_vector(77 downto 0);
signal cic_in, cic_out_clamp : std_logic_vector(17 downto 0);
signal cic_ce : std_logic;
function f_signed_multiply(a : std_logic_vector; b : std_logic_vector; shift : integer; output_length : integer)
return std_logic_vector is
variable mul : signed(a'length + b'length downto 0);
variable result : std_logic_vector(output_length-1 downto 0);
begin
mul := signed(a) * signed('0' & b);
result := std_logic_vector(resize(mul(mul'length-1 downto shift), output_length));
return result;
end f_signed_multiply;
signal tune_empty_d0 : std_logic;
signal adc_data : std_logic_vector(15 downto 0);
signal adc_dvalid : std_logic;
signal mdsp_out : std_logic_vector(23 downto 0);
signal pi_out : std_logic_vector(15 downto 0);
signal mdsp_in : std_logic_vector(23 downto 0);
function f_sign_extend(x : std_logic_vector; output_length : integer) return std_logic_vector is
variable tmp : std_logic_vector(output_length-1 downto 0);
begin
tmp(x'length-1 downto 0) := x;
tmp(output_length-1 downto x'length) := (others => x(x'length-1));
return tmp;
end f_sign_extend;
begin -- behavioral
U_Ref_Reset_SC : gc_sync_ffs
port map (
clk_i => clk_ref_i,
rst_n_i => '1',
data_i => swrst_n,
synced_o => rst_n_ref);
U_Intercon : xwb_crossbar
generic map (
g_num_masters => 1,
g_num_slaves => 2,
g_registered => true,
g_address => c_cnx_base_addr,
g_mask => c_cnx_base_mask)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i(0) => slave_i,
slave_o(0) => slave_o,
master_i => cnx_in,
master_o => cnx_out);
U_WB_Slave : dds_wb_slave
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => cnx_out(0).adr(5 downto 2),
wb_dat_i => cnx_out(0).dat,
wb_dat_o => cnx_in(0).dat,
wb_cyc_i => cnx_out(0).cyc,
wb_sel_i => cnx_out(0).sel,
wb_stb_i => cnx_out(0).stb,
wb_we_i => cnx_out(0).we,
wb_ack_o => cnx_in(0).ack,
wb_stall_o => cnx_in(0).stall,
clk_ref_i => clk_ref_i,
regs_i => regs_in,
regs_o => regs_out);
U_ADC_Interface : ad7980_if
port map (
clk_i => clk_ref_i,
rst_n_i => rst_n_ref,
trig_i => cic_ce,
d_o => adc_data,
d_valid_o => adc_dvalid,
adc_sdo_i => adc_sdo_i,
adc_sck_o => adc_sck_o,
adc_cnv_o => adc_cnv_o,
adc_sdi_o => adc_sdi_o);
regs_in.pd_fifo_data_i <= adc_data;
regs_in.pd_fifo_wr_req_i <= adc_dvalid and not regs_out.pd_fifo_wr_full_o;
dac_pwdn_o <= '1';
U_DAC_Serializer : max5870_serializer
port map (
DATA_OUT_FROM_DEVICE => dac_data_par,
DATA_OUT_TO_PINS_P => dac_p_o,
DATA_OUT_TO_PINS_N => dac_n_o,
CLK_IN => clk_dds_i,
CLK_DIV_IN => clk_ref_i,
LOCKED_IN => clk_dds_locked_i,
LOCKED_OUT => open,
CLK_RESET => rst_ref,
IO_RESET => rst_ref);
U_DDS_Synthesizer : dds_quad_channel
generic map (
g_acc_frac_bits => 32,
g_lut_size_log2 => 10,
g_output_bits => 14)
port map (
clk_i => clk_ref_i,
rst_n_i => rst_n_ref,
acc_i => synth_acc_in,
acc_o => synth_acc_out,
dreq_i => '1',
tune_i => synth_tune_d1,
tune_load_i => synth_tune_load,
acc_load_i => synth_acc_load,
y0_o => synth_y0,
y1_o => synth_y1,
y2_o => synth_y2,
y3_o => synth_y3);
U_Cic : cic_1024x
port map (
clk_i => clk_ref_i,
en_i => '1',
rst_i => rst_ref,
x_i => cic_in,
y_o => cic_out,
ce_out_o => cic_ce);
--mdsp_in <= std_logic_vector(resize(signed(unsigned(adc_data) - to_unsigned(32767, 16)),24));
pi_control_1: pi_control
port map (
clk_i => clk_ref_i,
rst_n_i => rst_n_ref,
d_valid_i => adc_dvalid,
d_i => adc_data,
q_valid_o => open,
q_o => pi_out,
ki_i => regs_out.pir_ki_o,
kp_i => regs_out.pir_kp_o);
--U_The_DSP : mdsp
-- port map (
-- clk_i => clk_ref_i,
-- rst_n_i => rst_n_i,
-- x_req_o => open,
-- x_valid_i => adc_dvalid,
-- x_i => mdsp_in,
-- y_valid_o => open,
-- y_req_i => '1',
-- y_o => mdsp_out,
-- wb_cyc_i => cnx_out(1).cyc,
-- wb_stb_i => cnx_out(1).stb,
-- wb_we_i => cnx_out(1).we,
-- wb_adr_i => cnx_out(1).adr,
-- wb_dat_i => cnx_out(1).dat,
-- wb_dat_o => cnx_in(1).dat,
-- wb_stall_o => cnx_in(1).stall,
-- wb_ack_o => cnx_in(1).ack);
cic_out_clamp <= cic_out(cic_out'length-1 downto cic_out'length - cic_out_clamp'length);
p_choose_tune_source : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if(regs_out.cr_test_o = '1') then
if(tune_empty_d0 = '1') then
cic_in <= (others => '0');
else
cic_in <= regs_out.tune_fifo_data_o(17 downto 0);
end if;
elsif(regs_out.cr_master_o = '1') then
--if(signed(mdsp_out(15 downto 0)) < -32000) then
-- cic_in <= std_logic_vector(to_signed(-32000, 18));
--elsif (signed(mdsp_out(15 downto 0)) > 32000) then
-- cic_in <= std_logic_vector(to_signed(32000, 18));
--else
cic_in <= pi_out(15) & pi_out(15) & pi_out;
--end if;
else
cic_in <= (others => '0');
end if;
end if;
end process;
regs_in.tune_fifo_rd_req_i <= not regs_out.tune_fifo_rd_empty_o and cic_ce;
process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' then
tune_empty_d0 <= '1';
elsif(cic_ce = '1') then
tune_empty_d0 <= regs_out.tune_fifo_rd_empty_o;
end if;
end if;
end process;
p_gen_tune : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if(rst_n_ref = '0') then
synth_tune <= (others => '0');
synth_tune_d0 <= (others => '0');
synth_tune_d1 <= (others => '0');
synth_tune_bias <= (others => '0');
synth_tune_load <= '0';
else
synth_tune_bias(31 downto 0) <= regs_out.freq_lo_o;
synth_tune_bias(42 downto 32) <= regs_out.freq_hi_o(10 downto 0);
synth_tune <= std_logic_vector(unsigned(synth_tune_bias) + unsigned(f_signed_multiply(cic_out_clamp, regs_out.gain_o, 0, synth_tune_bias'length)));
synth_tune_d0 <= synth_tune;
synth_tune_d1 <= synth_tune_d0;
synth_tune_load <= '1';
synth_acc_load <= '0';
dac_data_par <= synth_y3 & synth_y2 & synth_y1 & synth_y0;
end if;
end if;
end process;
swrst <= regs_out.rstr_sw_rst_o or (not rst_n_i);
swrst_o <= swrst;
swrst_n <= not swrst;
fpll_reset_o <= regs_out.rstr_pll_rst_o or (not rst_n_i);
rst_ref <= not rst_n_ref;
pll_vcxo_cs_n_o <= regs_out.gpior_pll_vcxo_cs_n_o;
pll_vcxo_function_o <= regs_out.gpior_pll_vcxo_function_o;
regs_in.gpior_pll_vcxo_sdo_i <= pll_vcxo_sdo_i;
pll_sys_cs_n_o <= regs_out.gpior_pll_sys_cs_n_o;
pll_sys_reset_n_o <= regs_out.gpior_pll_sys_reset_n_o;
pll_sys_sync_n_o <= '1';
pll_sclk_o <= regs_out.gpior_pll_sclk_o;
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if regs_out.gpior_pll_sdio_load_o = '1' then
pll_sdio_b <= regs_out.gpior_pll_sdio_o;
end if;
end if;
end process;
regs_in.gpior_pll_sdio_i <= pll_vcxo_sdo_i;
pd_ce_o <= regs_out.gpior_adf_ce_o;
pd_clk_o <= regs_out.gpior_adf_clk_o;
pd_data_b <= regs_out.gpior_adf_data_o;
pd_le_o <= regs_out.gpior_adf_le_o;
-- regs_in.gpior_adc_sdo_i <= adc_sdo_i;
-- adc_sck_o <= regs_out.gpior_adc_sck_o;
-- adc_cnv_o <= regs_out.gpior_adc_cnv_o;
-- adc_sdi_o <= regs_out.gpior_adc_sdi_o;
si57x_oe_o <= '1';
si57x_scl_b <= '0' when (regs_out.i2cr_scl_out_o = '0') else 'Z';
si57x_sda_b <= '0' when (regs_out.i2cr_sda_out_o = '0') else 'Z';
regs_in.i2cr_scl_in_i <= si57x_scl_b;
regs_in.i2cr_sda_in_i <= si57x_sda_b;
end behavioral;
rtl/dds_quad_channel.v 0 → 100644
View file @ 1bd30289
`timescale 1ns/1ps
module dds_quad_channel
(
clk_i,
rst_n_i,
acc_i,
acc_o,
dreq_i,
tune_i,
tune_load_i,
acc_load_i,
y0_o,
y1_o,
y2_o,
y3_o);
parameter integer g_acc_frac_bits = 32;
parameter integer g_output_bits = 14;
parameter integer g_lut_sample_bits= 18;
parameter integer g_lut_slope_bits = 18;
parameter integer g_interp_shift = 7;
parameter integer g_lut_size_log2 = 10;
parameter integer g_dither_taps = 32'hD0000001;
parameter integer g_dither_length = 32;
localparam c_acc_bits = g_acc_frac_bits + g_lut_size_log2 + 1;
localparam c_lut_cell_size = g_lut_sample_bits + g_lut_slope_bits;
input clk_i;
input rst_n_i;
input acc_load_i;
input tune_load_i;
input [g_acc_frac_bits + g_lut_size_log2 : 0] acc_i;
output reg [g_acc_frac_bits + g_lut_size_log2 : 0] acc_o;
input [g_acc_frac_bits + g_lut_size_log2 : 0] tune_i;
input dreq_i;
output wire [g_output_bits-1:0] y0_o, y1_o, y2_o, y3_o;
wire [g_lut_size_log2-1:0] lut_addr[0:3];
reg [c_lut_cell_size-1:0] lut_data[0:3];
reg [c_acc_bits-1:0] acc, acc_d0, acc_f[0:3], tune;
wire [g_output_bits-1:0] y[0:3];
always@(posedge clk_i)
begin
if(!rst_n_i)begin
tune <= 0;
acc <= 0;
end else begin
if(tune_load_i)
tune <= tune_i;
if(acc_load_i)
acc <= acc_i;
else if(dreq_i) begin
acc <= acc + tune;
acc_d0 <= acc;
acc_o <= acc;
acc_f[0] <= acc_d0;
acc_f[1] <= acc_d0 + (tune >> 2);
acc_f[2] <= acc_d0 + (tune >> 1);
acc_f[3] <= acc_d0 + (tune >> 2) + (tune >> 1);
end
end // else: !if(!rst_n_i)
end // always@ (posedge clk_i)
generate
genvar i;
for(i=0;i<4;i=i+1)
begin
dds_stage
#(
.g_acc_frac_bits(g_acc_frac_bits),
.g_output_bits(g_output_bits),
.g_lut_size_log2(g_lut_size_log2),
.g_dither_init_value(i*1234567)
)
U_Stage_X
(
.clk_i(clk_i),
.rst_n_i(rst_n_i),
.acc_i(acc_f[i]),
.y_o(y[i]),
.dreq_i(dreq_i),
.lut_addr_o(lut_addr[i]),
.lut_data_i(lut_data[i])
);
end // for (i=0;i<4;i++)
endgenerate
reg [g_lut_sample_bits + g_lut_slope_bits-1:0] lut01[0:2**g_lut_size_log2-1];
reg [g_lut_sample_bits + g_lut_slope_bits-1:0] lut23[0:2**g_lut_size_log2-1];
`include "lut_init.v"
initial begin
`INIT_LUT(01)
`INIT_LUT(23)
end
always@(posedge clk_i)
lut_data[0] <= lut01[lut_addr[0]];
always@(posedge clk_i)
lut_data[1] <= lut01[lut_addr[1]];
always@(posedge clk_i)
lut_data[2] <= lut23[lut_addr[2]];
always@(posedge clk_i)
lut_data[3] <= lut23[lut_addr[3]];
assign y0_o = y[0];
assign y1_o = y[1];
assign y2_o = y[2];
assign y3_o = y[3];
endmodule // dds_quad_channel
\ No newline at end of file
rtl/dds_stage.v 0 → 100644
View file @ 1bd30289
`timescale 1ns/1ps
module dds_stage
(
clk_i,
rst_n_i,
acc_i,
dreq_i,
y_o,
lut_addr_o,
lut_data_i
);
parameter integer g_acc_frac_bits = 32;
parameter integer g_dither_init_value = 32'h00000001;
parameter integer g_output_bits = 12;
parameter integer g_lut_sample_bits= 18;
parameter integer g_lut_slope_bits = 18;
parameter integer g_interp_shift = 7;
parameter integer g_lut_size_log2 = 12;
parameter integer g_dither_taps = 32'hD0000001;
parameter integer g_dither_length = 32;
localparam c_dither_bits = (g_lut_sample_bits - g_output_bits - 1);
localparam c_acc_bits = g_acc_frac_bits + g_lut_size_log2 + 1;
localparam c_output_shift = g_lut_sample_bits - g_output_bits;
wire signed [c_dither_bits :0 ] dither_in;
input clk_i;
input rst_n_i;
input [g_acc_frac_bits + g_lut_size_log2 : 0] acc_i;
input dreq_i;
output reg [g_output_bits-1:0] y_o;
output reg [g_lut_size_log2-1:0] lut_addr_o;
input [g_lut_sample_bits + g_lut_slope_bits - 1:0] lut_data_i;
reg [c_acc_bits-1:0] acc0, acc1, tune;
wire [g_lut_size_log2 : 0] phase;
wire [g_lut_slope_bits-1 : 0] frac;
reg [g_lut_slope_bits-1 : 0] frac_d0, frac_d1, frac_d2, frac_d3;
wire half;
reg [g_lut_size_log2-1:0] addr0, addr1,tmp,tmp2,tmp3;
reg [8:0] sign;
reg [g_lut_sample_bits + g_lut_slope_bits-1:0] lut_in;
wire signed [g_lut_slope_bits-1:0] lut_slope;
reg signed [g_lut_slope_bits-1:0] slope_d0;
wire signed [g_lut_sample_bits-1:0] lut_sample;
reg signed [g_lut_sample_bits-1:0] sample_d0;
reg signed [g_lut_sample_bits-1:0] interp, interp_d0;
reg signed [g_lut_sample_bits-1:0] qv;
reg signed [g_output_bits:0] yt;
wire signed [2*g_lut_slope_bits-1:0] interp_mul;
reg [g_dither_length-1:0] lfsr=g_dither_init_value;
assign lut_slope = lut_in[g_lut_sample_bits + g_lut_slope_bits - 1 : g_lut_sample_bits ];
assign lut_sample = lut_in[g_lut_sample_bits - 1 : 0];
assign phase = acc_i [ g_acc_frac_bits + g_lut_size_log2 - 1 : g_acc_frac_bits - 1];
assign half = acc_i [g_acc_frac_bits + g_lut_size_log2];
assign frac = acc_i [g_acc_frac_bits - 1 : g_acc_frac_bits-g_lut_slope_bits];
always@(posedge clk_i)
begin
if (!rst_n_i) begin
lfsr <= g_dither_init_value;
end else if (dreq_i) begin
if(lfsr[0])
lfsr <= {1'b0, lfsr[g_dither_length-1:1]} ^ g_dither_taps;
else
lfsr <= {1'b0, lfsr[g_dither_length-1:1]};
end
end
wire signed [g_lut_slope_bits:0] interp_frac;
assign interp_frac = {1'b0, frac_d3};
assign dither_in = { lfsr[c_dither_bits+4:5], 1'b0 };
assign interp_mul = lut_slope * interp_frac;
always@(posedge clk_i)
begin
if (!rst_n_i) begin
end else if(dreq_i) begin
addr0 <= acc_i[g_acc_frac_bits + g_lut_size_log2-1 : g_acc_frac_bits];
sign <= {sign[7:0], half };
lut_addr_o <= addr0;
lut_in <= lut_data_i;
frac_d0 <= frac;
frac_d1 <= frac_d0;
frac_d2 <= frac_d1;
frac_d3 <= frac_d2;
interp <= interp_mul >>> (g_lut_slope_bits + g_interp_shift);
sample_d0 <= lut_sample;
qv <= (sample_d0) + (interp) + (dither_in) + 1;
if(sign[5])
yt <= qv >>> (c_output_shift-1);
else
yt <= (-qv) >>> (c_output_shift-1);
if(yt[0])
y_o <= (yt[g_output_bits:1] + (1<<(g_output_bits - 1)) + 1);
else
y_o <= (yt[g_output_bits:1] + (1<<(g_output_bits - 1)));
end // if (dreq_i)
end // always@ (posedge clk_i)
endmodule // dds_single_channel
rtl/dds_wb_slave.vhd 0 → 100644
View file @ 1bd30289
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for DDS RF distribution WB Slave
---------------------------------------------------------------------------------------
-- File : dds_wb_slave.vhd
-- Author : auto-generated by wbgen2 from dds_wb_slave.wb
-- Created : Fri May 10 01:11:43 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dds_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
use work.dds_wbgen2_pkg.all;
entity dds_wb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
clk_ref_i : in std_logic;
regs_i : in t_dds_in_registers;
regs_o : out t_dds_out_registers
);
end dds_wb_slave;
architecture syn of dds_wb_slave is
signal dds_cr_test_int : std_logic ;
signal dds_cr_slave_int : std_logic ;
signal dds_cr_master_int : std_logic ;
signal dds_cr_adc_bb_enable_dly0 : std_logic ;
signal dds_cr_adc_bb_enable_int : std_logic ;
signal dds_cr_clk_id_int : std_logic_vector(15 downto 0);
signal dds_gpior_pll_sys_cs_n_int : std_logic ;
signal dds_gpior_pll_sys_reset_n_int : std_logic ;
signal dds_gpior_pll_sclk_int : std_logic ;
signal dds_gpior_pll_sdio_dir_int : std_logic ;
signal dds_gpior_pll_vcxo_reset_n_int : std_logic ;
signal dds_gpior_pll_vcxo_cs_n_int : std_logic ;
signal dds_gpior_pll_vcxo_function_int : std_logic ;
signal dds_gpior_adf_ce_int : std_logic ;
signal dds_gpior_adf_clk_int : std_logic ;
signal dds_gpior_adf_le_int : std_logic ;
signal dds_gpior_adf_data_int : std_logic ;
signal dds_gpior_adc_sdi_int : std_logic ;
signal dds_gpior_adc_cnv_int : std_logic ;
signal dds_gpior_adc_sck_int : std_logic ;
signal dds_pd_fifo_rst_n : std_logic ;
signal dds_pd_fifo_in_int : std_logic_vector(15 downto 0);
signal dds_pd_fifo_out_int : std_logic_vector(15 downto 0);
signal dds_pd_fifo_rdreq_int : std_logic ;
signal dds_pd_fifo_rdreq_int_d0 : std_logic ;
signal dds_tune_fifo_rst_n : std_logic ;
signal dds_tune_fifo_in_int : std_logic_vector(31 downto 0);
signal dds_tune_fifo_out_int : std_logic_vector(31 downto 0);
signal dds_tune_fifo_wrreq_int : std_logic ;
signal dds_freq_hi_int : std_logic_vector(31 downto 0);
signal dds_freq_hi_swb : std_logic ;
signal dds_freq_hi_swb_delay : std_logic ;
signal dds_freq_hi_swb_s0 : std_logic ;
signal dds_freq_hi_swb_s1 : std_logic ;
signal dds_freq_hi_swb_s2 : std_logic ;
signal dds_freq_lo_int : std_logic_vector(31 downto 0);
signal dds_freq_lo_swb : std_logic ;
signal dds_freq_lo_swb_delay : std_logic ;
signal dds_freq_lo_swb_s0 : std_logic ;
signal dds_freq_lo_swb_s1 : std_logic ;
signal dds_freq_lo_swb_s2 : std_logic ;
signal dds_gain_int : std_logic_vector(15 downto 0);
signal dds_gain_swb : std_logic ;
signal dds_gain_swb_delay : std_logic ;
signal dds_gain_swb_s0 : std_logic ;
signal dds_gain_swb_s1 : std_logic ;
signal dds_gain_swb_s2 : std_logic ;
signal dds_rstr_pll_rst_int : std_logic ;
signal dds_rstr_sw_rst_int : std_logic ;
signal dds_i2cr_scl_out_int : std_logic ;
signal dds_i2cr_sda_out_int : std_logic ;
signal dds_pir_kp_int : std_logic_vector(15 downto 0);
signal dds_pir_ki_int : std_logic_vector(15 downto 0);
signal dds_pd_fifo_full_int : std_logic ;
signal dds_pd_fifo_empty_int : std_logic ;
signal dds_tune_fifo_full_int : std_logic ;
signal dds_tune_fifo_empty_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
dds_cr_test_int <= '0';
dds_cr_slave_int <= '0';
dds_cr_master_int <= '0';
dds_cr_adc_bb_enable_int <= '0';
dds_cr_clk_id_int <= "0000000000000000";
dds_gpior_pll_sys_cs_n_int <= '0';
dds_gpior_pll_sys_reset_n_int <= '0';
dds_gpior_pll_sclk_int <= '0';
regs_o.gpior_pll_sdio_load_o <= '0';
dds_gpior_pll_sdio_dir_int <= '0';
dds_gpior_pll_vcxo_reset_n_int <= '0';
dds_gpior_pll_vcxo_cs_n_int <= '0';
dds_gpior_pll_vcxo_function_int <= '0';
dds_gpior_adf_ce_int <= '0';
dds_gpior_adf_clk_int <= '0';
dds_gpior_adf_le_int <= '0';
dds_gpior_adf_data_int <= '0';
dds_gpior_adc_sdi_int <= '0';
dds_gpior_adc_cnv_int <= '0';
dds_gpior_adc_sck_int <= '0';
dds_freq_hi_int <= "00000000000000000000000000000000";
dds_freq_hi_swb <= '0';
dds_freq_hi_swb_delay <= '0';
dds_freq_lo_int <= "00000000000000000000000000000000";
dds_freq_lo_swb <= '0';
dds_freq_lo_swb_delay <= '0';
dds_gain_int <= "0000000000000000";
dds_gain_swb <= '0';
dds_gain_swb_delay <= '0';
dds_rstr_pll_rst_int <= '0';
dds_rstr_sw_rst_int <= '0';
dds_i2cr_scl_out_int <= '1';
dds_i2cr_sda_out_int <= '1';
dds_pir_kp_int <= "0000000000000000";
dds_pir_ki_int <= "0000000000000000";
dds_pd_fifo_rdreq_int <= '0';
dds_tune_fifo_wrreq_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
dds_cr_adc_bb_enable_int <= '0';
regs_o.gpior_pll_sdio_load_o <= '0';
dds_tune_fifo_wrreq_int <= '0';
ack_in_progress <= '0';
else
regs_o.gpior_pll_sdio_load_o <= '0';
dds_freq_hi_swb <= dds_freq_hi_swb_delay;
dds_freq_hi_swb_delay <= '0';
dds_freq_lo_swb <= dds_freq_lo_swb_delay;
dds_freq_lo_swb_delay <= '0';
dds_gain_swb <= dds_gain_swb_delay;
dds_gain_swb_delay <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
dds_cr_test_int <= wrdata_reg(0);
dds_cr_slave_int <= wrdata_reg(1);
dds_cr_master_int <= wrdata_reg(2);
dds_cr_adc_bb_enable_int <= wrdata_reg(3);
dds_cr_clk_id_int <= wrdata_reg(19 downto 4);
end if;
rddata_reg(0) <= dds_cr_test_int;
rddata_reg(1) <= dds_cr_slave_int;
rddata_reg(2) <= dds_cr_master_int;
rddata_reg(3) <= '0';
rddata_reg(19 downto 4) <= dds_cr_clk_id_int;
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
dds_gpior_pll_sys_cs_n_int <= wrdata_reg(0);
dds_gpior_pll_sys_reset_n_int <= wrdata_reg(1);
dds_gpior_pll_sclk_int <= wrdata_reg(2);
regs_o.gpior_pll_sdio_load_o <= '1';
dds_gpior_pll_sdio_dir_int <= wrdata_reg(4);
dds_gpior_pll_vcxo_reset_n_int <= wrdata_reg(5);
dds_gpior_pll_vcxo_cs_n_int <= wrdata_reg(6);
dds_gpior_pll_vcxo_function_int <= wrdata_reg(7);
dds_gpior_adf_ce_int <= wrdata_reg(9);
dds_gpior_adf_clk_int <= wrdata_reg(10);
dds_gpior_adf_le_int <= wrdata_reg(11);
dds_gpior_adf_data_int <= wrdata_reg(12);
dds_gpior_adc_sdi_int <= wrdata_reg(13);
dds_gpior_adc_cnv_int <= wrdata_reg(14);
dds_gpior_adc_sck_int <= wrdata_reg(15);
end if;
rddata_reg(0) <= dds_gpior_pll_sys_cs_n_int;
rddata_reg(1) <= dds_gpior_pll_sys_reset_n_int;
rddata_reg(2) <= dds_gpior_pll_sclk_int;
rddata_reg(3) <= regs_i.gpior_pll_sdio_i;
rddata_reg(4) <= dds_gpior_pll_sdio_dir_int;
rddata_reg(5) <= dds_gpior_pll_vcxo_reset_n_int;
rddata_reg(6) <= dds_gpior_pll_vcxo_cs_n_int;
rddata_reg(7) <= dds_gpior_pll_vcxo_function_int;
rddata_reg(8) <= regs_i.gpior_pll_vcxo_sdo_i;
rddata_reg(9) <= dds_gpior_adf_ce_int;
rddata_reg(10) <= dds_gpior_adf_clk_int;
rddata_reg(11) <= dds_gpior_adf_le_int;
rddata_reg(12) <= dds_gpior_adf_data_int;
rddata_reg(13) <= dds_gpior_adc_sdi_int;
rddata_reg(14) <= dds_gpior_adc_cnv_int;
rddata_reg(15) <= dds_gpior_adc_sck_int;
rddata_reg(16) <= regs_i.gpior_adc_sdo_i;
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
dds_freq_hi_int <= wrdata_reg(31 downto 0);
dds_freq_hi_swb <= '1';
dds_freq_hi_swb_delay <= '1';
end if;
rddata_reg(31 downto 0) <= dds_freq_hi_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
dds_freq_lo_int <= wrdata_reg(31 downto 0);
dds_freq_lo_swb <= '1';
dds_freq_lo_swb_delay <= '1';
end if;
rddata_reg(31 downto 0) <= dds_freq_lo_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
dds_gain_int <= wrdata_reg(15 downto 0);
dds_gain_swb <= '1';
dds_gain_swb_delay <= '1';
end if;
rddata_reg(15 downto 0) <= dds_gain_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0101" =>
if (wb_we_i = '1') then
dds_rstr_pll_rst_int <= wrdata_reg(0);
dds_rstr_sw_rst_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= dds_rstr_pll_rst_int;
rddata_reg(1) <= dds_rstr_sw_rst_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
if (wb_we_i = '1') then
dds_i2cr_scl_out_int <= wrdata_reg(0);
dds_i2cr_sda_out_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= dds_i2cr_scl_out_int;
rddata_reg(1) <= dds_i2cr_sda_out_int;
rddata_reg(2) <= regs_i.i2cr_scl_in_i;
rddata_reg(3) <= regs_i.i2cr_sda_in_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (wb_we_i = '1') then
dds_pir_kp_int <= wrdata_reg(15 downto 0);
dds_pir_ki_int <= wrdata_reg(31 downto 16);
end if;
rddata_reg(15 downto 0) <= dds_pir_kp_int;
rddata_reg(31 downto 16) <= dds_pir_ki_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
end if;
if (dds_pd_fifo_rdreq_int_d0 = '0') then
dds_pd_fifo_rdreq_int <= not dds_pd_fifo_rdreq_int;
else
rddata_reg(15 downto 0) <= dds_pd_fifo_out_int(15 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
when "1001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dds_pd_fifo_full_int;
rddata_reg(17) <= dds_pd_fifo_empty_int;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
if (wb_we_i = '1') then
dds_tune_fifo_in_int(31 downto 0) <= wrdata_reg(31 downto 0);
dds_tune_fifo_wrreq_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dds_tune_fifo_full_int;
rddata_reg(17) <= dds_tune_fifo_empty_int;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Enable DDS test mode
regs_o.cr_test_o <= dds_cr_test_int;
-- Enable DDS RF slave mode
regs_o.cr_slave_o <= dds_cr_slave_int;
-- Enable DDS RF master mode
regs_o.cr_master_o <= dds_cr_master_int;
-- ADC Bitbanged Access Enable
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dds_cr_adc_bb_enable_dly0 <= '0';
regs_o.cr_adc_bb_enable_o <= '0';
elsif rising_edge(clk_sys_i) then
dds_cr_adc_bb_enable_dly0 <= dds_cr_adc_bb_enable_int;
regs_o.cr_adc_bb_enable_o <= dds_cr_adc_bb_enable_int and (not dds_cr_adc_bb_enable_dly0);
end if;
end process;
-- Broadcast Clock ID
regs_o.cr_clk_id_o <= dds_cr_clk_id_int;
-- System PLL CS
regs_o.gpior_pll_sys_cs_n_o <= dds_gpior_pll_sys_cs_n_int;
-- System Reset
regs_o.gpior_pll_sys_reset_n_o <= dds_gpior_pll_sys_reset_n_int;
-- PLL SCLK (shared)
regs_o.gpior_pll_sclk_o <= dds_gpior_pll_sclk_int;
-- PLL SDIO (shared)
regs_o.gpior_pll_sdio_o <= wrdata_reg(3);
-- PLL SDIO direction (shared)
regs_o.gpior_pll_sdio_dir_o <= dds_gpior_pll_sdio_dir_int;
-- VCXO PLL Reset
regs_o.gpior_pll_vcxo_reset_n_o <= dds_gpior_pll_vcxo_reset_n_int;
-- VCXO PLL Chip Select
regs_o.gpior_pll_vcxo_cs_n_o <= dds_gpior_pll_vcxo_cs_n_int;
-- VCXO PLL Function
regs_o.gpior_pll_vcxo_function_o <= dds_gpior_pll_vcxo_function_int;
-- VCXO PLL SDO
-- ADF4002 Chip Enable
regs_o.gpior_adf_ce_o <= dds_gpior_adf_ce_int;
-- ADF4002 Clock
regs_o.gpior_adf_clk_o <= dds_gpior_adf_clk_int;
-- ADF4002 Latch Enable
regs_o.gpior_adf_le_o <= dds_gpior_adf_le_int;
-- ADF4002 Data
regs_o.gpior_adf_data_o <= dds_gpior_adf_data_int;
-- AD7980 Bitbanged Data Out
regs_o.gpior_adc_sdi_o <= dds_gpior_adc_sdi_int;
-- AD7980 Bitbanged Convert Strobe
regs_o.gpior_adc_cnv_o <= dds_gpior_adc_cnv_int;
-- AD7980 Bitbanged Serial Clock
regs_o.gpior_adc_sck_o <= dds_gpior_adc_sck_int;
-- AD7980 Bitbanged Data In
-- extra code for reg/fifo/mem: PD ADC Test FIFO (test mode)
dds_pd_fifo_in_int(15 downto 0) <= regs_i.pd_fifo_data_i;
dds_pd_fifo_rst_n <= rst_n_i;
dds_pd_fifo_INST : wbgen2_fifo_async
generic map (
g_size => 512,
g_width => 16,
g_usedw_size => 9
)
port map (
wr_req_i => regs_i.pd_fifo_wr_req_i,
wr_full_o => regs_o.pd_fifo_wr_full_o,
wr_empty_o => regs_o.pd_fifo_wr_empty_o,
rd_full_o => dds_pd_fifo_full_int,
rd_empty_o => dds_pd_fifo_empty_int,
rd_req_i => dds_pd_fifo_rdreq_int,
rst_n_i => dds_pd_fifo_rst_n,
wr_clk_i => clk_ref_i,
rd_clk_i => clk_sys_i,
wr_data_i => dds_pd_fifo_in_int,
rd_data_o => dds_pd_fifo_out_int
);
-- extra code for reg/fifo/mem: DDS Tuning FIFO (test mode)
regs_o.tune_fifo_data_o <= dds_tune_fifo_out_int(31 downto 0);
dds_tune_fifo_rst_n <= rst_n_i;
dds_tune_fifo_INST : wbgen2_fifo_async
generic map (
g_size => 512,
g_width => 32,
g_usedw_size => 9
)
port map (
rd_req_i => regs_i.tune_fifo_rd_req_i,
rd_empty_o => regs_o.tune_fifo_rd_empty_o,
wr_full_o => dds_tune_fifo_full_int,
wr_empty_o => dds_tune_fifo_empty_int,
wr_req_i => dds_tune_fifo_wrreq_int,
rst_n_i => dds_tune_fifo_rst_n,
rd_clk_i => clk_ref_i,
wr_clk_i => clk_sys_i,
wr_data_i => dds_tune_fifo_in_int,
rd_data_o => dds_tune_fifo_out_int
);
-- Center freq HI
-- asynchronous std_logic_vector register : Center freq HI (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
dds_freq_hi_swb_s0 <= '0';
dds_freq_hi_swb_s1 <= '0';
dds_freq_hi_swb_s2 <= '0';
regs_o.freq_hi_o <= "00000000000000000000000000000000";
elsif rising_edge(clk_ref_i) then
dds_freq_hi_swb_s0 <= dds_freq_hi_swb;
dds_freq_hi_swb_s1 <= dds_freq_hi_swb_s0;
dds_freq_hi_swb_s2 <= dds_freq_hi_swb_s1;
if ((dds_freq_hi_swb_s2 = '0') and (dds_freq_hi_swb_s1 = '1')) then
regs_o.freq_hi_o <= dds_freq_hi_int;
end if;
end if;
end process;
-- Center freq LO
-- asynchronous std_logic_vector register : Center freq LO (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
dds_freq_lo_swb_s0 <= '0';
dds_freq_lo_swb_s1 <= '0';
dds_freq_lo_swb_s2 <= '0';
regs_o.freq_lo_o <= "00000000000000000000000000000000";
elsif rising_edge(clk_ref_i) then
dds_freq_lo_swb_s0 <= dds_freq_lo_swb;
dds_freq_lo_swb_s1 <= dds_freq_lo_swb_s0;
dds_freq_lo_swb_s2 <= dds_freq_lo_swb_s1;
if ((dds_freq_lo_swb_s2 = '0') and (dds_freq_lo_swb_s1 = '1')) then
regs_o.freq_lo_o <= dds_freq_lo_int;
end if;
end if;
end process;
-- DDS gain (4.12 unsigned)
-- asynchronous std_logic_vector register : DDS gain (4.12 unsigned) (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
dds_gain_swb_s0 <= '0';
dds_gain_swb_s1 <= '0';
dds_gain_swb_s2 <= '0';
regs_o.gain_o <= "0000000000000000";
elsif rising_edge(clk_ref_i) then
dds_gain_swb_s0 <= dds_gain_swb;
dds_gain_swb_s1 <= dds_gain_swb_s0;
dds_gain_swb_s2 <= dds_gain_swb_s1;
if ((dds_gain_swb_s2 = '0') and (dds_gain_swb_s1 = '1')) then
regs_o.gain_o <= dds_gain_int;
end if;
end if;
end process;
-- FPGA REF/Serdes PLL Reset
regs_o.rstr_pll_rst_o <= dds_rstr_pll_rst_int;
-- FPGA DDS Logic software reset
regs_o.rstr_sw_rst_o <= dds_rstr_sw_rst_int;
-- SCL Line out
regs_o.i2cr_scl_out_o <= dds_i2cr_scl_out_int;
-- SDA Line out
regs_o.i2cr_sda_out_o <= dds_i2cr_sda_out_int;
-- SCL Line in
-- SDA Line in
-- KP
regs_o.pir_kp_o <= dds_pir_kp_int;
-- KI
regs_o.pir_ki_o <= dds_pir_ki_int;
-- extra code for reg/fifo/mem: FIFO 'PD ADC Test FIFO (test mode)' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dds_pd_fifo_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
dds_pd_fifo_rdreq_int_d0 <= dds_pd_fifo_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'DDS Tuning FIFO (test mode)' data input register 0
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
rtl/dds_wb_slave.wb 0 → 100644
View file @ 1bd30289
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "DDS RF distribution WB Slave";
hdl_entity = "dds_wb_slave";
prefix = "dds";
reg {
prefix = "CR";
name = "Control Register";
field {
name = "Enable DDS test mode";
prefix = "TEST";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Enable DDS RF slave mode";
prefix = "SLAVE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Enable DDS RF master mode";
prefix = "MASTER";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "ADC Bitbanged Access Enable";
prefix = "ADC_BB_ENABLE";
type = MONOSTABLE;
};
field {
name = "Broadcast Clock ID";
description = "Send/Receive clocks matching given ID";
prefix = "CLK_ID";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 16;
};
};
reg {
prefix = "GPIOR";
name = "GPIO register";
field {
name = "System PLL CS";
prefix = "PLL_SYS_CS_N";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "System Reset";
prefix = "PLL_SYS_RESET_N";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PLL SCLK (shared)";
prefix = "PLL_SCLK";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PLL SDIO (shared)";
prefix = "PLL_SDIO";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "PLL SDIO direction (shared)";
prefix = "PLL_SDIO_DIR";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "VCXO PLL Reset";
prefix = "PLL_VCXO_RESET_N";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "VCXO PLL Chip Select";
prefix = "PLL_VCXO_CS_N";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "VCXO PLL Function";
prefix = "PLL_VCXO_FUNCTION";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "VCXO PLL SDO";
prefix = "PLL_VCXO_SDO";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "ADF4002 Chip Enable";
prefix = "ADF_CE";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "ADF4002 Clock";
prefix = "ADF_CLK";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "ADF4002 Latch Enable";
prefix = "ADF_LE";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "ADF4002 Data";
prefix = "ADF_DATA";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "AD7980 Bitbanged Data Out";
prefix = "ADC_SDI";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "AD7980 Bitbanged Convert Strobe";
prefix = "ADC_CNV";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "AD7980 Bitbanged Serial Clock";
prefix = "ADC_SCK";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "AD7980 Bitbanged Data In";
prefix = "ADC_SDO";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
fifo_reg {
name = "PD ADC Test FIFO (test mode)";
prefix = "PD_FIFO";
size = 512;
direction = CORE_TO_BUS;
clock = "clk_ref_i";
flags_bus = { FIFO_EMPTY, FIFO_FULL };
flags_dev = { FIFO_EMPTY, FIFO_FULL };
field {
name = "ADC data";
prefix = "DATA";
size = 16;
type = SLV;
};
};
fifo_reg {
name = "DDS Tuning FIFO (test mode)";
prefix = "TUNE_FIFO";
size = 512;
flags_bus = { FIFO_EMPTY, FIFO_FULL };
flags_dev = { FIFO_EMPTY };
direction = BUS_TO_CORE;
clock = "clk_ref_i";
field {
name = "DDS tune word";
prefix = "DATA";
size = 32;
type = SLV;
};
};
reg {
name = "DDS Center frequency hi";
prefix = "FREQ_HI";
field {
name = "Center freq HI";
size = 32;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DDS Center frequency lo";
prefix = "FREQ_LO";
field {
name = "Center freq LO";
size = 32;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DDS Gain";
prefix = "GAIN";
field {
name = "DDS gain (4.12 unsigned)";
size = 16;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Reset Register";
prefix = "RSTR";
field {
name = "FPGA REF/Serdes PLL Reset";
prefix = "PLL_RST";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "FPGA DDS Logic software reset";
prefix = "SW_RST";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "I2C bitbanged IO register";
prefix = "I2CR";
field {
name = "SCL Line out";
prefix = "SCL_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SDA Line out";
prefix = "SDA_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SCL Line in";
prefix = "SCL_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SDA Line in";
prefix = "SDA_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "PI register";
prefix = "PIR";
field {
name = "KP";
prefix = "KP";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 16;
};
field {
name = "KI";
prefix = "KI";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 16;
};
};
};
\ No newline at end of file
rtl/dds_wbgen2_pkg.vhd 0 → 100644
View file @ 1bd30289
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for DDS RF distribution WB Slave
---------------------------------------------------------------------------------------
-- File : dds_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from dds_wb_slave.wb
-- Created : Fri May 10 01:11:43 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dds_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
package dds_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_dds_in_registers is record
gpior_pll_sdio_i : std_logic;
gpior_pll_vcxo_sdo_i : std_logic;
gpior_adc_sdo_i : std_logic;
pd_fifo_wr_req_i : std_logic;
pd_fifo_data_i : std_logic_vector(15 downto 0);
tune_fifo_rd_req_i : std_logic;
i2cr_scl_in_i : std_logic;
i2cr_sda_in_i : std_logic;
end record;
constant c_dds_in_registers_init_value: t_dds_in_registers := (
gpior_pll_sdio_i => '0',
gpior_pll_vcxo_sdo_i => '0',
gpior_adc_sdo_i => '0',
pd_fifo_wr_req_i => '0',
pd_fifo_data_i => (others => '0'),
tune_fifo_rd_req_i => '0',
i2cr_scl_in_i => '0',
i2cr_sda_in_i => '0'
);
-- Output registers (WB slave -> user design)
type t_dds_out_registers is record
cr_test_o : std_logic;
cr_slave_o : std_logic;
cr_master_o : std_logic;
cr_adc_bb_enable_o : std_logic;
cr_clk_id_o : std_logic_vector(15 downto 0);
gpior_pll_sys_cs_n_o : std_logic;
gpior_pll_sys_reset_n_o : std_logic;
gpior_pll_sclk_o : std_logic;
gpior_pll_sdio_o : std_logic;
gpior_pll_sdio_load_o : std_logic;
gpior_pll_sdio_dir_o : std_logic;
gpior_pll_vcxo_reset_n_o : std_logic;
gpior_pll_vcxo_cs_n_o : std_logic;
gpior_pll_vcxo_function_o : std_logic;
gpior_adf_ce_o : std_logic;
gpior_adf_clk_o : std_logic;
gpior_adf_le_o : std_logic;
gpior_adf_data_o : std_logic;
gpior_adc_sdi_o : std_logic;
gpior_adc_cnv_o : std_logic;
gpior_adc_sck_o : std_logic;
pd_fifo_wr_full_o : std_logic;
pd_fifo_wr_empty_o : std_logic;
tune_fifo_rd_empty_o : std_logic;
tune_fifo_data_o : std_logic_vector(31 downto 0);
freq_hi_o : std_logic_vector(31 downto 0);
freq_lo_o : std_logic_vector(31 downto 0);
gain_o : std_logic_vector(15 downto 0);
rstr_pll_rst_o : std_logic;
rstr_sw_rst_o : std_logic;
i2cr_scl_out_o : std_logic;
i2cr_sda_out_o : std_logic;
pir_kp_o : std_logic_vector(15 downto 0);
pir_ki_o : std_logic_vector(15 downto 0);
end record;
constant c_dds_out_registers_init_value: t_dds_out_registers := (
cr_test_o => '0',
cr_slave_o => '0',
cr_master_o => '0',
cr_adc_bb_enable_o => '0',
cr_clk_id_o => (others => '0'),
gpior_pll_sys_cs_n_o => '0',
gpior_pll_sys_reset_n_o => '0',
gpior_pll_sclk_o => '0',
gpior_pll_sdio_o => '0',
gpior_pll_sdio_load_o => '0',
gpior_pll_sdio_dir_o => '0',
gpior_pll_vcxo_reset_n_o => '0',
gpior_pll_vcxo_cs_n_o => '0',
gpior_pll_vcxo_function_o => '0',
gpior_adf_ce_o => '0',
gpior_adf_clk_o => '0',
gpior_adf_le_o => '0',
gpior_adf_data_o => '0',
gpior_adc_sdi_o => '0',
gpior_adc_cnv_o => '0',
gpior_adc_sck_o => '0',
pd_fifo_wr_full_o => '0',
pd_fifo_wr_empty_o => '0',
tune_fifo_rd_empty_o => '0',
tune_fifo_data_o => (others => '0'),
freq_hi_o => (others => '0'),
freq_lo_o => (others => '0'),
gain_o => (others => '0'),
rstr_pll_rst_o => '0',
rstr_sw_rst_o => '0',
i2cr_scl_out_o => '0',
i2cr_sda_out_o => '0',
pir_kp_o => (others => '0'),
pir_ki_o => (others => '0')
);
function "or" (left, right: t_dds_in_registers) return t_dds_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body dds_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_dds_in_registers) return t_dds_in_registers is
variable tmp: t_dds_in_registers;
begin
tmp.gpior_pll_sdio_i := f_x_to_zero(left.gpior_pll_sdio_i) or f_x_to_zero(right.gpior_pll_sdio_i);
tmp.gpior_pll_vcxo_sdo_i := f_x_to_zero(left.gpior_pll_vcxo_sdo_i) or f_x_to_zero(right.gpior_pll_vcxo_sdo_i);
tmp.gpior_adc_sdo_i := f_x_to_zero(left.gpior_adc_sdo_i) or f_x_to_zero(right.gpior_adc_sdo_i);
tmp.pd_fifo_wr_req_i := f_x_to_zero(left.pd_fifo_wr_req_i) or f_x_to_zero(right.pd_fifo_wr_req_i);
tmp.pd_fifo_data_i := f_x_to_zero(left.pd_fifo_data_i) or f_x_to_zero(right.pd_fifo_data_i);
tmp.tune_fifo_rd_req_i := f_x_to_zero(left.tune_fifo_rd_req_i) or f_x_to_zero(right.tune_fifo_rd_req_i);
tmp.i2cr_scl_in_i := f_x_to_zero(left.i2cr_scl_in_i) or f_x_to_zero(right.i2cr_scl_in_i);
tmp.i2cr_sda_in_i := f_x_to_zero(left.i2cr_sda_in_i) or f_x_to_zero(right.i2cr_sda_in_i);
return tmp;
end function;
end package body;
rtl/lut_init.v 0 → 100644
View file @ 1bd30289
`define INIT_LUT(name) \
lut``name[0]=36'h30b1c0000; \
lut``name[1]=36'h30b180185; \
lut``name[2]=36'h30b14030b; \
lut``name[3]=36'h30b100490; \
lut``name[4]=36'h30b080616; \
lut``name[5]=36'h30b00079b; \
lut``name[6]=36'h30af40921; \
lut``name[7]=36'h30ae80aa6; \
lut``name[8]=36'h30ad80c2c; \
lut``name[9]=36'h30ac80db1; \
lut``name[10]=36'h30ab40f36; \
lut``name[11]=36'h30aa010bc; \
lut``name[12]=36'h30a881241; \
lut``name[13]=36'h30a7013c6; \
lut``name[14]=36'h30a58154c; \
lut``name[15]=36'h30a3816d1; \
lut``name[16]=36'h30a1c1856; \
lut``name[17]=36'h309fc19db; \
lut``name[18]=36'h309dc1b60; \
lut``name[19]=36'h309b81ce5; \
lut``name[20]=36'h309901e6a; \
lut``name[21]=36'h309681fef; \
lut``name[22]=36'h309402173; \
lut``name[23]=36'h3091422f8; \
lut``name[24]=36'h308e8247c; \
lut``name[25]=36'h308b82601; \
lut``name[26]=36'h308882785; \
lut``name[27]=36'h30854290a; \
lut``name[28]=36'h308202a8e; \
lut``name[29]=36'h307ec2c12; \
lut``name[30]=36'h307b42d96; \
lut``name[31]=36'h307782f1a; \
lut``name[32]=36'h3073c309d; \
lut``name[33]=36'h307003221; \
lut``name[34]=36'h306c033a4; \
lut``name[35]=36'h3067c3528; \
lut``name[36]=36'h3063c36ab; \
lut``name[37]=36'h305f4382e; \
lut``name[38]=36'h305ac39b1; \
lut``name[39]=36'h305643b34; \
lut``name[40]=36'h305183cb7; \
lut``name[41]=36'h304cc3e39; \
lut``name[42]=36'h304803fbc; \
lut``name[43]=36'h3042c413e; \
lut``name[44]=36'h303dc42c0; \
lut``name[45]=36'h303884442; \
lut``name[46]=36'h3033045c4; \
lut``name[47]=36'h302d84745; \
lut``name[48]=36'h3028048c7; \
lut``name[49]=36'h302244a48; \
lut``name[50]=36'h301c84bc9; \
lut``name[51]=36'h301684d4a; \
lut``name[52]=36'h301044ecb; \
lut``name[53]=36'h300a4504b; \
lut``name[54]=36'h3003c51cc; \
lut``name[55]=36'h2ffd8534c; \
lut``name[56]=36'h2ff7054cc; \
lut``name[57]=36'h2ff04564b; \
lut``name[58]=36'h2fe9857cb; \
lut``name[59]=36'h2fe28594a; \
lut``name[60]=36'h2fdb85ac9; \
lut``name[61]=36'h2fd485c48; \
lut``name[62]=36'h2fcd45dc7; \
lut``name[63]=36'h2fc605f45; \
lut``name[64]=36'h2fbe860c3; \
lut``name[65]=36'h2fb6c6241; \
lut``name[66]=36'h2faf463bf; \
lut``name[67]=36'h2fa74653c; \
lut``name[68]=36'h2f9f866ba; \
lut``name[69]=36'h2f9786837; \
lut``name[70]=36'h2f8f469b3; \
lut``name[71]=36'h2f8706b30; \
lut``name[72]=36'h2f7e86cac; \
lut``name[73]=36'h2f7606e28; \
lut``name[74]=36'h2f6d86fa4; \
lut``name[75]=36'h2f64c711f; \
lut``name[76]=36'h2f5c0729a; \
lut``name[77]=36'h2f5307415; \
lut``name[78]=36'h2f4a07590; \
lut``name[79]=36'h2f40c770a; \
lut``name[80]=36'h2f3787884; \
lut``name[81]=36'h2f2e079fe; \
lut``name[82]=36'h2f2487b77; \
lut``name[83]=36'h2f1b07cf0; \
lut``name[84]=36'h2f1147e69; \
lut``name[85]=36'h2f0747fe2; \
lut``name[86]=36'h2efd4815a; \
lut``name[87]=36'h2ef3482d2; \
lut``name[88]=36'h2ee90844a; \
lut``name[89]=36'h2edec85c1; \
lut``name[90]=36'h2ed448738; \
lut``name[91]=36'h2ec9c88af; \
lut``name[92]=36'h2ebf08a25; \
lut``name[93]=36'h2eb448b9b; \
lut``name[94]=36'h2ea988d10; \
lut``name[95]=36'h2e9e88e86; \
lut``name[96]=36'h2e9348ffb; \
lut``name[97]=36'h2e884916f; \
lut``name[98]=36'h2e7cc92e4; \
lut``name[99]=36'h2e7189457; \
lut``name[100]=36'h2e65c95cb; \
lut``name[101]=36'h2e5a4973e; \
lut``name[102]=36'h2e4e898b1; \
lut``name[103]=36'h2e4289a23; \
lut``name[104]=36'h2e3689b96; \
lut``name[105]=36'h2e2a89d07; \
lut``name[106]=36'h2e1e49e79; \
lut``name[107]=36'h2e11c9fea; \
lut``name[108]=36'h2e058a15a; \
lut``name[109]=36'h2df8ca2ca; \
lut``name[110]=36'h2dec4a43a; \
lut``name[111]=36'h2ddf8a5a9; \
lut``name[112]=36'h2dd28a718; \
lut``name[113]=36'h2dc58a887; \
lut``name[114]=36'h2db88a9f5; \
lut``name[115]=36'h2dab4ab63; \
lut``name[116]=36'h2d9e0acd0; \
lut``name[117]=36'h2d908ae3d; \
lut``name[118]=36'h2d830afaa; \
lut``name[119]=36'h2d754b116; \
lut``name[120]=36'h2d678b282; \
lut``name[121]=36'h2d59cb3ed; \
lut``name[122]=36'h2d4bcb558; \
lut``name[123]=36'h2d3d8b6c2; \
lut``name[124]=36'h2d2f4b82c; \
lut``name[125]=36'h2d210b995; \
lut``name[126]=36'h2d12cbafe; \
lut``name[127]=36'h2d040bc67; \
lut``name[128]=36'h2cf58bdcf; \
lut``name[129]=36'h2ce6cbf37; \
lut``name[130]=36'h2cd80c09e; \
lut``name[131]=36'h2cc90c205; \
lut``name[132]=36'h2cb9cc36b; \
lut``name[133]=36'h2caacc4d1; \
lut``name[134]=36'h2c9b8c636; \
lut``name[135]=36'h2c8c0c79b; \
lut``name[136]=36'h2c7c8c8ff; \
lut``name[137]=36'h2c6d0ca63; \
lut``name[138]=36'h2c5d4cbc7; \
lut``name[139]=36'h2c4d4cd2a; \
lut``name[140]=36'h2c3d8ce8c; \
lut``name[141]=36'h2c2d8cfee; \
lut``name[142]=36'h2c1d4d14f; \
lut``name[143]=36'h2c0d0d2b0; \
lut``name[144]=36'h2bfccd411; \
lut``name[145]=36'h2bec4d571; \
lut``name[146]=36'h2bdbcd6d0; \
lut``name[147]=36'h2bcb0d82f; \
lut``name[148]=36'h2bba4d98d; \
lut``name[149]=36'h2ba94daeb; \
lut``name[150]=36'h2b984dc48; \
lut``name[151]=36'h2b874dda5; \
lut``name[152]=36'h2b760df01; \
lut``name[153]=36'h2b64ce05d; \
lut``name[154]=36'h2b534e1b8; \
lut``name[155]=36'h2b41ce313; \
lut``name[156]=36'h2b304e46d; \
lut``name[157]=36'h2b1e8e5c6; \
lut``name[158]=36'h2b0cce71f; \
lut``name[159]=36'h2aface878; \
lut``name[160]=36'h2ae8ce9d0; \
lut``name[161]=36'h2ad68eb27; \
lut``name[162]=36'h2ac44ec7e; \
lut``name[163]=36'h2ab20edd4; \
lut``name[164]=36'h2a9f8ef29; \
lut``name[165]=36'h2a8d0f07e; \
lut``name[166]=36'h2a7a8f1d3; \
lut``name[167]=36'h2a67cf326; \
lut``name[168]=36'h2a54cf47a; \
lut``name[169]=36'h2a41cf5cc; \
lut``name[170]=36'h2a2ecf71e; \
lut``name[171]=36'h2a1bcf870; \
lut``name[172]=36'h2a088f9c1; \
lut``name[173]=36'h29f50fb11; \
lut``name[174]=36'h29e18fc61; \
lut``name[175]=36'h29ce0fdb0; \
lut``name[176]=36'h29ba4fefe; \
lut``name[177]=36'h29a69004c; \
lut``name[178]=36'h2992d0199; \
lut``name[179]=36'h297ed02e6; \
lut``name[180]=36'h296ad0432; \
lut``name[181]=36'h29569057d; \
lut``name[182]=36'h2942506c8; \
lut``name[183]=36'h292e10812; \
lut``name[184]=36'h29199095b; \
lut``name[185]=36'h290510aa4; \
lut``name[186]=36'h28f050bec; \
lut``name[187]=36'h28db90d34; \
lut``name[188]=36'h28c690e7b; \
lut``name[189]=36'h28b1d0fc1; \
lut``name[190]=36'h289c91106; \
lut``name[191]=36'h28879124b; \
lut``name[192]=36'h287251390; \
lut``name[193]=36'h285cd14d3; \
lut``name[194]=36'h284791616; \
lut``name[195]=36'h283211758; \
lut``name[196]=36'h281c5189a; \
lut``name[197]=36'h2806919db; \
lut``name[198]=36'h27f0d1b1b; \
lut``name[199]=36'h27dad1c5a; \
lut``name[200]=36'h27c4d1d99; \
lut``name[201]=36'h27ae91ed7; \
lut``name[202]=36'h279892015; \
lut``name[203]=36'h278212152; \
lut``name[204]=36'h276bd228e; \
lut``name[205]=36'h2755523c9; \
lut``name[206]=36'h273e92504; \
lut``name[207]=36'h27281263e; \
lut``name[208]=36'h271112777; \
lut``name[209]=36'h26fa528b0; \
lut``name[210]=36'h26e3529e7; \
lut``name[211]=36'h26cc52b1e; \
lut``name[212]=36'h26b512c55; \
lut``name[213]=36'h269dd2d8b; \
lut``name[214]=36'h268692ebf; \
lut``name[215]=36'h266f12ff4; \
lut``name[216]=36'h265793127; \
lut``name[217]=36'h263fd325a; \
lut``name[218]=36'h26285338c; \
lut``name[219]=36'h2610534bd; \
lut``name[220]=36'h25f8935ee; \
lut``name[221]=36'h25e09371d; \
lut``name[222]=36'h25c89384c; \
lut``name[223]=36'h25b05397b; \
lut``name[224]=36'h259813aa8; \
lut``name[225]=36'h257f93bd5; \
lut``name[226]=36'h256753d01; \
lut``name[227]=36'h254e93e2c; \
lut``name[228]=36'h253613f57; \
lut``name[229]=36'h251d54080; \
lut``name[230]=36'h2504941a9; \
lut``name[231]=36'h24eb942d1; \
lut``name[232]=36'h24d2943f9; \
lut``name[233]=36'h24b99451f; \
lut``name[234]=36'h24a094645; \
lut``name[235]=36'h24875476a; \
lut``name[236]=36'h246dd488e; \
lut``name[237]=36'h2454949b2; \
lut``name[238]=36'h243b14ad4; \
lut``name[239]=36'h242154bf6; \
lut``name[240]=36'h240794d17; \
lut``name[241]=36'h23edd4e38; \
lut``name[242]=36'h23d414f57; \
lut``name[243]=36'h23ba15076; \
lut``name[244]=36'h23a015193; \
lut``name[245]=36'h2386152b0; \
lut``name[246]=36'h236bd53cd; \
lut``name[247]=36'h2351954e8; \
lut``name[248]=36'h233715603; \
lut``name[249]=36'h231c9571c; \
lut``name[250]=36'h230215835; \
lut``name[251]=36'h22e79594d; \
lut``name[252]=36'h22ccd5a65; \
lut``name[253]=36'h22b215b7b; \
lut``name[254]=36'h229715c90; \
lut``name[255]=36'h227c15da5; \
lut``name[256]=36'h226115eb9; \
lut``name[257]=36'h224615fcc; \
lut``name[258]=36'h222ad60de; \
lut``name[259]=36'h220f961f0; \
lut``name[260]=36'h21f416300; \
lut``name[261]=36'h21d896410; \
lut``name[262]=36'h21bd1651f; \
lut``name[263]=36'h21a19662c; \
lut``name[264]=36'h2185d6739; \
lut``name[265]=36'h216a16846; \
lut``name[266]=36'h214e16951; \
lut``name[267]=36'h213256a5b; \
lut``name[268]=36'h211616b65; \
lut``name[269]=36'h20fa16c6e; \
lut``name[270]=36'h20ddd6d76; \
lut``name[271]=36'h20c196e7c; \
lut``name[272]=36'h20a556f83; \
lut``name[273]=36'h2088d7088; \
lut``name[274]=36'h206c5718c; \
lut``name[275]=36'h204fd728f; \
lut``name[276]=36'h203317392; \
lut``name[277]=36'h201697493; \
lut``name[278]=36'h1ff997594; \
lut``name[279]=36'h1fdcd7694; \
lut``name[280]=36'h1fbfd7793; \
lut``name[281]=36'h1fa2d7891; \
lut``name[282]=36'h1f859798e; \
lut``name[283]=36'h1f6897a8a; \
lut``name[284]=36'h1f4b57b85; \
lut``name[285]=36'h1f2dd7c80; \
lut``name[286]=36'h1f1097d79; \
lut``name[287]=36'h1ef317e72; \
lut``name[288]=36'h1ed557f69; \
lut``name[289]=36'h1eb7d8060; \
lut``name[290]=36'h1e9a18156; \
lut``name[291]=36'h1e7c5824b; \
lut``name[292]=36'h1e5e5833e; \
lut``name[293]=36'h1e4098431; \
lut``name[294]=36'h1e2298523; \
lut``name[295]=36'h1e0458614; \
lut``name[296]=36'h1de658705; \
lut``name[297]=36'h1dc8187f4; \
lut``name[298]=36'h1da9d88e2; \
lut``name[299]=36'h1d8b589cf; \
lut``name[300]=36'h1d6cd8abc; \
lut``name[301]=36'h1d4e58ba7; \
lut``name[302]=36'h1d2fd8c92; \
lut``name[303]=36'h1d1118d7b; \
lut``name[304]=36'h1cf298e64; \
lut``name[305]=36'h1cd398f4b; \
lut``name[306]=36'h1cb4d9032; \
lut``name[307]=36'h1c95d9117; \
lut``name[308]=36'h1c76d91fc; \
lut``name[309]=36'h1c57d92e0; \
lut``name[310]=36'h1c38d93c3; \
lut``name[311]=36'h1c19994a4; \
lut``name[312]=36'h1bfa59585; \
lut``name[313]=36'h1bdad9665; \
lut``name[314]=36'h1bbb99744; \
lut``name[315]=36'h1b9c19822; \
lut``name[316]=36'h1b7c998ff; \
lut``name[317]=36'h1b5cd99da; \
lut``name[318]=36'h1b3d59ab5; \
lut``name[319]=36'h1b1d99b8f; \
lut``name[320]=36'h1afd99c68; \
lut``name[321]=36'h1addd9d40; \
lut``name[322]=36'h1abdd9e17; \
lut``name[323]=36'h1a9dd9eed; \
lut``name[324]=36'h1a7dd9fc2; \
lut``name[325]=36'h1a5dda096; \
lut``name[326]=36'h1a3d9a169; \
lut``name[327]=36'h1a1d5a23b; \
lut``name[328]=36'h19fd1a30c; \
lut``name[329]=36'h19dc9a3dc; \
lut``name[330]=36'h19bc1a4aa; \
lut``name[331]=36'h199b9a578; \
lut``name[332]=36'h197b1a645; \
lut``name[333]=36'h195a9a711; \
lut``name[334]=36'h1939da7dc; \
lut``name[335]=36'h19191a8a6; \
lut``name[336]=36'h18f85a96e; \
lut``name[337]=36'h18d75aa36; \
lut``name[338]=36'h18b69aafd; \
lut``name[339]=36'h18959abc3; \
lut``name[340]=36'h18745ac87; \
lut``name[341]=36'h18535ad4b; \
lut``name[342]=36'h18321ae0e; \
lut``name[343]=36'h18111aecf; \
lut``name[344]=36'h17ef9af90; \
lut``name[345]=36'h17ce5b04f; \
lut``name[346]=36'h17ad1b10e; \
lut``name[347]=36'h178b9b1cb; \
lut``name[348]=36'h176a1b287; \
lut``name[349]=36'h17489b343; \
lut``name[350]=36'h1726db3fd; \
lut``name[351]=36'h17051b4b6; \
lut``name[352]=36'h16e35b56e; \
lut``name[353]=36'h16c19b625; \
lut``name[354]=36'h169fdb6db; \
lut``name[355]=36'h167ddb790; \
lut``name[356]=36'h165c1b844; \
lut``name[357]=36'h163a1b8f7; \
lut``name[358]=36'h1617db9a9; \
lut``name[359]=36'h15f5dba5a; \
lut``name[360]=36'h15d39bb0a; \
lut``name[361]=36'h15b15bbb8; \
lut``name[362]=36'h158f1bc66; \
lut``name[363]=36'h156cdbd12; \
lut``name[364]=36'h154a9bdbe; \
lut``name[365]=36'h15281be68; \
lut``name[366]=36'h15059bf11; \
lut``name[367]=36'h14e31bfb9; \
lut``name[368]=36'h14c09c060; \
lut``name[369]=36'h149ddc106; \
lut``name[370]=36'h147b1c1ab; \
lut``name[371]=36'h14589c24f; \
lut``name[372]=36'h1435dc2f2; \
lut``name[373]=36'h1412dc394; \
lut``name[374]=36'h13f01c434; \
lut``name[375]=36'h13cd1c4d4; \
lut``name[376]=36'h13aa1c572; \
lut``name[377]=36'h13871c610; \
lut``name[378]=36'h13641c6ac; \
lut``name[379]=36'h13411c747; \
lut``name[380]=36'h131ddc7e1; \
lut``name[381]=36'h12fa9c87a; \
lut``name[382]=36'h12d75c912; \
lut``name[383]=36'h12b41c9a8; \
lut``name[384]=36'h1290dca3e; \
lut``name[385]=36'h126d5cad3; \
lut``name[386]=36'h1249dcb66; \
lut``name[387]=36'h12269cbf8; \
lut``name[388]=36'h12031cc89; \
lut``name[389]=36'h11df5cd1a; \
lut``name[390]=36'h11bbdcda9; \
lut``name[391]=36'h11981ce36; \
lut``name[392]=36'h11749cec3; \
lut``name[393]=36'h1150dcf4f; \
lut``name[394]=36'h112d1cfd9; \
lut``name[395]=36'h11091d063; \
lut``name[396]=36'h10e55d0eb; \
lut``name[397]=36'h10c19d172; \
lut``name[398]=36'h109d9d1f8; \
lut``name[399]=36'h10799d27d; \
lut``name[400]=36'h10559d301; \
lut``name[401]=36'h10319d384; \
lut``name[402]=36'h100d5d405; \
lut``name[403]=36'hfe95d486; \
lut``name[404]=36'hfc51d505; \
lut``name[405]=36'hfa0dd583; \
lut``name[406]=36'hf7c9d600; \
lut``name[407]=36'hf585d67c; \
lut``name[408]=36'hf341d6f7; \
lut``name[409]=36'hf0fdd770; \
lut``name[410]=36'heeb5d7e9; \
lut``name[411]=36'hec6dd860; \
lut``name[412]=36'hea29d8d6; \
lut``name[413]=36'he7e1d94c; \
lut``name[414]=36'he595d9c0; \
lut``name[415]=36'he34dda32; \
lut``name[416]=36'he105daa4; \
lut``name[417]=36'hdeb9db14; \
lut``name[418]=36'hdc71db84; \
lut``name[419]=36'hda25dbf2; \
lut``name[420]=36'hd7d9dc5f; \
lut``name[421]=36'hd58ddccb; \
lut``name[422]=36'hd341dd36; \
lut``name[423]=36'hd0f1dd9f; \
lut``name[424]=36'hcea5de08; \
lut``name[425]=36'hcc55de6f; \
lut``name[426]=36'hca09ded5; \
lut``name[427]=36'hc7b9df3a; \
lut``name[428]=36'hc569df9e; \
lut``name[429]=36'hc319e001; \
lut``name[430]=36'hc0c9e063; \
lut``name[431]=36'hbe75e0c3; \
lut``name[432]=36'hbc25e122; \
lut``name[433]=36'hb9d5e180; \
lut``name[434]=36'hb781e1dd; \
lut``name[435]=36'hb52de239; \
lut``name[436]=36'hb2d9e294; \
lut``name[437]=36'hb085e2ed; \
lut``name[438]=36'hae31e345; \
lut``name[439]=36'habdde39c; \
lut``name[440]=36'ha989e3f2; \
lut``name[441]=36'ha735e447; \
lut``name[442]=36'ha4dde49b; \
lut``name[443]=36'ha289e4ed; \
lut``name[444]=36'ha031e53e; \
lut``name[445]=36'h9dd9e58e; \
lut``name[446]=36'h9b81e5dd; \
lut``name[447]=36'h9929e62b; \
lut``name[448]=36'h96d1e678; \
lut``name[449]=36'h9479e6c3; \
lut``name[450]=36'h9221e70d; \
lut``name[451]=36'h8fc9e756; \
lut``name[452]=36'h8d6de79e; \
lut``name[453]=36'h8b15e7e5; \
lut``name[454]=36'h88b9e82b; \
lut``name[455]=36'h8661e86f; \
lut``name[456]=36'h8405e8b2; \
lut``name[457]=36'h81a9e8f4; \
lut``name[458]=36'h7f4de935; \
lut``name[459]=36'h7cf1e975; \
lut``name[460]=36'h7a95e9b3; \
lut``name[461]=36'h7839e9f0; \
lut``name[462]=36'h75ddea2c; \
lut``name[463]=36'h7381ea67; \
lut``name[464]=36'h7121eaa1; \
lut``name[465]=36'h6ec5eada; \
lut``name[466]=36'h6c65eb11; \
lut``name[467]=36'h6a09eb47; \
lut``name[468]=36'h67a9eb7c; \
lut``name[469]=36'h654debb0; \
lut``name[470]=36'h62edebe3; \
lut``name[471]=36'h608dec14; \
lut``name[472]=36'h5e2dec45; \
lut``name[473]=36'h5bcdec74; \
lut``name[474]=36'h5971eca2; \
lut``name[475]=36'h5711ecce; \
lut``name[476]=36'h54b1ecfa; \
lut``name[477]=36'h524ded24; \
lut``name[478]=36'h4feded4d; \
lut``name[479]=36'h4d8ded75; \
lut``name[480]=36'h4b2ded9c; \
lut``name[481]=36'h48cdedc2; \
lut``name[482]=36'h4669ede6; \
lut``name[483]=36'h4409ee09; \
lut``name[484]=36'h41a5ee2b; \
lut``name[485]=36'h3f45ee4c; \
lut``name[486]=36'h3ce1ee6c; \
lut``name[487]=36'h3a81ee8a; \
lut``name[488]=36'h381deea7; \
lut``name[489]=36'h35bdeec4; \
lut``name[490]=36'h3359eede; \
lut``name[491]=36'h30f5eef8; \
lut``name[492]=36'h2e95ef11; \
lut``name[493]=36'h2c31ef28; \
lut``name[494]=36'h29cdef3e; \
lut``name[495]=36'h276def53; \
lut``name[496]=36'h2509ef67; \
lut``name[497]=36'h22a5ef79; \
lut``name[498]=36'h2041ef8a; \
lut``name[499]=36'h1dddef9b; \
lut``name[500]=36'h1b79efa9; \
lut``name[501]=36'h1915efb7; \
lut``name[502]=36'h16b5efc4; \
lut``name[503]=36'h1451efcf; \
lut``name[504]=36'h11edefd9; \
lut``name[505]=36'hf89efe2; \
lut``name[506]=36'hd25efea; \
lut``name[507]=36'hac1eff1; \
lut``name[508]=36'h85deff6; \
lut``name[509]=36'h5f9effa; \
lut``name[510]=36'h395effd; \
lut``name[511]=36'h131efff; \
lut``name[512]=36'hffed1f000; \
lut``name[513]=36'hffc6defff; \
lut``name[514]=36'hffa09effd; \
lut``name[515]=36'hff7a5effa; \
lut``name[516]=36'hff541eff6; \
lut``name[517]=36'hff2ddeff1; \
lut``name[518]=36'hff079efea; \
lut``name[519]=36'hfee15efe2; \
lut``name[520]=36'hfebb1efd9; \
lut``name[521]=36'hfe94defcf; \
lut``name[522]=36'hfe6edefc4; \
lut``name[523]=36'hfe489efb7; \
lut``name[524]=36'hfe225efa9; \
lut``name[525]=36'hfdfc1ef9b; \
lut``name[526]=36'hfdd5def8a; \
lut``name[527]=36'hfdaf9ef79; \
lut``name[528]=36'hfd895ef67; \
lut``name[529]=36'hfd635ef53; \
lut``name[530]=36'hfd3d1ef3e; \
lut``name[531]=36'hfd16def28; \
lut``name[532]=36'hfcf0def11; \
lut``name[533]=36'hfcca9eef8; \
lut``name[534]=36'hfca45eede; \
lut``name[535]=36'hfc7e5eec4; \
lut``name[536]=36'hfc581eea7; \
lut``name[537]=36'hfc321ee8a; \
lut``name[538]=36'hfc0bdee6c; \
lut``name[539]=36'hfbe5dee4c; \
lut``name[540]=36'hfbbf9ee2b; \
lut``name[541]=36'hfb999ee09; \
lut``name[542]=36'hfb735ede6; \
lut``name[543]=36'hfb4d5edc2; \
lut``name[544]=36'hfb275ed9c; \
lut``name[545]=36'hfb015ed75; \
lut``name[546]=36'hfadb5ed4d; \
lut``name[547]=36'hfab51ed24; \
lut``name[548]=36'hfa8f1ecfa; \
lut``name[549]=36'hfa691ecce; \
lut``name[550]=36'hfa435eca2; \
lut``name[551]=36'hfa1d5ec74; \
lut``name[552]=36'hf9f75ec45; \
lut``name[553]=36'hf9d15ec14; \
lut``name[554]=36'hf9ab5ebe3; \
lut``name[555]=36'hf9859ebb0; \
lut``name[556]=36'hf95f9eb7c; \
lut``name[557]=36'hf939deb47; \
lut``name[558]=36'hf913deb11; \
lut``name[559]=36'hf8ee1eada; \
lut``name[560]=36'hf8c81eaa1; \
lut``name[561]=36'hf8a25ea67; \
lut``name[562]=36'hf87c9ea2c; \
lut``name[563]=36'hf856de9f0; \
lut``name[564]=36'hf8311e9b3; \
lut``name[565]=36'hf80b5e975; \
lut``name[566]=36'hf7e59e935; \
lut``name[567]=36'hf7bfde8f4; \
lut``name[568]=36'hf79a1e8b2; \
lut``name[569]=36'hf7749e86f; \
lut``name[570]=36'hf74ede82b; \
lut``name[571]=36'hf7295e7e5; \
lut``name[572]=36'hf7039e79e; \
lut``name[573]=36'hf6de1e756; \
lut``name[574]=36'hf6b89e70d; \
lut``name[575]=36'hf6931e6c3; \
lut``name[576]=36'hf66d9e678; \
lut``name[577]=36'hf6481e62b; \
lut``name[578]=36'hf6229e5dd; \
lut``name[579]=36'hf5fd1e58e; \
lut``name[580]=36'hf5d79e53e; \
lut``name[581]=36'hf5b25e4ed; \
lut``name[582]=36'hf58cde49b; \
lut``name[583]=36'hf5679e447; \
lut``name[584]=36'hf5425e3f2; \
lut``name[585]=36'hf51d1e39c; \
lut``name[586]=36'hf4f7de345; \
lut``name[587]=36'hf4d29e2ed; \
lut``name[588]=36'hf4ad5e294; \
lut``name[589]=36'hf4881e239; \
lut``name[590]=36'hf462de1dd; \
lut``name[591]=36'hf43dde180; \
lut``name[592]=36'hf418de122; \
lut``name[593]=36'hf3f39e0c3; \
lut``name[594]=36'hf3ce9e063; \
lut``name[595]=36'hf3a99e001; \
lut``name[596]=36'hf3849df9e; \
lut``name[597]=36'hf35f9df3a; \
lut``name[598]=36'hf33added5; \
lut``name[599]=36'hf315dde6f; \
lut``name[600]=36'hf2f11de08; \
lut``name[601]=36'hf2cc1dd9f; \
lut``name[602]=36'hf2a75dd36; \
lut``name[603]=36'hf2829dccb; \
lut``name[604]=36'hf25dddc5f; \
lut``name[605]=36'hf2391dbf2; \
lut``name[606]=36'hf2149db84; \
lut``name[607]=36'hf1efddb14; \
lut``name[608]=36'hf1cb5daa4; \
lut``name[609]=36'hf1a6dda32; \
lut``name[610]=36'hf1821d9c0; \
lut``name[611]=36'hf15d9d94c; \
lut``name[612]=36'hf1395d8d6; \
lut``name[613]=36'hf114dd860; \
lut``name[614]=36'hf0f05d7e9; \
lut``name[615]=36'hf0cc1d770; \
lut``name[616]=36'hf0a7dd6f7; \
lut``name[617]=36'hf0839d67c; \
lut``name[618]=36'hf05f5d600; \
lut``name[619]=36'hf03b1d583; \
lut``name[620]=36'hf016dd505; \
lut``name[621]=36'heff2dd486; \
lut``name[622]=36'hefce9d405; \
lut``name[623]=36'hefaa9d384; \
lut``name[624]=36'hef869d301; \
lut``name[625]=36'hef629d27d; \
lut``name[626]=36'hef3e9d1f8; \
lut``name[627]=36'hef1add172; \
lut``name[628]=36'heef71d0eb; \
lut``name[629]=36'heed31d063; \
lut``name[630]=36'heeaf5cfd9; \
lut``name[631]=36'hee8b9cf4f; \
lut``name[632]=36'hee681cec3; \
lut``name[633]=36'hee445ce36; \
lut``name[634]=36'hee20dcda9; \
lut``name[635]=36'hedfd1cd1a; \
lut``name[636]=36'hedd99cc89; \
lut``name[637]=36'hedb65cbf8; \
lut``name[638]=36'hed92dcb66; \
lut``name[639]=36'hed6f5cad3; \
lut``name[640]=36'hed4c1ca3e; \
lut``name[641]=36'hed28dc9a8; \
lut``name[642]=36'hed059c912; \
lut``name[643]=36'hece25c87a; \
lut``name[644]=36'hecbf1c7e1; \
lut``name[645]=36'hec9c1c747; \
lut``name[646]=36'hec791c6ac; \
lut``name[647]=36'hec561c610; \
lut``name[648]=36'hec331c572; \
lut``name[649]=36'hec101c4d4; \
lut``name[650]=36'hebed5c434; \
lut``name[651]=36'hebca5c394; \
lut``name[652]=36'heba79c2f2; \
lut``name[653]=36'heb851c24f; \
lut``name[654]=36'heb625c1ab; \
lut``name[655]=36'heb3f9c106; \
lut``name[656]=36'heb1d1c060; \
lut``name[657]=36'heafa9bfb9; \
lut``name[658]=36'head81bf11; \
lut``name[659]=36'heab59be68; \
lut``name[660]=36'hea935bdbe; \
lut``name[661]=36'hea711bd12; \
lut``name[662]=36'hea4edbc66; \
lut``name[663]=36'hea2c9bbb8; \
lut``name[664]=36'hea0a5bb0a; \
lut``name[665]=36'he9e85ba5a; \
lut``name[666]=36'he9c61b9a9; \
lut``name[667]=36'he9a41b8f7; \
lut``name[668]=36'he9825b844; \
lut``name[669]=36'he9605b790; \
lut``name[670]=36'he93e9b6db; \
lut``name[671]=36'he91cdb625; \
lut``name[672]=36'he8fb1b56e; \
lut``name[673]=36'he8d95b4b6; \
lut``name[674]=36'he8b79b3fd; \
lut``name[675]=36'he8961b343; \
lut``name[676]=36'he8749b287; \
lut``name[677]=36'he8531b1cb; \
lut``name[678]=36'he831db10e; \
lut``name[679]=36'he8109b04f; \
lut``name[680]=36'he7ef1af90; \
lut``name[681]=36'he7ce1aecf; \
lut``name[682]=36'he7acdae0e; \
lut``name[683]=36'he78bdad4b; \
lut``name[684]=36'he76a9ac87; \
lut``name[685]=36'he7499abc3; \
lut``name[686]=36'he728daafd; \
lut``name[687]=36'he707daa36; \
lut``name[688]=36'he6e71a96e; \
lut``name[689]=36'he6c65a8a6; \
lut``name[690]=36'he6a59a7dc; \
lut``name[691]=36'he6851a711; \
lut``name[692]=36'he6649a645; \
lut``name[693]=36'he6441a578; \
lut``name[694]=36'he6239a4aa; \
lut``name[695]=36'he6031a3dc; \
lut``name[696]=36'he5e2da30c; \
lut``name[697]=36'he5c29a23b; \
lut``name[698]=36'he5a25a169; \
lut``name[699]=36'he5825a096; \
lut``name[700]=36'he56259fc2; \
lut``name[701]=36'he54259eed; \
lut``name[702]=36'he52259e17; \
lut``name[703]=36'he50299d40; \
lut``name[704]=36'he4e299c68; \
lut``name[705]=36'he4c2d9b8f; \
lut``name[706]=36'he4a359ab5; \
lut``name[707]=36'he483999da; \
lut``name[708]=36'he464198ff; \
lut``name[709]=36'he44499822; \
lut``name[710]=36'he42559744; \
lut``name[711]=36'he405d9665; \
lut``name[712]=36'he3e699585; \
lut``name[713]=36'he3c7594a4; \
lut``name[714]=36'he3a8593c3; \
lut``name[715]=36'he389592e0; \
lut``name[716]=36'he36a591fc; \
lut``name[717]=36'he34b59117; \
lut``name[718]=36'he32c99032; \
lut``name[719]=36'he30d98f4b; \
lut``name[720]=36'he2ef18e64; \
lut``name[721]=36'he2d058d7b; \
lut``name[722]=36'he2b1d8c92; \
lut``name[723]=36'he29358ba7; \
lut``name[724]=36'he274d8abc; \
lut``name[725]=36'he256589cf; \
lut``name[726]=36'he238188e2; \
lut``name[727]=36'he219d87f4; \
lut``name[728]=36'he1fbd8705; \
lut``name[729]=36'he1dd98614; \
lut``name[730]=36'he1bf98523; \
lut``name[731]=36'he1a1d8431; \
lut``name[732]=36'he183d833e; \
lut``name[733]=36'he1661824b; \
lut``name[734]=36'he14858156; \
lut``name[735]=36'he12ad8060; \
lut``name[736]=36'he10d17f69; \
lut``name[737]=36'he0ef97e72; \
lut``name[738]=36'he0d257d79; \
lut``name[739]=36'he0b4d7c80; \
lut``name[740]=36'he09797b85; \
lut``name[741]=36'he07a97a8a; \
lut``name[742]=36'he05d5798e; \
lut``name[743]=36'he04057891; \
lut``name[744]=36'he02357793; \
lut``name[745]=36'he00697694; \
lut``name[746]=36'hdfe997594; \
lut``name[747]=36'hdfcd17493; \
lut``name[748]=36'hdfb057392; \
lut``name[749]=36'hdf93d728f; \
lut``name[750]=36'hdf775718c; \
lut``name[751]=36'hdf5ad7088; \
lut``name[752]=36'hdf3e96f83; \
lut``name[753]=36'hdf2256e7c; \
lut``name[754]=36'hdf0616d76; \
lut``name[755]=36'hdeea16c6e; \
lut``name[756]=36'hdecdd6b65; \
lut``name[757]=36'hdeb216a5b; \
lut``name[758]=36'hde9616951; \
lut``name[759]=36'hde7a56846; \
lut``name[760]=36'hde5e96739; \
lut``name[761]=36'hde431662c; \
lut``name[762]=36'hde279651f; \
lut``name[763]=36'hde0c16410; \
lut``name[764]=36'hddf096300; \
lut``name[765]=36'hddd5561f0; \
lut``name[766]=36'hddba160de; \
lut``name[767]=36'hdd9f15fcc; \
lut``name[768]=36'hdd8415eb9; \
lut``name[769]=36'hdd6915da5; \
lut``name[770]=36'hdd4e15c90; \
lut``name[771]=36'hdd3355b7b; \
lut``name[772]=36'hdd1895a65; \
lut``name[773]=36'hdcfe1594d; \
lut``name[774]=36'hdce395835; \
lut``name[775]=36'hdcc91571c; \
lut``name[776]=36'hdcae95603; \
lut``name[777]=36'hdc94554e8; \
lut``name[778]=36'hdc7a153cd; \
lut``name[779]=36'hdc60152b0; \
lut``name[780]=36'hdc4615193; \
lut``name[781]=36'hdc2c15076; \
lut``name[782]=36'hdc1254f57; \
lut``name[783]=36'hdbf894e38; \
lut``name[784]=36'hdbded4d17; \
lut``name[785]=36'hdbc514bf6; \
lut``name[786]=36'hdbab94ad4; \
lut``name[787]=36'hdb92549b2; \
lut``name[788]=36'hdb78d488e; \
lut``name[789]=36'hdb5f9476a; \
lut``name[790]=36'hdb4694645; \
lut``name[791]=36'hdb2d9451f; \
lut``name[792]=36'hdb14943f9; \
lut``name[793]=36'hdafb942d1; \
lut``name[794]=36'hdae2d41a9; \
lut``name[795]=36'hdaca14080; \
lut``name[796]=36'hdab193f57; \
lut``name[797]=36'hda98d3e2c; \
lut``name[798]=36'hda8093d01; \
lut``name[799]=36'hda6813bd5; \
lut``name[800]=36'hda4fd3aa8; \
lut``name[801]=36'hda379397b; \
lut``name[802]=36'hda1f9384c; \
lut``name[803]=36'hda079371d; \
lut``name[804]=36'hd9efd35ee; \
lut``name[805]=36'hd9d7d34bd; \
lut``name[806]=36'hd9c05338c; \
lut``name[807]=36'hd9a89325a; \
lut``name[808]=36'hd99113127; \
lut``name[809]=36'hd97992ff4; \
lut``name[810]=36'hd96252ebf; \
lut``name[811]=36'hd94b12d8b; \
lut``name[812]=36'hd933d2c55; \
lut``name[813]=36'hd91cd2b1e; \
lut``name[814]=36'hd905d29e7; \
lut``name[815]=36'hd8ef128b0; \
lut``name[816]=36'hd8d812777; \
lut``name[817]=36'hd8c19263e; \
lut``name[818]=36'hd8aad2504; \
lut``name[819]=36'hd894523c9; \
lut``name[820]=36'hd87e1228e; \
lut``name[821]=36'hd86792152; \
lut``name[822]=36'hd85192015; \
lut``name[823]=36'hd83b51ed7; \
lut``name[824]=36'hd82551d99; \
lut``name[825]=36'hd80f51c5a; \
lut``name[826]=36'hd7f991b1b; \
lut``name[827]=36'hd7e3d19db; \
lut``name[828]=36'hd7ce1189a; \
lut``name[829]=36'hd7b891758; \
lut``name[830]=36'hd7a351616; \
lut``name[831]=36'hd78dd14d3; \
lut``name[832]=36'hd77891390; \
lut``name[833]=36'hd7639124b; \
lut``name[834]=36'hd74e51106; \
lut``name[835]=36'hd73990fc1; \
lut``name[836]=36'hd72490e7b; \
lut``name[837]=36'hd70fd0d34; \
lut``name[838]=36'hd6fb10bec; \
lut``name[839]=36'hd6e690aa4; \
lut``name[840]=36'hd6d21095b; \
lut``name[841]=36'hd6bdd0812; \
lut``name[842]=36'hd6a9906c8; \
lut``name[843]=36'hd6955057d; \
lut``name[844]=36'hd68150432; \
lut``name[845]=36'hd66d502e6; \
lut``name[846]=36'hd65990199; \
lut``name[847]=36'hd645d004c; \
lut``name[848]=36'hd6320fefe; \
lut``name[849]=36'hd61e8fdb0; \
lut``name[850]=36'hd60b0fc61; \
lut``name[851]=36'hd5f78fb11; \
lut``name[852]=36'hd5e44f9c1; \
lut``name[853]=36'hd5d14f870; \
lut``name[854]=36'hd5be4f71e; \
lut``name[855]=36'hd5ab4f5cc; \
lut``name[856]=36'hd5984f47a; \
lut``name[857]=36'hd5858f326; \
lut``name[858]=36'hd5730f1d3; \
lut``name[859]=36'hd5608f07e; \
lut``name[860]=36'hd54e0ef29; \
lut``name[861]=36'hd53bcedd4; \
lut``name[862]=36'hd5298ec7e; \
lut``name[863]=36'hd5174eb27; \
lut``name[864]=36'hd5054e9d0; \
lut``name[865]=36'hd4f34e878; \
lut``name[866]=36'hd4e18e71f; \
lut``name[867]=36'hd4cfce5c6; \
lut``name[868]=36'hd4be4e46d; \
lut``name[869]=36'hd4acce313; \
lut``name[870]=36'hd49b4e1b8; \
lut``name[871]=36'hd48a0e05d; \
lut``name[872]=36'hd478cdf01; \
lut``name[873]=36'hd467cdda5; \
lut``name[874]=36'hd456cdc48; \
lut``name[875]=36'hd445cdaeb; \
lut``name[876]=36'hd4350d98d; \
lut``name[877]=36'hd4244d82f; \
lut``name[878]=36'hd413cd6d0; \
lut``name[879]=36'hd4034d571; \
lut``name[880]=36'hd3f30d411; \
lut``name[881]=36'hd3e2cd2b0; \
lut``name[882]=36'hd3d28d14f; \
lut``name[883]=36'hd3c28cfee; \
lut``name[884]=36'hd3b2cce8c; \
lut``name[885]=36'hd3a2ccd2a; \
lut``name[886]=36'hd3930cbc7; \
lut``name[887]=36'hd3838ca63; \
lut``name[888]=36'hd3740c8ff; \
lut``name[889]=36'hd3648c79b; \
lut``name[890]=36'hd3554c636; \
lut``name[891]=36'hd3464c4d1; \
lut``name[892]=36'hd3370c36b; \
lut``name[893]=36'hd3280c205; \
lut``name[894]=36'hd3194c09e; \
lut``name[895]=36'hd30a8bf37; \
lut``name[896]=36'hd2fc0bdcf; \
lut``name[897]=36'hd2ed4bc67; \
lut``name[898]=36'hd2df0bafe; \
lut``name[899]=36'hd2d0cb995; \
lut``name[900]=36'hd2c28b82c; \
lut``name[901]=36'hd2b44b6c2; \
lut``name[902]=36'hd2a64b558; \
lut``name[903]=36'hd2988b3ed; \
lut``name[904]=36'hd28acb282; \
lut``name[905]=36'hd27d0b116; \
lut``name[906]=36'hd26f8afaa; \
lut``name[907]=36'hd2620ae3d; \
lut``name[908]=36'hd254cacd0; \
lut``name[909]=36'hd2478ab63; \
lut``name[910]=36'hd23a8a9f5; \
lut``name[911]=36'hd22d8a887; \
lut``name[912]=36'hd2208a718; \
lut``name[913]=36'hd213ca5a9; \
lut``name[914]=36'hd2074a43a; \
lut``name[915]=36'hd1fa8a2ca; \
lut``name[916]=36'hd1ee4a15a; \
lut``name[917]=36'hd1e1c9fea; \
lut``name[918]=36'hd1d589e79; \
lut``name[919]=36'hd1c989d07; \
lut``name[920]=36'hd1bd89b96; \
lut``name[921]=36'hd1b189a23; \
lut``name[922]=36'hd1a5c98b1; \
lut``name[923]=36'hd19a4973e; \
lut``name[924]=36'hd18e895cb; \
lut``name[925]=36'hd18349457; \
lut``name[926]=36'hd177c92e4; \
lut``name[927]=36'hd16cc916f; \
lut``name[928]=36'hd16188ffb; \
lut``name[929]=36'hd15688e86; \
lut``name[930]=36'hd14bc8d10; \
lut``name[931]=36'hd14108b9b; \
lut``name[932]=36'hd13648a25; \
lut``name[933]=36'hd12bc88af; \
lut``name[934]=36'hd12148738; \
lut``name[935]=36'hd117085c1; \
lut``name[936]=36'hd10cc844a; \
lut``name[937]=36'hd102c82d2; \
lut``name[938]=36'hd0f8c815a; \
lut``name[939]=36'hd0eec7fe2; \
lut``name[940]=36'hd0e507e69; \
lut``name[941]=36'hd0db87cf0; \
lut``name[942]=36'hd0d207b77; \
lut``name[943]=36'hd0c8879fe; \
lut``name[944]=36'hd0bf47884; \
lut``name[945]=36'hd0b60770a; \
lut``name[946]=36'hd0ad07590; \
lut``name[947]=36'hd0a407415; \
lut``name[948]=36'hd09b4729a; \
lut``name[949]=36'hd0928711f; \
lut``name[950]=36'hd08a06fa4; \
lut``name[951]=36'hd08186e28; \
lut``name[952]=36'hd07906cac; \
lut``name[953]=36'hd070c6b30; \
lut``name[954]=36'hd068869b3; \
lut``name[955]=36'hd06086837; \
lut``name[956]=36'hd058c66ba; \
lut``name[957]=36'hd050c653c; \
lut``name[958]=36'hd049463bf; \
lut``name[959]=36'hd04186241; \
lut``name[960]=36'hd03a060c3; \
lut``name[961]=36'hd032c5f45; \
lut``name[962]=36'hd02b85dc7; \
lut``name[963]=36'hd02485c48; \
lut``name[964]=36'hd01d85ac9; \
lut``name[965]=36'hd0168594a; \
lut``name[966]=36'hd00fc57cb; \
lut``name[967]=36'hd0090564b; \
lut``name[968]=36'hd002854cc; \
lut``name[969]=36'hcffc4534c; \
lut``name[970]=36'hcff5c51cc; \
lut``name[971]=36'hcfefc504b; \
lut``name[972]=36'hcfe984ecb; \
lut``name[973]=36'hcfe384d4a; \
lut``name[974]=36'hcfddc4bc9; \
lut``name[975]=36'hcfd804a48; \
lut``name[976]=36'hcfd2848c7; \
lut``name[977]=36'hcfcd04745; \
lut``name[978]=36'hcfc7845c4; \
lut``name[979]=36'hcfc244442; \
lut``name[980]=36'hcfbd442c0; \
lut``name[981]=36'hcfb80413e; \
lut``name[982]=36'hcfb343fbc; \
lut``name[983]=36'hcfae83e39; \
lut``name[984]=36'hcfa9c3cb7; \
lut``name[985]=36'hcfa543b34; \
lut``name[986]=36'hcfa0c39b1; \
lut``name[987]=36'hcf9c4382e; \
lut``name[988]=36'hcf98436ab; \
lut``name[989]=36'hcf9403528; \
lut``name[990]=36'hcf90033a4; \
lut``name[991]=36'hcf8c43221; \
lut``name[992]=36'hcf888309d; \
lut``name[993]=36'hcf84c2f1a; \
lut``name[994]=36'hcf8142d96; \
lut``name[995]=36'hcf7e02c12; \
lut``name[996]=36'hcf7ac2a8e; \
lut``name[997]=36'hcf778290a; \
lut``name[998]=36'hcf7482785; \
lut``name[999]=36'hcf7182601; \
lut``name[1000]=36'hcf6ec247c; \
lut``name[1001]=36'hcf6c022f8; \
lut``name[1002]=36'hcf6982173; \
lut``name[1003]=36'hcf6701fef; \
lut``name[1004]=36'hcf6481e6a; \
lut``name[1005]=36'hcf6241ce5; \
lut``name[1006]=36'hcf6041b60; \
lut``name[1007]=36'hcf5e419db; \
lut``name[1008]=36'hcf5c81856; \
lut``name[1009]=36'hcf5a816d1; \
lut``name[1010]=36'hcf590154c; \
lut``name[1011]=36'hcf57813c6; \
lut``name[1012]=36'hcf5601241; \
lut``name[1013]=36'hcf54c10bc; \
lut``name[1014]=36'hcf5380f36; \
lut``name[1015]=36'hcf5280db1; \
lut``name[1016]=36'hcf5180c2c; \
lut``name[1017]=36'hcf50c0aa6; \
lut``name[1018]=36'hcf5000921; \
lut``name[1019]=36'hcf4f8079b; \
lut``name[1020]=36'hcf4f00616; \
lut``name[1021]=36'hcf4ec0490; \
lut``name[1022]=36'hcf4e8030b; \
lut``name[1023]=36'hcf4e40185;
rtl/mac_test.v 0 → 100644
View file @ 1bd30289
module mac_test(
input clk_i,
input rst_n_i,
input signed [63:0] acc_i,
input [1:0] op_i,
input signed [31:0] a_i,
input signed [31:0] b_i,
output signed [63:0] q_o);
reg signed [63:0] acc0, acc1, acc2, m0, d0;
`define op_mul 2'b00
`define op_mac 2'b01
`define op_load 2'b10
`define op_trunc 2'b11
reg [1:0] s2_op, s3_op, s4_op;
always@(posedge clk_i)
begin
case(op_i)
`op_mac: m0 <= a_i * b_i;
`op_mul: m0 <= a_i * b_i;
`op_load: d0 <= acc_i;
default: m0 <= a_i * b_i;
endcase // case (op_i)
s2_op <= op_i;
end // always@ (posedge clk_i)
always@(posedge clk_i)
begin
s3_op <= s2_op;
case(s2_op)
`op_mac: acc0 <= acc0 + m0;
`op_load: acc0 <= d0;
default: acc0 <= m0;
endcase // case (s2_op)
end
always@(posedge clk_i)
begin
s4_op <= s3_op;
acc1 <=acc0;
end
always@(posedge clk_i)
if(s4_op == `op_trunc)
acc2 <= acc1 >> 30;
else
acc2 <= acc1;
assign q_o = acc2;
endmodule // mac_test
\ No newline at end of file
rtl/max5870_serializer.vhd 0 → 100644
View file @ 1bd30289
-- file: max5870_serializer.vhd
-- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity max5870_serializer is
generic
(-- width of the data for the system
sys_w : integer := 14;
-- width of the data for the device
dev_w : integer := 56);
port
(
-- From the device out to the system
DATA_OUT_FROM_DEVICE : in std_logic_vector(dev_w-1 downto 0);
DATA_OUT_TO_PINS_P : out std_logic_vector(sys_w-1 downto 0);
DATA_OUT_TO_PINS_N : out std_logic_vector(sys_w-1 downto 0);
-- Clock and reset signals
CLK_IN : in std_logic; -- Fast clock from PLL/MMCM
CLK_DIV_IN : in std_logic; -- Slow clock from PLL/MMCM
LOCKED_IN : in std_logic;
LOCKED_OUT : out std_logic;
CLK_RESET : in std_logic; -- Reset signal for Clock circuit
IO_RESET : in std_logic); -- Reset signal for IO circuit
end max5870_serializer;
architecture xilinx of max5870_serializer is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "max5870_serializer,selectio_wiz_v3_2,{component_name=max5870_serializer,bus_dir=OUTPUTS,bus_sig_type=DIFF,bus_io_std=LVDS_25,use_serialization=true,use_phase_detector=false,serialization_factor=4,enable_bitslip=false,enable_train=false,system_data_width=14,bus_in_delay=NONE,bus_out_delay=NONE,clk_sig_type=SINGLE,clk_io_std=LVCMOS18,clk_buf=BUFPLL,active_edge=RISING,clk_delay=NONE,v6_bus_in_delay=NONE,v6_bus_out_delay=NONE,v6_clk_buf=BUFIO,v6_active_edge=NOT_APP,v6_ddr_alignment=SAME_EDGE_PIPELINED,v6_oddr_alignment=SAME_EDGE,ddr_alignment=C0,v6_interface_type=NETWORKING,interface_type=NETWORKING,v6_bus_in_tap=0,v6_bus_out_tap=0,v6_clk_io_std=LVCMOS18,v6_clk_sig_type=DIFF}";
constant clock_enable : std_logic := '1';
signal unused : std_logic;
signal clk_in_int_buf : std_logic;
signal clk_div_in_int : std_logic;
-- Before the buffer
signal data_out_to_pins_int : std_logic_vector(sys_w-1 downto 0);
-- Between the delay and serdes
signal data_out_to_pins_predelay : std_logic_vector(sys_w-1 downto 0);
constant num_serial_bits : integer := dev_w/sys_w;
type serdarr is array (0 to 7) of std_logic_vector(sys_w-1 downto 0);
-- Array to use intermediately from the serdes to the internal
-- devices. bus "0" is the leftmost bus
-- * fills in from higher order
signal oserdes_d : serdarr := (( others => (others => '0')));
signal serdesstrobe : std_logic;
signal ocascade_ms_d : std_logic_vector(sys_w-1 downto 0);
signal ocascade_ms_t : std_logic_vector(sys_w-1 downto 0);
signal ocascade_sm_d : std_logic_vector(sys_w-1 downto 0);
signal ocascade_sm_t : std_logic_vector(sys_w-1 downto 0);
begin
-- Create the clock logic
bufpll_inst : BUFPLL
generic map (
DIVIDE => 4)
port map (
IOCLK => clk_in_int_buf,
LOCK => LOCKED_OUT,
SERDESSTROBE => serdesstrobe,
GCLK => CLK_DIV_IN, -- GCLK pin must be driven by BUFG
LOCKED => LOCKED_IN,
PLLIN => CLK_IN);
-- We have multiple bits- step over every bit, instantiating the required elements
pins: for pin_count in 0 to sys_w-1 generate
begin
-- Instantiate the buffers
----------------------------------
-- Instantiate a buffer for every bit of the data bus
obufds_inst : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => DATA_OUT_TO_PINS_P (pin_count),
OB => DATA_OUT_TO_PINS_N (pin_count),
I => data_out_to_pins_int(pin_count));
-- Pass through the delay
-----------------------------------
data_out_to_pins_int(pin_count) <= data_out_to_pins_predelay(pin_count);
-- Instantiate the serdes primitive
----------------------------------
-- declare the oserdes
oserdes2_master : OSERDES2
generic map (
DATA_RATE_OQ => "SDR",
DATA_RATE_OT => "SDR",
TRAIN_PATTERN => 0,
DATA_WIDTH => 4,
SERDES_MODE => "NONE",
OUTPUT_MODE => "SINGLE_ENDED")
port map (
D1 => oserdes_d(3)(pin_count),
D2 => oserdes_d(2)(pin_count),
D3 => oserdes_d(1)(pin_count),
D4 => oserdes_d(0)(pin_count),
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
SHIFTIN1 => '1',
SHIFTIN2 => '1',
SHIFTIN3 => '1',
SHIFTIN4 => '1',
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TRAIN => '0',
OCE => clock_enable,
CLK0 => clk_in_int_buf,
CLK1 => '0',
CLKDIV => CLK_DIV_IN,
OQ => data_out_to_pins_predelay(pin_count),
TQ => open,
IOCE => serdesstrobe,
TCE => clock_enable,
RST => IO_RESET);
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
out_slices: for slice_count in 0 to num_serial_bits-1 generate begin
-- This places the first data in time on the right
oserdes_d(4-slice_count-1) <=
DATA_OUT_FROM_DEVICE(slice_count*sys_w+sys_w-1 downto slice_count*sys_w);
-- To place the first data in time on the left, use the
-- following code, instead
-- oserdes_d(slice_count) <=
-- DATA_OUT_FROM_DEVICE(slice_count*sys_w+sys_w-1 downto slice_count*sys_w);
end generate out_slices;
end generate pins;
end xilinx;
rtl/mdsp.v 0 → 100644
View file @ 1bd30289
`timescale 1ns/1ns
module mdsp (
input clk_i,
input rst_n_i,
output x_req_o,
input x_valid_i,
input signed [23:0] x_i,
output reg y_valid_o,
input y_req_i,
output reg signed [23:0] y_o,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
output [31:0] wb_dat_o,
output reg wb_stall_o,
output reg wb_ack_o
);
/*
opcode format
[mac/mul/write] : 2 bits
[coef] : 32 bits
[src] : 7 bits
[dst] : 7 bits
*/
parameter g_data_bits = 32;
parameter g_coef_bits = 18;
parameter g_acc_shift = 17;
parameter g_state_bits = 7;
parameter g_microcode_size = 128;
localparam c_acc_width = 2 + g_coef_bits + g_data_bits;
localparam c_microcode_addr_bits = 7;
//$clogb2(g_microcode_size);
// stage 1 control (fetch)
reg [g_state_bits-1:0] f_didx, f_sidx;
reg signed [g_coef_bits-1:0] f_coef;
reg f_mul_only, f_write_dest, f_write_out, f_store_acc, f_use_in;
reg [3:0] f_oidx;
reg [2:0] f_opcode;
// stage 1a control (fetch)
reg [g_state_bits-1:0] pd_didx, pd_sidx;
reg signed [g_coef_bits-1:0] pd_coef;
reg pd_mul_only, pd_write_dest, pd_write_out, pd_store_acc, pd_finish, pd_use_in;
reg [3:0] pd_oidx;
reg signed [g_data_bits -1 :0 ] pd_state;
reg [2:0] pd_opcode;
// stage 2 control (decode / fetch source)
reg [g_state_bits-1:0] d_didx;
reg signed [g_coef_bits-1:0] d_coef;
reg d_mul_only, d_write_dest, d_write_out, d_store_acc,d_use_in;
reg [3:0] d_oidx;
reg signed [g_data_bits -1 :0 ] d_state;
reg [2:0] d_opcode;
// stage 3 control (execute 1)
reg [g_state_bits-1:0] e1_didx;
reg e1_write_dest, e1_write_out, e1_store_acc;
reg [3:0] e1_oidx;
reg signed [g_data_bits -1 :0 ] e1_state;
reg [2:0] e1_opcode;
// stage 4 control (execute 2)
reg [g_state_bits-1:0] e2_didx;
reg e2_write_dest, e2_write_out, e2_store_acc;
reg [3:0] e2_oidx;
reg signed [g_data_bits -1 :0 ] e2_state;
reg [2:0] e2_opcode;
// stage 4 control (execute 2)
reg [g_state_bits-1:0] e3_didx;
reg e3_write_dest, e3_write_out, e3_store_acc;
reg [3:0] e3_oidx;
reg signed [g_data_bits -1 :0 ] e3_state;
reg [2:0] e3_opcode;
reg signed [c_acc_width-1:0] acc0, acc1, acc2, m0;
reg signed [g_data_bits-1:0] acc_trunc;
reg signed [g_data_bits-1:0] state_mem[0: 2**g_state_bits-1];
reg [c_microcode_addr_bits-1:0] pc,pc_d0;
reg [63:0] microcode[0:2**c_microcode_addr_bits-1];
reg [31:0] mc_in_hi, mc_in_lo;
reg stall;
reg reset_wb = 0;
wire rst_n = rst_n_i & ~reset_wb;
`define opc_mul 3'b000
`define opc_mac 3'b001
`define opc_clamph 3'b010
`define opc_clampl 3'b011
`define opc_finish 3'b111
reg [31:0] ram_tmp;
/*
generic_dpram
#(
.g_data_width(32),
.g_size (g_microcode_size),
.g_dual_clock (0)
) U_MC_Ram_HI (
.rst_n_i (rst_n_i),
.clka_i (clk_i),
.wea_i (wb_we_i && wb_adr_i[11] && wb_adr_i[2]),
.aa_i (wb_adr_i [9:3]),
.da_i (wb_dat_i),
.ab_i (pc[6:0]),
.qb_o (mc_in_hi));
generic_dpram
#(
.g_data_width(32),
.g_size (g_microcode_size),
.g_dual_clock (0)
) U_MC_Ram_LO (
.rst_n_i (rst_n_i),
.clka_i (clk_i),
.wea_i (wb_we_i && wb_adr_i[11] && !wb_adr_i[2]),
.aa_i (wb_adr_i [9:3]),
.da_i (wb_dat_i),
.ab_i (pc[6:0]),
.qb_o (mc_in_lo));
*/
always@(posedge clk_i)
if(!rst_n_i) begin
wb_stall_o <= 0;
wb_ack_o <= 0;
reset_wb <= 1;
end else if(wb_cyc_i && wb_stb_i)
begin
if(wb_we_i && wb_adr_i[11] && wb_adr_i[2])
ram_tmp <= wb_dat_i;
// microcode_hi[wb_adr_i [10:3]] <= wb_dat_i;
else if(wb_we_i && wb_adr_i[11] && !wb_adr_i[2])
microcode[wb_adr_i [10:3]] <= {ram_tmp, wb_dat_i};
else if (wb_we_i && !wb_adr_i[11])
reset_wb <= wb_dat_i[0];
wb_ack_o <= 1;
end else
wb_ack_o <= 0;
// pipeline stall control
always @(*)
if(!x_valid_i && pd_use_in)
stall <= 1;
else if(!y_req_i && e2_write_out)
stall <= 1;
else
stall <= 0;
// synthesis attribute ram_style of microcode is "block";
always@(microcode, pc_d0)
{ mc_in_hi, mc_in_lo } <= microcode[pc_d0];
reg rst_n_d0 = 0;
always@(posedge clk_i)
rst_n_d0 <= rst_n;
always@(posedge clk_i)
if(!rst_n || !rst_n_d0 || (!stall && d_opcode == `opc_finish))
pc <= 1;
else if (!stall)
pc <= pc + 1;
always@(posedge clk_i)
if(!rst_n || !rst_n_d0 || (!stall && d_opcode == `opc_finish))
pc_d0 <= 0;
else if(!stall)
pc_d0 <= pc;
// synthesis translate_off
initial begin : init_sram
integer i;
for(i=0;i< (1<<g_state_bits) ;i=i+1)
state_mem[i]=0;
end
// synthesis translate_on
// stage 0: fetch next instruction word, increase PC
always@(mc_in_hi, mc_in_lo)
begin
f_opcode[2] <= mc_in_hi[31];
f_opcode[1] <= mc_in_hi[30];
f_opcode[0] <= mc_in_hi[35-32];
f_write_dest <= mc_in_hi[61-32];
f_write_out <= mc_in_hi[60-32];
f_use_in <= mc_in_hi[59-32];
f_store_acc <= mc_in_hi[58-32];
f_oidx <= mc_in_hi[57-32:56-32];
f_sidx <= mc_in_hi[55-32:46-32];
f_didx <= mc_in_hi[45-32:36-32];
f_coef <= {mc_in_hi[1:0] , mc_in_lo };
end
assign x_req_o = (pd_use_in & rst_n) & ~x_valid_i;
always@(posedge clk_i)
if(!rst_n) begin
pd_write_dest <= 0;
pd_write_out <= 0;
pd_store_acc <= 0;
pd_use_in <= 0;
pd_opcode <= 0;
end else if(!stall)
begin
pd_opcode <= f_opcode;
pd_coef <= f_coef;
pd_write_dest <= f_write_dest;
pd_write_out <= f_write_out;
pd_store_acc <= f_store_acc;
pd_oidx <= f_oidx;
pd_didx <= f_didx;
pd_sidx <= f_sidx;
pd_state <= x_i;
pd_use_in <= f_use_in;
end
always@(posedge clk_i)
if(!rst_n) begin
d_write_dest <= 0;
d_write_out <= 0;
d_store_acc <= 0;
d_opcode <=0;
d_use_in <= 0;
end else
if(!stall)
begin
d_opcode <= pd_opcode;
d_use_in <= pd_use_in;
d_coef <= pd_coef;
d_write_dest <= pd_write_dest;
d_write_out <= pd_write_out;
d_store_acc <= pd_store_acc;
d_oidx <= pd_oidx;
d_didx <= pd_didx;
if(pd_use_in)
d_state <= x_i;
else
d_state <= state_mem[pd_sidx];
end
always@(posedge clk_i)
if(!rst_n)
begin
acc0 <= 0;
e1_write_dest <= 0;
e1_write_out <= 0;
e1_store_acc <= 0;
e1_opcode <= 0;
end else if(!stall)
begin
e1_write_dest <= d_write_dest;
e1_write_out <= d_write_out;
e1_store_acc <= d_store_acc;
e1_oidx <= d_oidx;
e1_didx <= d_didx;
e1_state <= d_state;
e1_opcode <= d_opcode;
m0 <= d_state * d_coef;
// case(d_opcode)
/* `opc_mul:
acc0 <= d_state * d_coef;
`opc_mac:
acc0 <= acc0 + d_state * d_coef;
`opc_mul:
acc0 <= d_state * d_coef;*/
// default:
/* `opc_clamph:
if((acc0 >> g_acc_shift) > d_coef)
acc0 <= d_coef << g_acc_shift;
`opc_clampl:
if((acc0 >> g_acc_shift) < d_coef)
acc0 <= d_coef << g_acc_shift;*/
// endcase // case (d_opcode)
end
always@(posedge clk_i)
if(!rst_n)
begin
e2_write_dest <= 0;
e2_write_out <= 0;
e2_store_acc <= 0;
e2_opcode <= 0;
end else begin
if(!stall)
begin
case (e1_opcode)
`opc_mul:
acc1 <= m0;
`opc_mac:
acc1 <= acc1 + m0;
default:
acc1 <= m0;
endcase // case (e1_opcode)
e2_opcode <= e1_opcode;
e2_write_dest <= e1_write_dest;
e2_write_out <= e1_write_out;
e2_store_acc <= e1_store_acc;
e2_oidx <= e1_oidx;
e2_didx <= e1_didx;
e2_state <= e1_state;
//acc1 <= acc0;
end
end // else: !if(!rst_)n
always@(posedge clk_i)
if(!rst_n)
begin
e3_write_dest <= 0;
e3_write_out <= 0;
e3_store_acc <= 0;
end else begin
if(!stall)
begin
acc2<=acc1;
e3_write_dest <= e2_write_dest;
e3_write_out <= e2_write_out;
e3_store_acc <= e2_store_acc;
e3_oidx <= e2_oidx;
e3_didx <= e2_didx;
e3_state <= e2_state;
//acc1 <= acc0;
end
end // else: !if(!rst_n)
always@(acc2)
if(acc2[g_acc_shift-1])
acc_trunc <= (acc2 >> g_acc_shift);
else
acc_trunc <= (acc2 >> g_acc_shift);
always@(posedge clk_i)
if(!stall) begin
if(e3_store_acc)
state_mem[e3_didx] <= acc_trunc;
else if(e2_write_dest)
state_mem[e3_didx] <= e3_state;
if(e3_write_out) begin
y_o <= acc_trunc;
y_valid_o <= 1;
end else begin
y_valid_o <= 0;
end
end // if (!stall)
endmodule // mdsp
rtl/pi_control.v 0 → 100644
View file @ 1bd30289
module pi_control(
input clk_i,
input rst_n_i,
input d_valid_i,
input [15:0] d_i,
output reg q_valid_o,
output reg signed [15:0] q_o,
input signed [15:0] ki_i,
input signed [15:0] kp_i
);
parameter g_goal = 32768;
parameter g_acc_shift = 6;
reg signed [39:0] acc;
reg signed [15:0] err,d0,d1;
reg [4:0] stage;
reg clip_plus;
reg clip_minus;
wire signed [17:0] ds;
assign ds = {3'b0, d_i} - g_goal;
always@(posedge clk_i)
if(!rst_n_i) begin
stage[0] <= 0;
acc <= 0;
end else begin
stage[0] <= d_valid_i;
if(d_valid_i) begin
$display("%d %d", ds <0, !clip_minus);
if(clip_plus && ds<0)
acc <= acc + ds;
else if(clip_minus && ds>0)
acc <= acc + ds;
else if (!clip_plus && !clip_minus)
acc <= acc + ds;
d0 <= ds;
end
end
reg signed [39 - g_acc_shift : 0] acc0;
always@(posedge clk_i)
if(!rst_n_i) begin
stage[1] <= 0;
end else begin
acc0 <= acc >> g_acc_shift;
d1<=d0;
stage[1] <= stage[0];
end
reg signed [23:0] term_p, term_i, sum;
wire signed [24 + 30 - 1 : 0] mul_p, mul_i;
assign mul_i = acc0 * ki_i;
assign mul_p = d1 * kp_i;
always@(posedge clk_i)
if(!rst_n_i) begin
stage[2] <= 0;
end else begin
stage[2]<=stage[1];
term_i <= mul_i >> 16;
term_p <= mul_p >> 16;
end
always@(posedge clk_i)
if(!rst_n_i) begin
stage[3] <= 0;
end else begin
sum <= term_p + term_i;
stage[3] <= stage[2];
end
always@(posedge clk_i)
if(!rst_n_i) begin
q_valid_o <= 0;
clip_plus <=0;
clip_minus <= 0;
end else begin
if(stage[3])
begin
if(sum < -32767) begin
clip_minus <= 1;
clip_plus<= 0;
q_o <= -32767;
end else if(sum > 32767) begin
clip_minus <= 0;
clip_plus<= 1;
q_o <= 32767;
end else begin
clip_minus <= 0;
clip_plus<= 0;
q_o <= sum;
end
end
q_valid_o <= stage[3];
end
endmodule
\ No newline at end of file
rtl/spi_master.vhd 0 → 100644
View file @ 1bd30289
-----------------------------------------------------------------------------
-- Title : SPI Bus Master
-- Project : Simple VME64x FMC Carrier (SVEC)
-------------------------------------------------------------------------------
-- File : spi_master.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-05-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Just a simple SPI master (bus-less).
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011-2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_master is
generic(
-- clock division ratio (SCLK = clk_sys_i / (2 ** g_div_ratio_log2).
g_div_ratio_log2 : integer := 2;
-- number of data bits per transfer
g_num_data_bits : integer := 2);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- 1: start next transfer (using CPOL, DATA and SEL from the inputs below)
start_i : in std_logic;
-- Clock polarity: 1: slave clocks in the data on rising SCLK edge, 0: ...
-- on falling SCLK edge
cpol_i : in std_logic;
-- TX Data input
data_i : in std_logic_vector(g_num_data_bits - 1 downto 0);
drdy_o : out std_logic;
-- 1: data_o contains the result of last read operation. Core is ready to initiate
-- another transfer.
ready_o : out std_logic;
-- data read from selected slave, valid when ready_o == 1.
data_o : out std_logic_vector(g_num_data_bits - 1 downto 0);
-- these are obvious
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end spi_master;
architecture behavioral of spi_master is
signal divider : unsigned(11 downto 0);
signal tick : std_logic;
signal sreg : std_logic_vector(g_num_data_bits-1 downto 0);
signal rx_sreg : std_logic_vector(g_num_data_bits-1 downto 0);
type t_state is (IDLE, TX_CS, TX_DAT1, TX_DAT2, TX_SCK1, TX_SCK2, TX_CS2, TX_GAP);
signal state : t_state;
signal sclk : std_logic;
signal counter : unsigned(4 downto 0);
begin -- rtl
-- Simple clock divder. Produces a 'tick' signal which defines the timing for
-- the main state machine transitions.
p_divide_spi_clock : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
divider <= (others => '0');
else
if(start_i = '1' or tick = '1') then
divider <= (others => '0');
else
divider <= divider + 1;
end if;
end if;
end if;
end process;
tick <= divider(g_div_ratio_log2);
-- Main state machine. Executes SPI transfers
p_main_fsm : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= IDLE;
sclk <= '0';
sreg <= (others => '0');
rx_sreg <= (others => '0');
spi_mosi_o <= '0';
counter <= (others => '0');
drdy_o <= '0';
else
case state is
-- Waits for start of transfer command
when IDLE =>
sclk <= '0';
counter <= (others => '0');
if(start_i = '1') then
sreg <= data_i;
state <= TX_CS;
spi_mosi_o <= data_i(sreg'high);
end if;
-- Generates a gap between the externally asserted Chip Select and
-- the beginning of data transfer
when TX_CS =>
if tick = '1' then
state <= TX_DAT1;
end if;
-- Outputs subsequent bits to MOSI line.
when TX_DAT1 =>
if(tick = '1') then
spi_mosi_o <= sreg(sreg'high);
sreg <= sreg(sreg'high-1 downto 0) & '0';
state <= TX_SCK1;
end if;
-- Flips the SCLK (active edge)
when TX_SCK1 =>
if(tick = '1') then
sclk <= not sclk;
counter <= counter + 1;
state <= TX_DAT2;
end if;
-- Shifts in bits read from the slave
when TX_DAT2 =>
if(tick = '1') then
rx_sreg <= rx_sreg(rx_sreg'high-1 downto 0) & spi_miso_i;
state <= TX_SCK2;
end if;
-- Flips the SCLK (inactive edge). Checks if all bits have been
-- transferred.
when TX_SCK2 =>
if(tick = '1') then
sclk <= not sclk;
if(counter = g_num_data_bits) then
state <= TX_CS2;
else
state <= TX_DAT1;
end if;
end if;
-- Generates a gap for de-assertoin of CS line
when TX_CS2 =>
if(tick = '1') then
state <= TX_GAP;
data_o <= rx_sreg;
drdy_o <= '1';
end if;
when TX_GAP =>
drdy_o <= '0';
if (tick = '1') then
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
ready_o <= '1' when (state = IDLE and start_i = '0') else '0';
-- SCLK polarity control
spi_sclk_o <= sclk xor cpol_i;
end behavioral;
rtl/streamers/Manifest.py 0 → 100644
View file @ 1bd30289
files = [ "xtx_streamer.vhd", "tx_streamer.vhd", "xrx_streamer.vhd", "rx_streamer.vhd", "gc_escape_inserter.vhd", "gc_escape_detector.vhd", "dropping_buffer.vhd","streamers_pkg.vhd" ]
rtl/streamers/dropping_buffer.vhd 0 → 100644
View file @ 1bd30289
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity dropping_buffer is
generic (
g_size : integer;
g_data_width : integer);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
d_req_o : out std_logic;
d_drop_i : in std_logic;
d_accept_i : in std_logic;
d_valid_i : in std_logic;
d_o : out std_logic_vector(g_data_width-1 downto 0);
d_valid_o : out std_logic;
d_req_i : in std_logic);
end dropping_buffer;
architecture behavioral of dropping_buffer is
type t_mem_array is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
subtype t_counter is unsigned(f_log2_size(g_size)-1 downto 0);
signal wr_ptr, rd_ptr, boundary : t_counter := (others => '0');
signal full, empty_comb : std_logic;
signal empty_reg : std_logic := '0';
signal mem : t_mem_array;
begin -- behavioral
p_counters : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ptr <= (others => '0');
rd_ptr <= (others => '0');
boundary <= (others => '0');
else
if(d_accept_i = '1') then
boundary <= wr_ptr;
end if;
if(d_drop_i = '1') then
wr_ptr <= boundary;
elsif(d_valid_i = '1' and full = '0') then
wr_ptr <= wr_ptr + 1;
end if;
if (d_req_i = '1' and empty_reg = '0' and empty_comb = '0') then
rd_ptr <= rd_ptr + 1;
end if;
end if;
end if;
end process;
empty_comb <= '1' when (boundary = rd_ptr) else '0';
full <= '1' when (wr_ptr + 1 = rd_ptr) else '0';
d_req_o <= not full;
p_empty_reg : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
empty_reg <= '1';
else
empty_reg <= empty_comb;
end if;
end if;
end process;
p_mem_read : process(clk_i)
begin
if rising_edge(clk_i) then
if(d_req_i = '1' and empty_reg = '0' and empty_comb = '0') then
d_o <= mem(to_integer(rd_ptr));
d_valid_o <= '1';
else
d_valid_o <= '0';
end if;
end if;
end process;
p_mem_write : process(clk_i)
begin
if rising_edge(clk_i) then
if(d_valid_i = '1') then
mem(to_integer(wr_ptr)) <= d_i;
end if;
end if;
end process;
end behavioral;
rtl/streamers/gc_escape_detector.vhd 0 → 100644
View file @ 1bd30289
library ieee;
use ieee.std_logic_1164.all;
entity escape_detector is
generic(
g_data_width : integer;
g_escape_code : std_logic_vector
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
d_detect_enable_i : in std_logic;
d_valid_i : in std_logic;
d_req_o : out std_logic;
d_o : out std_logic_vector(g_data_width-1 downto 0);
d_escape_o : out std_logic;
d_valid_o : out std_logic;
d_req_i : in std_logic
);
end escape_detector;
architecture behavioral of escape_detector is
type t_state is (IDLE, CHECK_ESCAPE);
signal state : t_state;
signal is_escape_code : std_logic;
begin -- behavioral
d_req_o <= d_req_i;
is_escape_code <= '1' when (d_detect_enable_i = '1' and state = IDLE and d_valid_i = '1' and d_i = g_escape_code) else '0';
d_o <= g_escape_code when (state = CHECK_ESCAPE and d_i = x"0000") else d_i;
d_valid_o <= d_valid_i and not is_escape_code;
d_escape_o <= '1' when (state = CHECK_ESCAPE and d_i /= x"0000") else '0';
p_fsm : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' or d_detect_enable_i = '0' then
state <= IDLE;
else
case state is
when IDLE =>
if(d_i = g_escape_code and d_valid_i = '1') then
state <= CHECK_ESCAPE;
end if;
when CHECK_ESCAPE =>
if(d_valid_i = '1') then
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
end behavioral;
rtl/streamers/gc_escape_inserter.vhd 0 → 100644
View file @ 1bd30289
-------------------------------------------------------------------------------
-- Title : Escape insertion unit
-- Project : General cores library
-------------------------------------------------------------------------------
-- File : gc_escape_inserter.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-10-01
-- Last update: 2012-10-10
-- Platform : FPGA-generic
-- Standard : VHDL '93
------------------------------------------------------------------------------
-- Description: Unit for inserting escaped codes in a continuous data stream.
-- Allows for insertion of easily distinguishable control codes, such as start-
-- or end-of-frame markers. Given an input tuple (E[d_escape_i], D[d_i]), the
-- output (d_o) is:
-- - D when E == 0 and D != g_escape_code
-- - g_escape_code followed by 0 when E == 0 and D == g_escape_code
-- - g_escape_code followed by D when E == 1.
-- Note: When E == 1, D must not be 0.
------------------------------------------------------------------------------
--
-- Copyright (c) 2012 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity gc_escape_inserter is
generic(
-- data path width
g_data_width : integer;
-- unique escape character (of g_data_width bits), must not be 0.
g_escape_code : std_logic_vector
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- data input (unescaped)
d_i : in std_logic_vector(g_data_width-1 downto 0);
-- when 1, escape insertion logic is enabled (i.e. if d_i == g_escape_code,
-- it's translated to g_escape_code followed by 0 instead of just being passed
-- through
d_insert_enable_i : in std_logic;
-- when 1, d_i is treated as a escaped character
d_escape_i : in std_logic;
-- when 1, d_i and d_escape_i contain valid character
d_valid_i : in std_logic;
-- when 1, module can accept data in the following clock cycle.
d_req_o : out std_logic;
-- data output
d_o : out std_logic_vector (g_data_width-1 downto 0);
-- when 1, d_o contains a valid character
d_valid_o : out std_logic;
-- when 1, d_o/d_valid_o may output a character in the next clock cycle.
d_req_i : in std_logic
);
end gc_escape_inserter;
architecture behavioral of gc_escape_inserter is
type t_state is (IDLE, INSERT_ESCAPE);
signal d_prev : std_logic_vector(g_data_width-1 downto 0);
signal d_req_prev : std_logic;
signal state : t_state;
signal match_esc_code : std_logic;
begin -- behavioral
match_esc_code <= '1' when d_i = g_escape_code else '0';
-- stop the traffic if we need to insert an escaped sequence. This
-- can happen when
-- - the input character is an escape code (d_escape_i = '1')
-- - the input character is not to be escaped, but it's equal to g_escape_code
d_req_o <= d_req_i and not (d_valid_i and (d_escape_i or match_esc_code));
d_o <= d_prev when (state = INSERT_ESCAPE) else
d_i when d_escape_i = '0' else
g_escape_code;
d_valid_o <= d_valid_i when (state = IDLE) else
d_req_prev;
p_fsm : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' or d_insert_enable_i = '0' then
state <= IDLE;
d_req_prev <= '0';
else
d_req_prev <= d_req_i;
case state is
when IDLE =>
-- case 1: escape the escape character sent as normal character
if(d_i = g_escape_code and d_valid_i = '1' and d_escape_i = '0') then
state <= INSERT_ESCAPE;
d_prev <= x"0000";
-- case 2: send an escaped character
elsif(d_escape_i = '1' and d_valid_i = '1') then
state <= INSERT_ESCAPE;
d_prev <= d_i;
end if;
when INSERT_ESCAPE =>
if(d_req_prev = '1') then
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
end behavioral;
rtl/streamers/rx_streamer.vhd 0 → 100644
View file @ 1bd30289
-- see xrx_streamer.vhd for port documentation
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
entity rx_streamer is
generic (
g_data_width : integer := 32;
g_buffer_size : integer := 128;
g_filter_remote_mac : boolean := false
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Endpoint/WRC interface
snk_dat_i : in std_logic_vector(15 downto 0);
snk_adr_i : in std_logic_vector(1 downto 0);
snk_sel_i : in std_logic_vector(1 downto 0);
snk_cyc_i : in std_logic;
snk_stb_i : in std_logic;
snk_we_i : in std_logic;
snk_stall_o : out std_logic;
snk_ack_o : out std_logic;
snk_err_o : out std_logic;
snk_rty_o : out std_logic;
clk_ref_i : in std_logic := '0';
tm_time_valid_i : in std_logic := '0';
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
rx_first_o : out std_logic;
rx_last_o : out std_logic;
rx_data_o : out std_logic_vector(g_data_width-1 downto 0);
rx_valid_o : out std_logic;
rx_dreq_i : in std_logic;
rx_lost_o : out std_logic := '0';
rx_latency_o : out std_logic_vector(27 downto 0);
rx_latency_valid_o : out std_logic;
cfg_mac_local_i : in std_logic_vector(47 downto 0);
cfg_mac_remote_i : in std_logic_vector(47 downto 0);
cfg_ethertype_i : in std_logic_vector(15 downto 0) := x"dbff";
cfg_accept_broadcasts_i : in std_logic := '1'
);
end rx_streamer;
architecture wrapper of rx_streamer is
component xrx_streamer
generic (
g_data_width : integer;
g_buffer_size : integer;
g_filter_remote_mac : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
clk_ref_i : in std_logic := '0';
tm_time_valid_i : in std_logic := '0';
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
rx_first_o : out std_logic;
rx_last_o : out std_logic;
rx_data_o : out std_logic_vector(g_data_width-1 downto 0);
rx_valid_o : out std_logic;
rx_dreq_i : in std_logic;
rx_lost_o : out std_logic := '0';
rx_latency_o : out std_logic_vector(27 downto 0);
rx_latency_valid_o : out std_logic;
cfg_mac_local_i : in std_logic_vector(47 downto 0);
cfg_mac_remote_i : in std_logic_vector(47 downto 0);
cfg_ethertype_i : in std_logic_vector(15 downto 0) := x"dbff";
cfg_accept_broadcasts_i : in std_logic := '1');
end component;
signal snk_in : t_wrf_sink_in;
signal snk_out : t_wrf_sink_out;
begin -- rtl
U_Wrapped_Streamer : xrx_streamer
generic map (
g_data_width => g_data_width,
g_filter_remote_mac => g_filter_remote_mac,
g_buffer_size => g_buffer_size)
port map (
clk_sys_i => clk_sys_i,
clk_ref_i => clk_ref_i,
tm_tai_i => tm_tai_i,
tm_time_valid_i => tm_time_valid_i,
tm_cycles_i => tm_cycles_i,
rst_n_i => rst_n_i,
snk_i => snk_in,
snk_o => snk_out,
rx_data_o => rx_data_o,
rx_valid_o => rx_valid_o,
rx_dreq_i => rx_dreq_i,
rx_lost_o => rx_lost_o,
rx_first_o => rx_first_o,
rx_last_o => rx_last_o,
rx_latency_valid_o => rx_latency_valid_o,
rx_latency_o => rx_latency_o,
cfg_mac_local_i => cfg_mac_local_i,
cfg_mac_remote_i => cfg_mac_remote_i,
cfg_ethertype_i => cfg_ethertype_i,
cfg_accept_broadcasts_i => cfg_accept_broadcasts_i);
snk_in.dat <= snk_dat_i;
snk_in.adr <= snk_adr_i;
snk_in.sel <= snk_sel_i;
snk_in.cyc <= snk_cyc_i;
snk_in.stb <= snk_stb_i;
snk_in.we <= snk_we_i;
snk_stall_o <= snk_out.stall;
snk_ack_o <= snk_out.ack;
snk_err_o <= snk_out.err;
snk_rty_o <= snk_out.rty;
end wrapper;
rtl/streamers/streamers_pkg.vhd 0 → 100644
View file @ 1bd30289
library ieee;
use ieee.std_logic_1164.all;
use work.wr_fabric_pkg.all;
package streamers_pkg is
component xtx_streamer
generic (
g_data_width : integer := 32;
g_tx_threshold : integer := 16;
g_tx_max_words_per_frame : integer := 128;
g_tx_timeout : integer := 128);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
clk_ref_i : in std_logic := '0';
tm_time_valid_i : in std_logic := '0';
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
tx_data_i : in std_logic_vector(g_data_width-1 downto 0);
tx_valid_i : in std_logic;
tx_dreq_o : out std_logic;
tx_last_i : in std_logic := '1';
tx_flush_i : in std_logic := '0';
tx_reset_seq_i : in std_logic := '0';
cfg_mac_local_i : in std_logic_vector(47 downto 0) := x"000000000000";
cfg_mac_target_i : in std_logic_vector(47 downto 0);
cfg_ethertype_i : in std_logic_vector(15 downto 0) := x"dbff");
end component;
component xrx_streamer
generic (
g_data_width : integer := 32;
g_buffer_size : integer := 16;
g_filter_remote_mac : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
clk_ref_i : in std_logic := '0';
tm_time_valid_i : in std_logic := '0';
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
rx_first_o : out std_logic;
rx_last_o : out std_logic;
rx_data_o : out std_logic_vector(g_data_width-1 downto 0);
rx_valid_o : out std_logic;
rx_dreq_i : in std_logic;
rx_lost_o : out std_logic := '0';
rx_latency_o : out std_logic_vector(27 downto 0);
rx_latency_valid_o : out std_logic;
cfg_mac_local_i : in std_logic_vector(47 downto 0) := x"000000000000";
cfg_mac_remote_i : in std_logic_vector(47 downto 0) := x"000000000000";
cfg_ethertype_i : in std_logic_vector(15 downto 0) := x"dbff";
cfg_accept_broadcasts_i : in std_logic := '1');
end component;
end streamers_pkg;
rtl/streamers/tx_streamer.vhd 0 → 100644
View file @ 1bd30289
-- see xtx_streamer.vhd for comments
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.streamers_pkg.all;
entity tx_streamer is
generic (
g_data_width : integer := 32;
g_tx_threshold : integer := 16;
g_tx_max_words_per_frame : integer := 128;
g_tx_timeout : integer := 1024
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Endpoint/WRC interface
src_dat_o : out std_logic_vector(15 downto 0);
src_adr_o : out std_logic_vector(1 downto 0);
src_sel_o : out std_logic_vector(1 downto 0);
src_cyc_o : out std_logic;
src_stb_o : out std_logic;
src_we_o : out std_logic;
src_stall_i : in std_logic;
src_ack_i : in std_logic;
src_err_i : in std_logic;
clk_ref_i : in std_logic := '0';
tm_time_valid_i : in std_logic := '0';
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
tx_flush_i : in std_logic := '0';
tx_last_i : in std_logic := '1';
tx_data_i : in std_logic_vector(g_data_width-1 downto 0);
tx_reset_seq_i : in std_logic := '0';
tx_valid_i : in std_logic;
tx_dreq_o : out std_logic;
-- MAC address
cfg_mac_local_i : in std_logic_vector(47 downto 0) := x"000000000000";
cfg_mac_target_i : in std_logic_vector(47 downto 0) := x"ffffffffffff";
cfg_ethertype_i : in std_logic_vector(15 downto 0) := x"dbff"
);
end tx_streamer;
architecture rtl of tx_streamer is
signal src_in : t_wrf_source_in;
signal src_out : t_wrf_source_out;
begin -- rtl
U_Wrapped_Streamer : xtx_streamer
generic map (
g_data_width => g_data_width,
g_tx_threshold => g_tx_threshold,
g_tx_max_words_per_frame => g_tx_max_words_per_frame,
g_tx_timeout => g_tx_timeout)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
src_i => src_in,
src_o => src_out,
tx_last_i => tx_last_i,
tx_data_i => tx_data_i,
tx_reset_seq_i => tx_reset_seq_i,
tx_valid_i => tx_valid_i,
tx_dreq_o => tx_dreq_o,
tx_flush_i => tx_flush_i,
clk_ref_i => clk_ref_i,
tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_tai_i,
tm_cycles_i => tm_cycles_i,
cfg_mac_local_i => cfg_mac_local_i,
cfg_mac_target_i => cfg_mac_target_i,
cfg_ethertype_i => cfg_ethertype_i);
src_adr_o <= src_out.adr;
src_dat_o <= src_out.dat;
src_sel_o <= src_out.sel;
src_stb_o <= src_out.stb;
src_we_o <= src_out.we;
src_cyc_o <= src_out.cyc;
src_in.ack <= src_ack_i;
src_in.stall <= src_stall_i;
src_in.err <= src_err_i;
end rtl;
rtl/streamers/xrx_streamer.vhd 0 → 100644
View file @ 1bd30289
-------------------------------------------------------------------------------
-- Title : Simple Ethernet Data Streamer
-- Project : White Rabbit Hands-On Course
-------------------------------------------------------------------------------
-- File : xrx_streamer.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-11-02
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: A simple core demonstrating how to encapsulate a continuous
-- stream of data words into Ethernet frames, in a format that is accepted by
-- the White Rabbit PTP core. This core decodes Ethernet frames encoded by
-- xtx_streamer. More info in the documentation.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CERN BE-CO-HT.
-- Licensed under LGPL 2.1.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity xrx_streamer is
generic (
-- Width of the data words. Must be same as in the TX streamer.
g_data_width : integer := 32;
-- Size of RX buffer, in data words.
g_buffer_size : integer := 16;
-- When true, receives only packets whose destination MAC equals
-- cfg_mac_remote_i. When false. accepts all incoming packets.
g_filter_remote_mac : boolean := false
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Endpoint/WRC interface
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
---------------------------------------------------------------------------
-- WRC Timing interface, used for latency measurement
-- Caution: uses clk_ref_i clock domain!
---------------------------------------------------------------------------
-- White Rabbit reference clock
clk_ref_i : in std_logic := '0';
-- Time valid flag
tm_time_valid_i : in std_logic := '0';
-- TAI seconds
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
-- Fractional part of the second (in clk_ref_i cycles)
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
---------------------------------------------------------------------------
-- User interface
---------------------------------------------------------------------------
-- 1 indicates the 1st word of the data block on rx_data_o.
rx_first_o : out std_logic;
-- 1 indicates the last word of the data block on rx_data_o.
rx_last_o : out std_logic;
-- Received data.
rx_data_o : out std_logic_vector(g_data_width-1 downto 0);
-- 1 indicted that rx_data_o is outputting a valid data word.
rx_valid_o : out std_logic;
-- Synchronous data request input: when 1, the streamer may output another
-- data word in the subsequent clock cycle.
rx_dreq_i : in std_logic;
-- Lost output: 1 indicates that one or more of frames have been lost.
rx_lost_o : out std_logic := '0';
-- Latency measurement output: indicates the transport latency (between the
-- TX streamer in remote device and this streamer), in clk_ref_i clock cycles.
rx_latency_o : out std_logic_vector(27 downto 0);
-- 1 when the latency on rx_latency_o is valid.
rx_latency_valid_o : out std_logic;
-- MAC address
cfg_mac_local_i : in std_logic_vector(47 downto 0);
cfg_mac_remote_i : in std_logic_vector(47 downto 0);
cfg_ethertype_i : in std_logic_vector(15 downto 0) := x"dbff";
-- 1: accept all broadcast packets
-- 0: accept only unicasts
cfg_accept_broadcasts_i : in std_logic := '1'
);
end xrx_streamer;
architecture rtl of xrx_streamer is
type t_pipe is record
dvalid : std_logic;
dreq : std_logic;
sof : std_logic;
eof : std_logic;
error : std_logic;
data : std_logic_vector(15 downto 0);
addr : std_logic_vector(1 downto 0);
bytesel : std_logic;
end record;
component escape_detector
generic (
g_data_width : integer;
g_escape_code : std_logic_vector);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
d_detect_enable_i : in std_logic;
d_valid_i : in std_logic;
d_req_o : out std_logic;
d_o : out std_logic_vector(g_data_width-1 downto 0);
d_escape_o : out std_logic;
d_valid_o : out std_logic;
d_req_i : in std_logic);
end component;
component dropping_buffer
generic (
g_size : integer;
g_data_width : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
d_req_o : out std_logic;
d_drop_i : in std_logic;
d_accept_i : in std_logic;
d_valid_i : in std_logic;
d_o : out std_logic_vector(g_data_width-1 downto 0);
d_valid_o : out std_logic;
d_req_i : in std_logic);
end component;
component pulse_stamper
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
pulse_a_i : in std_logic;
tm_time_valid_i : in std_logic;
tm_tai_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
tag_tai_o : out std_logic_vector(39 downto 0);
tag_cycles_o : out std_logic_vector(27 downto 0);
tag_valid_o : out std_logic);
end component;
component xwb_fabric_sink
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic);
end component;
type t_rx_state is (IDLE, HEADER, PAYLOAD, SUBFRAME_HEADER, EOF);
signal fab, fsm_in : t_pipe;
signal state : t_rx_state;
signal count, ser_count : unsigned(3 downto 0);
signal seq_no, seq_new : unsigned(14 downto 0);
signal crc_match, crc_en, crc_en_masked, crc_restart : std_logic;
signal detect_escapes, is_escape : std_logic;
signal rx_pending : std_logic;
signal pack_data, fifo_data : std_logic_vector(g_data_width-1 downto 0);
signal fifo_drop, fifo_accept, fifo_accept_d0, fifo_dvalid : std_logic;
signal fifo_sync, fifo_last, fifo_lost : std_logic;
signal fifo_dout, fifo_din : std_logic_vector(g_data_width + 2 downto 0);
signal pending_write, fab_dvalid_pre : std_logic;
signal tx_tag_cycles, rx_tag_cycles : std_logic_vector(27 downto 0);
signal tx_tag_valid, rx_tag_valid : std_logic;
signal got_next_subframe : std_logic;
begin -- rtl
U_rx_crc_generator : gc_crc_gen
generic map (
g_polynomial => x"1021",
g_init_value => x"ffff",
g_residue => x"470f",
g_data_width => 16,
g_sync_reset => 1,
g_dual_width => 0,
g_registered_match_output => true)
port map (
clk_i => clk_sys_i,
rst_i => '0',
restart_i => crc_restart,
en_i => crc_en_masked,
data_i => fsm_in.data,
half_i => '0',
match_o => crc_match);
crc_en_masked <= crc_en and fsm_in.dvalid;
U_Fabric_Sink : xwb_fabric_sink
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
snk_i => snk_i,
snk_o => snk_o,
addr_o => fab.addr,
data_o => fab.data,
dvalid_o => fab_dvalid_pre,
sof_o => fab.sof,
eof_o => fab.eof,
error_o => fab.error,
bytesel_o => fab.bytesel,
dreq_i => fab.dreq);
fab.dvalid <= '1' when fab_dvalid_pre = '1' and fab.addr = c_WRF_DATA and fab.bytesel = '0' else '0';
U_Escape_Detect : escape_detector
generic map (
g_data_width => 16,
g_escape_code => x"cafe")
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
d_i => fab.data,
d_detect_enable_i => detect_escapes,
d_valid_i => fab.dvalid,
d_req_o => fab.dreq,
d_o => fsm_in.data,
d_escape_o => is_escape,
d_valid_o => fsm_in.dvalid,
d_req_i => fsm_in.dreq);
fsm_in.eof <= fab.eof or fab.error;
fsm_in.sof <= fab.sof;
U_Output_FIFO : dropping_buffer
generic map (
g_size => g_buffer_size,
g_data_width => g_data_width + 3)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
d_i => fifo_din,
d_req_o => fsm_in.dreq,
d_drop_i => fifo_drop,
d_accept_i => fifo_accept_d0,
d_valid_i => fifo_dvalid,
d_o => fifo_dout,
d_valid_o => rx_valid_o,
d_req_i => rx_dreq_i);
fifo_din(g_data_width+1) <= fifo_sync;
fifo_din(g_data_width) <= fifo_last;
fifo_din(g_data_width-1 downto 0) <= fifo_data;
rx_data_o <= fifo_dout(g_data_width-1 downto 0);
rx_first_o <= fifo_dout(g_data_width+1);
rx_last_o <= fifo_dout(g_data_width);
U_RX_Timestamper : pulse_stamper
port map (
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
pulse_a_i => fsm_in.sof,
tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_tai_i,
tm_cycles_i => tm_cycles_i,
tag_cycles_o => rx_tag_cycles);
p_fsm : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= IDLE;
count <= (others => '0');
seq_no <= (others => '0');
else
case state is
when IDLE =>
detect_escapes <= '0';
crc_en <= '0';
count <= (others => '0');
fifo_accept <= '0';
fifo_drop <= '0';
fifo_dvalid <= '0';
pending_write <= '0';
rx_latency_valid_o <= '0';
tx_tag_valid <= '0';
if(fsm_in.sof = '1') then
state <= HEADER;
end if;
when HEADER =>
if(fsm_in.eof = '1') then
state <= IDLE;
elsif(fsm_in.dvalid = '1') then
case count is
when x"0" =>
if(fsm_in.data /= cfg_mac_local_i(47 downto 32) nor (cfg_accept_broadcasts_i = '1' and fsm_in.data /= x"ffff")) then
state <= IDLE;
end if;
when x"1" =>
if(fsm_in.data /= cfg_mac_local_i(31 downto 16) nor (cfg_accept_broadcasts_i = '1' and fsm_in.data /= x"ffff")) then
state <= IDLE;
end if;
when x"2" =>
if(fsm_in.data /= cfg_mac_local_i(15 downto 0) nor (cfg_accept_broadcasts_i = '1' and fsm_in.data /= x"ffff")) then
state <= IDLE;
end if;
when x"3" =>
if(fsm_in.data /= cfg_mac_remote_i(47 downto 32) and g_filter_remote_mac) then
state <= IDLE;
end if;
when x"4" =>
if(fsm_in.data /= cfg_mac_remote_i(31 downto 16) and g_filter_remote_mac) then
state <= IDLE;
end if;
when x"5" =>
if(fsm_in.data /= cfg_mac_remote_i(15 downto 0) and g_filter_remote_mac) then
state <= IDLE;
end if;
when x"6" =>
if(fsm_in.data /= cfg_ethertype_i) then
state <= IDLE;
end if;
when x"7" =>
tx_tag_valid <= fsm_in.data(15);
tx_tag_cycles(27 downto 16) <= fsm_in.data(11 downto 0);
when x"8" =>
tx_tag_cycles(15 downto 0) <= fsm_in.data;
crc_en <= '1';
detect_escapes <= '1';
state <= SUBFRAME_HEADER;
when others => null;
end case;
count <= count + 1;
end if;
when SUBFRAME_HEADER =>
fifo_drop <= '0';
fifo_accept <= '0';
ser_count <= (others => '0');
if(tx_tag_valid = '1') then
rx_latency_valid_o <= '1';
if(unsigned(tx_tag_cycles) > unsigned(rx_tag_cycles)) then
rx_latency_o <= std_logic_vector(unsigned(rx_tag_cycles) - unsigned(tx_tag_cycles) + to_unsigned(125000000, 28));
else
rx_latency_o <= std_logic_vector(unsigned(rx_tag_cycles) - unsigned(tx_tag_cycles));
end if;
tx_tag_valid <= '0';
else
rx_latency_valid_o <= '0';
end if;
if(fsm_in.eof = '1') then
state <= IDLE;
elsif (fsm_in.dvalid = '1' and is_escape = '1') then
got_next_subframe <= '1';
if(std_logic_vector(seq_no) /= fsm_in.data(14 downto 0)) then
seq_no <= unsigned(fsm_in.data(14 downto 0));
fifo_lost <= '1';
else
seq_no <= unsigned(seq_no + 1);
fifo_lost <= '0';
end if;
state <= PAYLOAD;
end if;
when PAYLOAD =>
fifo_sync <= got_next_subframe;
if(fsm_in.eof = '1') then
state <= IDLE;
fifo_drop <= '1';
fifo_accept <= '0';
got_next_subframe <= '0';
elsif(fsm_in.dvalid = '1') then
if(is_escape = '1') then
ser_count <= (others => '0');
fifo_last <= '1';
got_next_subframe <= '1';
if(fsm_in.data(15) = '1') then
if(std_logic_vector(seq_no) /= fsm_in.data(14 downto 0)) then
seq_no <= unsigned(fsm_in.data(14 downto 0));
fifo_lost <= '1';
else
seq_no <= unsigned(seq_no + 1);
fifo_lost <= '0';
end if;
state <= PAYLOAD;
fifo_accept <= crc_match; --_latched;
fifo_drop <= not crc_match; --_latched;
fifo_dvalid <= pending_write and not fifo_dvalid;
pending_write <= '0';
elsif fsm_in.data = x"0bad" then
state <= EOF;
fifo_accept <= crc_match; --_latched;
fifo_drop <= not crc_match; --_latched;
fifo_dvalid <= pending_write and not fifo_dvalid;
else
state <= EOF;
fifo_drop <= '1';
fifo_accept <= '0';
end if;
-- fifo_dvalid <= '0';
else
fifo_last <= '0';
fifo_accept <= '0';
fifo_drop <= '0';
pack_data(to_integer(ser_count) * 16 + 15 downto to_integer(ser_count) * 16) <= fsm_in.data;
if(ser_count = g_data_width/16 - 1) then
ser_count <= (others => '0');
pending_write <= '1';
fifo_data(g_data_width-16-1 downto 0) <= pack_data(g_data_width-16-1 downto 0);
fifo_data(g_data_width-1 downto g_data_width-16) <= fsm_in.data;
fifo_dvalid <= '0';
elsif(ser_count = g_data_width/16-2 and pending_write = '1') then
pending_write <= '0';
ser_count <= ser_count + 1;
fifo_dvalid <= '1';
fifo_sync <= got_next_subframe;
got_next_subframe <= '0';
else
ser_count <= ser_count + 1;
fifo_dvalid <= '0';
end if;
end if;
else
fifo_dvalid <= '0';
end if;
if(fifo_dvalid = '1') then
fifo_sync <= '0';
end if;
when EOF =>
fifo_dvalid <= '0';
fifo_drop <= '0';
fifo_accept <= '0';
state <= IDLE;
end case;
end if;
end if;
end process;
p_delay_fifo_accept : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
fifo_accept_d0 <= fifo_accept;
end if;
end process;
-- fifo_data <= pack_data;
crc_restart <= '1' when (is_escape = '1' and fsm_in.data(15) = '1') else '0';
end rtl;
rtl/streamers/xtx_streamer.vhd 0 → 100644
View file @ 1bd30289
-------------------------------------------------------------------------------
-- Title : Simple Ethernet Data Streamer
-- Project : White Rabbit Hands-On Course
-------------------------------------------------------------------------------
-- File : xtx_streamer.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-11-02
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: A simple core demonstrating how to encapsulate a continuous
-- stream of data words into Ethernet frames, in a format that is accepted by
-- the White Rabbit PTP core. More info in the documentation.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CERN BE-CO-HT.
-- Licensed under LGPL 2.1.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity xtx_streamer is
generic (
-- Width of data words on tx_data_i.
g_data_width : integer := 32;
-- Minimum number of data words in the TX buffer that will trigger transmission of an
-- Ethernet frame. Also defines the buffer size (2 * g_tx_threshold). Note
-- that in order for a frame to be transmitted, the buffer must conatain at
-- least one complete block.
g_tx_threshold : integer := 128;
-- Maximum number of data words in a single Ethernet frame. It also defines
-- the maximum block size (since blocks can't be currently split across
-- multiple frames).
g_tx_max_words_per_frame : integer := 128;
-- Transmission timeout (in clk_sys_i cycles), after which the contents
-- of TX buffer are sent regardless of the amount of data that is currently
-- stored in the buffer, so that data in the buffer does not get stuck.
g_tx_timeout : integer := 1024
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Endpoint/WRC interface - packet source
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
---------------------------------------------------------------------------
-- WRC Timing interface, used for latency measurement
-- Caution: uses clk_ref_i clock domain!
---------------------------------------------------------------------------
-- White Rabbit reference clock
clk_ref_i : in std_logic := '0';
-- Time valid flag
tm_time_valid_i : in std_logic := '0';
-- TAI seconds
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
-- Fractional part of the second (in clk_ref_i cycles)
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
---------------------------------------------------------------------------
-- User interface
---------------------------------------------------------------------------
-- Data word to be sent.
tx_data_i : in std_logic_vector(g_data_width-1 downto 0);
-- 1 indicates that the tx_data_i contains a valid data word.
tx_valid_i : in std_logic;
-- Synchronous data request: if active, the user may send a data word in
-- the following clock cycle.
tx_dreq_o : out std_logic;
-- Last signal. Can be used to indicate the last data word in a larger
-- block of samples (see documentation for more details).
tx_last_i : in std_logic := '1';
-- Flush input. When asserted, the streamer will immediatly send out all
-- the data that is stored in its TX buffer, ignoring g_tx_timeout.
tx_flush_i : in std_logic := '0';
-- Reset sequence number. When asserted, the internal sequence number
-- generator used to detect loss of frames is reset to 0. Advanced feature.
tx_reset_seq_i : in std_logic := '0';
---------------------------------------------------------------------------
-- Configuration
---------------------------------------------------------------------------
-- Local MAC address. Leave at 0 when using with the WR MAC/Core, it will
-- insert its own source MAC.
cfg_mac_local_i : in std_logic_vector(47 downto 0) := x"000000000000";
-- Destination MAC address.
cfg_mac_target_i : in std_logic_vector(47 downto 0);
-- Ethertype of our frames. Default value is accepted by standard
-- configuration of the WR PTP Core
cfg_ethertype_i : in std_logic_vector(15 downto 0) := x"dbff"
);
end xtx_streamer;
architecture rtl of xtx_streamer is
type t_pipe is record
dvalid : std_logic;
dreq : std_logic;
sof : std_logic;
eof : std_logic;
error : std_logic;
data : std_logic_vector(15 downto 0);
end record;
component xwb_fabric_source
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
addr_i : in std_logic_vector(1 downto 0);
data_i : in std_logic_vector(15 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic;
dreq_o : out std_logic);
end component;
component gc_escape_inserter
generic (
g_data_width : integer;
g_escape_code : std_logic_vector);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
d_insert_enable_i : in std_logic;
d_escape_i : in std_logic;
d_valid_i : in std_logic;
d_req_o : out std_logic;
d_o : out std_logic_vector (g_data_width-1 downto 0);
d_valid_o : out std_logic;
d_req_i : in std_logic);
end component;
component pulse_stamper
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
pulse_a_i : in std_logic;
tm_time_valid_i : in std_logic;
tm_tai_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
tag_tai_o : out std_logic_vector(39 downto 0);
tag_cycles_o : out std_logic_vector(27 downto 0);
tag_valid_o : out std_logic);
end component;
type t_tx_state is (IDLE, SOF, ETH_HEADER, SUBFRAME_HEADER, PAYLOAD, CRC_WORD, PADDING, EOF);
constant c_min_packet_size : integer := 32;
signal tx_threshold_hit : std_logic;
signal tx_timeout_hit : std_logic;
signal tx_flush_latched : std_logic;
signal tx_fifo_last, tx_fifo_we, tx_fifo_full, tx_fifo_empty, tx_fifo_rd : std_logic;
signal tx_fifo_q, tx_fifo_d : std_logic_vector(g_data_width downto 0);
signal tx_fifo_valid : std_logic;
signal state : t_tx_state;
signal seq_no : unsigned(14 downto 0);
signal count, ser_count : unsigned(7 downto 0);
signal total_words : unsigned(10 downto 0);
signal timeout_counter : unsigned(11 downto 0);
signal pack_data : std_logic_vector(15 downto 0);
signal fsm_out, escaper, fab_src : t_pipe;
signal fsm_escape, fsm_escape_enable : std_logic;
signal crc_en, crc_en_masked, crc_reset : std_logic;
signal crc_value : std_logic_vector(15 downto 0);
signal tx_almost_empty, tx_almost_full : std_logic;
signal buf_frame_count : unsigned(5 downto 0) := (others => '0');
signal tag_cycles : std_logic_vector(27 downto 0);
signal tag_valid, tag_valid_latched : std_logic;
signal reset_dly : std_logic;
begin -- rtl
U_tx_crc_generator : gc_crc_gen
generic map (
g_polynomial => x"1021",
g_init_value => x"ffff",
g_residue => x"0000",
g_data_width => 16,
g_sync_reset => 1,
g_dual_width => 0,
g_registered_match_output => false,
g_registered_crc_output => false)
port map (
clk_i => clk_sys_i,
rst_i => crc_reset,
en_i => crc_en_masked,
data_i => fsm_out.data,
half_i => '0',
crc_o => crc_value);
crc_en_masked <= crc_en and fsm_out.dvalid;
U_Fab_Source : xwb_fabric_source
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
src_i => src_i,
src_o => src_o,
addr_i => c_WRF_DATA,
data_i => fab_src.data,
dvalid_i => fab_src.dvalid,
sof_i => fab_src.sof,
eof_i => fab_src.eof,
error_i => '0',
bytesel_i => '0',
dreq_o => fab_src.dreq);
fab_src.sof <= fsm_out.sof;
fab_src.eof <= fsm_out.eof;
U_Insert_Escape : gc_escape_inserter
generic map (
g_data_width => 16,
g_escape_code => x"cafe")
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
d_i => fsm_out.data,
d_insert_enable_i => fsm_escape_enable,
d_escape_i => fsm_escape,
d_valid_i => fsm_out.dvalid,
d_req_o => fsm_out.dreq,
d_o => fab_src.data,
d_valid_o => fab_src.dvalid,
d_req_i => fab_src.dreq);
tx_fifo_we <= tx_valid_i and not tx_fifo_full;
tx_fifo_d <= tx_last_i & tx_data_i;
U_TX_Buffer : generic_sync_fifo
generic map (
g_data_width => g_data_width + 1,
g_size => 2 * g_tx_threshold,
g_with_almost_full => true,
g_with_almost_empty => true,
g_almost_empty_threshold => g_tx_threshold,
g_almost_full_threshold => 2*g_tx_threshold - 2,
g_show_ahead => true)
port map (
rst_n_i => rst_n_i,
clk_i => clk_sys_i,
d_i => tx_fifo_d,
we_i => tx_fifo_we,
q_o => tx_fifo_q,
rd_i => tx_fifo_rd,
empty_o => tx_fifo_empty,
full_o => tx_fifo_full,
almost_empty_o => tx_almost_empty,
almost_full_o => tx_almost_full
);
tx_threshold_hit <= '1' when tx_almost_empty = '0' and (buf_frame_count /= 0) else '0';
tx_fifo_last <= tx_fifo_q(g_data_width);
U_Timestamper : pulse_stamper
port map (
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
pulse_a_i => fsm_out.sof,
tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_tai_i,
tm_cycles_i => tm_cycles_i,
tag_tai_o => open,
tag_cycles_o => tag_cycles,
tag_valid_o => tag_valid);
p_latch_tx_tag : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' or state = IDLE then
tag_valid_latched <= '0';
elsif(tag_valid = '1') then
tag_valid_latched <= '1';
end if;
end if;
end process;
p_frame_counter : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
buf_frame_count <= (others => '0');
else
if(tx_fifo_we = '1' and tx_last_i = '1' and (tx_fifo_rd = '0' or tx_fifo_last = '0')) then
buf_frame_count <= buf_frame_count+ 1;
elsif((tx_fifo_we = '0' or tx_last_i = '0') and (tx_fifo_rd = '1' and tx_fifo_last = '1')) then
buf_frame_count <= buf_frame_count - 1;
end if;
end if;
end if;
end process;
p_tx_fifo_valid : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
tx_fifo_valid <= '0';
else
tx_fifo_valid <= tx_fifo_rd and not tx_fifo_empty;
end if;
end if;
end process;
p_tx_timeout : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
timeout_counter <= (others => '0');
tx_timeout_hit <= '0';
else
if(tx_fifo_empty = '0' and tx_threshold_hit = '0') then
timeout_counter <= timeout_counter + 1;
else
timeout_counter <= (others => '0');
end if;
if(timeout_counter = g_tx_timeout) then
tx_timeout_hit <= '1';
else
tx_timeout_hit <= '0';
end if;
end if;
end if;
end process;
p_latch_tx_flush : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
tx_flush_latched <= '0';
else
if(state = IDLE) then
tx_flush_latched <= tx_flush_i or tx_timeout_hit;
else
tx_flush_latched <= '0';
end if;
end if;
end if;
end process;
p_fsm : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= IDLE;
fsm_out.sof <= '0';
fsm_out.eof <= '0';
fsm_out.dvalid <= '0';
count <= (others => '0');
seq_no <= (others => '0');
-- tx_fifo_rd <= '0';
crc_reset <= '1';
else
if(tx_reset_seq_i = '1') then
seq_no <= (others => '0');
end if;
case state is
when IDLE =>
crc_en <= '0';
crc_reset <= '0';
fsm_out.eof <= '0';
if(fsm_out.dreq = '1' and (tx_flush_latched = '1' or tx_flush_i = '1' or tx_threshold_hit = '1')) then
state <= SOF;
fsm_out.sof <= '1';
end if;
fsm_escape_enable <= '0';
fsm_escape <= '0';
when SOF =>
fsm_out.sof <= '0';
ser_count <= (others => '0');
state <= ETH_HEADER;
count <= (others => '0');
when ETH_HEADER =>
if(fsm_out.dreq = '1') then
case count is
when x"00" =>
fsm_out.data <= cfg_mac_target_i(47 downto 32);
count <= count + 1;
when x"01" =>
fsm_out.data <= cfg_mac_target_i(31 downto 16);
count <= count + 1;
when x"02" =>
fsm_out.data <= cfg_mac_target_i(15 downto 0);
count <= count + 1;
when x"03" =>
fsm_out.data <= cfg_mac_local_i(47 downto 32);
count <= count + 1;
when x"04" =>
fsm_out.data <= cfg_mac_local_i(31 downto 16);
count <= count + 1;
when x"05" =>
fsm_out.data <= cfg_mac_local_i(15 downto 0);
count <= count + 1;
when x"06" =>
fsm_out.data <= cfg_ethertype_i;
count <= count + 1;
when x"07" =>
fsm_out.data <= tag_valid_latched & "000" & tag_cycles(27 downto 16);
count <= count + 1;
when x"08" =>
fsm_out.data <= tag_cycles(15 downto 0);
count <= (others => '0');
state <= SUBFRAME_HEADER;
when others =>
fsm_out.data <= (others => 'X');
count <= (others => 'X');
end case;
fsm_out.dvalid <= '1';
else
fsm_out.dvalid <= '0';
end if;
when SUBFRAME_HEADER =>
crc_en <= '1';
crc_reset <= '0';
if(fsm_out.dreq = '1') then
fsm_out.dvalid <= '1';
fsm_escape <= '1';
fsm_escape_enable <= '1';
fsm_out.data <= '1' & std_logic_vector(seq_no);
seq_no <= seq_no + 1;
state <= PAYLOAD;
else
fsm_out.dvalid <= '0';
fsm_out.data <= (others => 'X');
end if;
when PAYLOAD =>
fsm_escape <= '0';
if(fsm_out.dreq = '1') then
-- next subframe?
if(tx_fifo_empty = '1' or (ser_count = g_data_width/16-1 and tx_fifo_last = '1')) then
state <= CRC_WORD;
end if;
if(ser_count = g_data_width/16-1) then
count <= count + 1;
ser_count <= (others => '0');
else
ser_count <= ser_count + 1;
end if;
fsm_out.data <= tx_fifo_q((to_integer(ser_count) + 1)* 16 -1 downto to_integer(ser_count) * 16);
fsm_out.dvalid <= not tx_fifo_empty;
else
fsm_out.data <= (others => 'X');
fsm_out.dvalid <= '0';
end if;
when CRC_WORD =>
crc_en <= '0';
ser_count <= (others => '0');
if(fsm_out.dreq = '1') then
fsm_out.dvalid <= '1';
fsm_out.data <= crc_value;
crc_reset <= '1';
if(tx_fifo_empty = '1' or count >= g_tx_max_words_per_frame) then
state <= PADDING;
else
state <= SUBFRAME_HEADER;
end if;
end if;
when PADDING =>
if(fsm_out.dreq = '1') then
fsm_escape <= '1';
fsm_out.dvalid <= '1';
fsm_out.data <= x"0bad";
if(total_words >= c_min_packet_size) then
state <= EOF;
end if;
else
fsm_out.dvalid <= '0';
fsm_out.data <= (others => 'X');
end if;
when EOF =>
fsm_out.dvalid <= '0';
if(fsm_out.dreq = '1') then
fsm_out.eof <= '1';
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
p_count_words : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if fsm_out.sof = '1' then
total_words <= (others => '0');
elsif fsm_out.dvalid = '1' then
total_words <= total_words +1;
end if;
end if;
end process;
p_comb_fx_fifo_read : process(state, fsm_out, ser_count)
begin
if(state = PAYLOAD and ser_count = g_data_width/16-1 and fsm_out.dreq = '1' and tx_fifo_empty = '0') then
tx_fifo_rd <= '1';
else
tx_fifo_rd <= '0';
end if;
end process;
p_delay_reset: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
reset_dly <= rst_n_i;
end if;
end process;
tx_dreq_o <= (not tx_almost_full) and reset_dly;
end rtl;
rtl/timestamp_adder.vhd 0 → 100644
View file @ 1bd30289
-------------------------------------------------------------------------------
-- Title : Pipelined timestamp adder with normalization
-- Project : Fine Delay Core (FmcDelay1ns4cha)
-------------------------------------------------------------------------------
-- File : fd_ts_adder.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-29
-- Last update: 2013-03-13
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Pipelined timestamp adder with re-normalization of the result.
-- Adds a to b, producing normalized timestamp q. A timestmap is normalized when
-- the 0 <= frac < 2**g_frac_bits, 0 <= coarse <= g_coarse_range-1 and utc >= 0.
-- For correct operation of renormalizer, input timestamps must meet the
-- following constraints:
-- 1. 0 <= (a/b)_frac_i <= 2**g_frac_bits-1
-- 2. -g_coarse_range+1 <= (a_coarse_i + b_coarse_i) <= 3*g_coarse_range-1
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN / BE-CO-HT
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-08-29 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timestamp_adder is
generic
(
-- sizes of the respective bitfields of the input/output timestamps
g_frac_bits : integer := 12;
g_cycles_bits : integer := 28;
g_tai_bits : integer := 40;
-- upper bound of the coarse part
g_ref_clk_rate: integer := 125000000
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
valid_i : in std_logic; -- when HI, a_* and b_* contain valid timestamps
enable_i : in std_logic := '1'; -- pipeline enable
-- Input timestamps
a_tai_i : in std_logic_vector(g_tai_bits-1 downto 0);
a_cycles_i : in std_logic_vector(g_cycles_bits-1 downto 0);
a_frac_i : in std_logic_vector(g_frac_bits-1 downto 0) := (others => '0');
b_tai_i : in std_logic_vector(g_tai_bits-1 downto 0);
b_cycles_i : in std_logic_vector(g_cycles_bits-1 downto 0);
b_frac_i : in std_logic_vector(g_frac_bits-1 downto 0) := (others => '0');
-- Normalized sum output (valid when valid_o == 1)
valid_o : out std_logic;
q_tai_o : out std_logic_vector(g_tai_bits-1 downto 0);
q_cycles_o : out std_logic_vector(g_cycles_bits-1 downto 0);
q_frac_o : out std_logic_vector(g_frac_bits-1 downto 0)
);
end timestamp_adder;
architecture rtl of timestamp_adder is
constant c_NUM_PIPELINE_STAGES : integer := 4;
type t_internal_sum is record
utc : signed(g_tai_bits-1 downto 0);
coarse : signed(g_cycles_bits+1 downto 0);
frac : signed(g_frac_bits+1 downto 0);
end record;
type t_internal_sum_array is array (integer range <>) of t_internal_sum;
signal pipe : std_logic_vector(c_NUM_PIPELINE_STAGES-1 downto 0);
signal sums : t_internal_sum_array(0 to c_NUM_PIPELINE_STAGES-1);
signal ovf_frac : std_logic;
signal ovf_coarse : std_logic_vector(1 downto 0);
signal unf_coarse : std_logic;
begin -- rtl
-- Pipeline stage 0: just add the two timestamps field by field
p_stage0 : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pipe(0) <= '0';
elsif(enable_i = '1') then
pipe(0) <= valid_i;
sums(0).frac <= signed("00" & a_frac_i) + signed("00" & b_frac_i);
sums(0).coarse <= resize(signed(a_cycles_i), sums(0).coarse'length) +
resize(signed(b_cycles_i), sums(0).coarse'length);
sums(0).utc <= signed(a_tai_i) + signed(b_tai_i);
else
pipe(0) <= '0';
end if;
end if;
end process;
ovf_frac <= std_logic(sums(0).frac(g_frac_bits));
-- Pipeline stage 1: check the fractional sum for overflow and eventually adjust
-- the coarse sum
p_stage1 : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pipe(1) <= '0';
else
pipe(1) <= pipe(0);
if(ovf_frac = '1') then
sums(1).frac <= sums(0).frac - 2**g_frac_bits;
sums(1).coarse <= sums(0).coarse + 1;
else
sums(1).frac <= sums(0).frac;
sums(1).coarse <= sums(0).coarse;
end if;
sums(1).utc <= sums(0).utc;
end if;
end if;
end process;
-- Pipeline stage 2: check the coarse sum for under/overflows
p_stage2 : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pipe(2) <= '0';
else
sums(2) <= sums(1);
pipe(2) <= pipe(1);
if(sums(1).coarse < 0) then
unf_coarse <= '1';
ovf_coarse <= "00";
elsif(sums(1).coarse >= 2 * g_ref_clk_rate) then
ovf_coarse <= "10";
unf_coarse <= '0';
elsif(sums(1).coarse >= g_ref_clk_rate) then
ovf_coarse <= "01";
unf_coarse <= '0';
else
ovf_coarse <= "00";
unf_coarse <= '0';
end if;
end if;
end if;
end process;
-- Pipeline stage 3: adjust the coarse & UTC sums according to normalize the
-- previously detected under/overflows
p_stage3 : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pipe(3) <= '0';
else
pipe(3) <= pipe(2);
if(unf_coarse = '1') then
sums(3).coarse <= sums(2).coarse + g_ref_clk_rate;
sums(3).utc <= sums(2).utc - 1;
elsif(ovf_coarse = "10") then
sums(3).coarse <= sums(2).coarse - (2*g_ref_clk_rate);
sums(3).utc <= sums(2).utc + 2;
elsif(ovf_coarse = "01") then
sums(3).coarse <= sums(2).coarse - g_ref_clk_rate;
sums(3).utc <= sums(2).utc + 1;
else
sums(3).coarse <= sums(2).coarse;
sums(3).utc <= sums(2).utc;
end if;
sums(3).frac <= sums(2).frac;
end if;
end if;
end process;
-- clip the extra bits and output the result
valid_o <= pipe(c_NUM_PIPELINE_STAGES-1);
q_tai_o <= std_logic_vector(sums(c_NUM_PIPELINE_STAGES-1).utc(g_tai_bits-1 downto 0));
q_cycles_o <= std_logic_vector(sums(c_NUM_PIPELINE_STAGES-1).coarse(g_cycles_bits-1 downto 0));
q_frac_o <= std_logic_vector(sums(c_NUM_PIPELINE_STAGES-1).frac(g_frac_bits-1 downto 0));
end rtl;
scripts/dds600m.pins 0 → 100644
View file @ 1bd30289
#
# Mezzanine top level pin assignment file:
# syntax: pin FMC_pin_name Core_Pin_name IO_Standard
# % is replaced with FMC number if the carrier supports more than 1 mezzanine
#
mezzanine fmc-dds-600m
pin la_n2 dds%_dac_n_o[11] lvds_25
pin la_p2 dds%_dac_p_o[11] lvds_25
pin la_n4 dds%_dac_n_o[9] lvds_25
pin la_p4 dds%_dac_p_o[9] lvds_25
pin la_n7 dds%_dac_n_o[6] lvds_25
pin la_p7 dds%_dac_p_o[6] lvds_25
pin la_n11 dds%_dac_n_o[3] lvds_25
pin la_p11 dds%_dac_p_o[3] lvds_25
pin la_n15 dds%_dac_n_o[0] lvds_25
pin la_p15 dds%_dac_p_o[0] lvds_25
pin la_p14 dds%_pll_sys_sync_n_o lvcmos25
pin la_n14 dds%_pd_ce_o lvcmos25
pin la_p19 dds%_pll_sys_refmon_i lvcmos25
pin la_n19 dds%_pll_sys_ld_i lvcmos25
pin la_p21 dds%_pll_vcxo_sdo_i lvcmos25
pin la_n21 dds%_pll_sys_reset_n_o lvcmos25
pin la_p24 dds%_adc_sdo_i lvcmos25
pin la_n24 dds%_adc_sck_o lvcmos25
pin la_p28 dds%_wr_dac_sclk_o lvcmos25
pin la_n28 dds%_pll_vcxo_cs_n_o lvcmos25
pin la_p30 dds%_pll_vcxo_function_o lvcmos25
pin la_n30 dds%_si57x_oe_o lvcmos25
pin la_p32 dds%_pll_vcxo_status_i lvcmos25
pin la_n32 dds%_onewire_b lvcmos25
#pin clk1m2c_n dds%_wr_ref_clk_n_i lvds_25
#pin clk1m2c_p dds%_wr_ref_clk_p_i lvds_25
pin la_n0 dds%_wr_ref_clk_n_i lvds_25
pin la_p0 dds%_wr_ref_clk_p_i lvds_25
pin la_p3 dds%_dac_p_o[10] lvds_25
pin la_n3 dds%_dac_n_o[10] lvds_25
pin la_p8 dds%_dac_p_o[7] lvds_25
pin la_n8 dds%_dac_n_o[7] lvds_25
pin la_p12 dds%_dac_p_o[4] lvds_25
pin la_n12 dds%_dac_n_o[4] lvds_25
pin la_p16 dds%_dac_p_o[1] lvds_25
pin la_n16 dds%_dac_n_o[1] lvds_25
pin la_p20 dds%_trig_term_en_o lvcmos25
pin la_n20 dds%_pll_sys_status_i lvcmos25
pin la_p22 dds%_pll_sclk_o lvcmos25
pin la_n22 dds%_pll_sdio_b lvcmos25
pin la_p25 dds%_adc_cnv_o lvcmos25
pin la_n25 dds%_adc_sdi_o lvcmos25
pin la_p29 dds%_wr_dac_din_o lvcmos25
pin la_n29 dds%_wr_dac_sync_n_o lvcmos25
pin la_n31 dds%_si57x_sda_b lvcmos25
pin la_p33 dds%_si57x_scl_b lvcmos25
pin la_p1 dds%_dac_p_o[13] lvds_25
pin la_n1 dds%_dac_n_o[13] lvds_25
pin la_p5 dds%_dac_p_o[8] lvds_25
pin la_n5 dds%_dac_n_o[8] lvds_25
pin la_p9 dds%_dac_p_o[5] lvds_25
pin la_n9 dds%_dac_n_o[5] lvds_25
pin la_p13 dds%_dac_p_o[2] lvds_25
pin la_n13 dds%_dac_n_o[2] lvds_25
pin la_n17 dds%_dac_pwdn_o lvcmos25
pin la_p23 dds%_pd_lockdet_i lvcmos25
pin la_n23 dds%_pd_clk_o lvcmos25
pin la_p26 dds%_pll_sys_cs_n_o lvcmos25
# pin la_n26 dds%_filter_clk_o lvcmos25
pin la_p6 dds%_dac_p_o[12] lvds_25
pin la_n6 dds%_dac_n_o[12] lvds_25
pin la_p10 dds%_trig_dir_o lvcmos25
pin la_n10 dds%_trig_act_o lvcmos25
#pin la_p18 dds_trig_p_b lvds_25
#pin la_n18 dds_trig_n_b lvds_25
pin la_p27 dds_pd_data_b lvcmos25
pin la_n27 dds_pd_le_o lvcmos25
#eof
scripts/spec.pins 0 → 100644
View file @ 1bd30289
#
# Carrier FMC pins description file
#
# Syntax:
# carrier carrier_name numeber_of_fmc_slots
# pin FMC_Slot signal_name FPGA_pin
carrier spec 1
pin 0 clk1m2c_p L20 #
pin 0 clk1m2c_n L22 #
pin 0 clk0m2c_p E16 #
pin 0 clk0m2c_n F16 #
pin 0 la_p33 C19
pin 0 la_p32 B20
pin 0 la_p31 D7
pin 0 la_p30 V17
pin 0 la_p29 W17
pin 0 la_p28 Y16
pin 0 la_p27 AA18
pin 0 la_p26 Y17
pin 0 la_p25 T15
pin 0 la_p24 W14
pin 0 la_p23 AA16
pin 0 la_p22 R13
pin 0 la_p21 V13
pin 0 la_p20 R11
pin 0 la_p19 Y15
pin 0 la_p18 T12
pin 0 la_p17 Y13
pin 0 la_p16 W12
pin 0 la_p15 V11
pin 0 la_p14 AA4
pin 0 la_p13 Y9
pin 0 la_p12 T10
pin 0 la_p11 W10
pin 0 la_p10 AA8
pin 0 la_p9 Y7
pin 0 la_p8 R9
pin 0 la_p7 U9
pin 0 la_p6 Y5
pin 0 la_p5 AA6
pin 0 la_p4 T8
pin 0 la_p3 V7
pin 0 la_p2 W6
pin 0 la_p1 AA12
pin 0 la_p0 Y11
pin 0 la_n33 A19
pin 0 la_n32 A20
pin 0 la_n31 C18
pin 0 la_n30 W18
pin 0 la_n29 Y18
pin 0 la_n28 W15
pin 0 la_n27 AB18
pin 0 la_n26 AB17
pin 0 la_n25 U15
pin 0 la_n24 Y14
pin 0 la_n23 AB16
pin 0 la_n22 T14
pin 0 la_n21 W13
pin 0 la_n20 T11
pin 0 la_n19 AB15
pin 0 la_n18 U12
pin 0 la_n17 AB13
pin 0 la_n16 Y12
pin 0 la_n15 W11
pin 0 la_n14 AB4 #
pin 0 la_n13 AB9
pin 0 la_n12 U10
pin 0 la_n11 Y10
pin 0 la_n10 AB8
pin 0 la_n9 AB7
pin 0 la_n8 R8
pin 0 la_n7 V9
pin 0 la_n6 AB5 #
pin 0 la_n5 AB6 #
pin 0 la_n4 U8 #
pin 0 la_n3 W8 #
pin 0 la_n2 Y6 #
pin 0 la_n1 AB12 #
pin 0 la_n0 AB11 #
#eof
scripts/spec_top.ucf 0 → 100644
View file @ 1bd30289
#bank 0
NET "CLK_20M_VCXO_I" LOC = H12;
NET "CLK_20M_VCXO_I" IOSTANDARD = "LVCMOS25";
#NET "clk_125m_pllref_n_i" LOC = F10;
#NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
#NET "clk_125m_pllref_p_i" LOC = G9;
#NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#NET "clk_125m_gtp_n_i" LOC = D11;
#NET "clk_125m_gtp_p_i" LOC = C11;
#####################################################################
### Gennum ports
#####################################################################
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "GPIO[1]" LOC = U16;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO[0]" LOC = AB19;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
#####################################################################
### SPEC Generic Stuff
#####################################################################
NET "LED_RED" LOC = D5;
NET "LED_RED" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN" LOC = E5;
NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
NET "dac_cs1_n_o" LOC = A3;
NET "dac_cs1_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_cs2_n_o" LOC = B3;
NET "dac_cs2_n_o" IOSTANDARD = "LVCMOS25";
#NET "dac_clr_n_o" LOC = F7;
#NET "dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "BUTTON1_I" LOC = C22;
NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
NET "BUTTON2_I" LOC = D21;
NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
NET "fmc_scl_b" LOC = F7 ;
NET "fmc_scl_b" IOSTANDARD =LVCMOS25;
NET "fmc_sda_b" LOC = F8 ;
NET "fmc_sda_b" IOSTANDARD =LVCMOS25;
#net "led_n_o[0]" loc=c20;
#net "led_n_o[0]" IOSTANDARD=LVCMOS18;
#net "led_n_o[1]" loc=F18;
#net "led_n_o[1]" IOSTANDARD=LVCMOS18;
#net "led_n_o[2]" loc=f20;
#net "led_n_o[2]" IOSTANDARD=LVCMOS18;
#net "led_n_o[3]" loc=G19;
#net "led_n_o[3]" IOSTANDARD=LVCMOS18;
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc_PRSNT_M2C_L_i" LOC="AB14";
#NET "sfp_rxp_i" LOC= D15;
#NET "sfp_rxn_i" LOC= C15;
#NET "sfp_txp_o" LOC= B16;
#NET "sfp_txn_o" LOC= A16;
#NET "SFP_MOD_DEF1_b" LOC = C17;
#NET "SFP_MOD_DEF1_b" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF0_b" LOC = G15;
#NET "SFP_MOD_DEF0_b" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF2_b" LOC = G16;
#NET "SFP_MOD_DEF2_b" IOSTANDARD = "LVCMOS25";
#NET "SFP_RATE_SELECT_b" LOC = H14;
#NET "SFP_RATE_SELECT_b" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_FAULT_i" LOC = A17;
#NET "SFP_TX_FAULT_i" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_DISABLE_o" LOC = F17;
#NET "SFP_TX_DISABLE_o" IOSTANDARD = "LVCMOS25";
#NET "SFP_LOS_i" LOC = D18;
#NET "SFP_LOS_i" IOSTANDARD = "LVCMOS25";
####################################################################################
# Misc
####################################################################################
#NET "uart_rxd_i" LOC= A2;
#NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
#NET "uart_txd_o" LOC= B2;
#NET "uart_txd_o" IOSTANDARD=LVCMOS25;
#bank 0
#gennum
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
# <ucfgen_start>
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-dds-600m slot 0
NET "dds_dac_n_o[11]" LOC = "Y6";
NET "dds_dac_n_o[11]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[11]" LOC = "W6";
NET "dds_dac_p_o[11]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[9]" LOC = "U8";
NET "dds_dac_n_o[9]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[9]" LOC = "T8";
NET "dds_dac_p_o[9]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[6]" LOC = "V9";
NET "dds_dac_n_o[6]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[6]" LOC = "U9";
NET "dds_dac_p_o[6]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[3]" LOC = "Y10";
NET "dds_dac_n_o[3]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[3]" LOC = "W10";
NET "dds_dac_p_o[3]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[0]" LOC = "W11";
NET "dds_dac_n_o[0]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[0]" LOC = "V11";
NET "dds_dac_p_o[0]" IOSTANDARD = "LVDS_25";
NET "dds_pll_sys_sync_n_o" LOC = "AA4";
NET "dds_pll_sys_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "dds_pd_ce_o" LOC = "AB4";
NET "dds_pd_ce_o" IOSTANDARD = "LVCMOS25";
NET "dds_pll_sys_refmon_i" LOC = "Y15";
NET "dds_pll_sys_refmon_i" IOSTANDARD = "LVCMOS25";
NET "dds_pll_sys_ld_i" LOC = "AB15";
NET "dds_pll_sys_ld_i" IOSTANDARD = "LVCMOS25";
NET "dds_pll_vcxo_sdo_i" LOC = "V13";
NET "dds_pll_vcxo_sdo_i" IOSTANDARD = "LVCMOS25";
NET "dds_pll_sys_reset_n_o" LOC = "W13";
NET "dds_pll_sys_reset_n_o" IOSTANDARD = "LVCMOS25";
NET "dds_adc_sdo_i" LOC = "W14";
NET "dds_adc_sdo_i" IOSTANDARD = "LVCMOS25";
NET "dds_adc_sck_o" LOC = "Y14";
NET "dds_adc_sck_o" IOSTANDARD = "LVCMOS25";
NET "dds_wr_dac_sclk_o" LOC = "Y16";
NET "dds_wr_dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "dds_pll_vcxo_cs_n_o" LOC = "W15";
NET "dds_pll_vcxo_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "dds_pll_vcxo_function_o" LOC = "V17";
NET "dds_pll_vcxo_function_o" IOSTANDARD = "LVCMOS25";
NET "dds_si57x_oe_o" LOC = "W18";
NET "dds_si57x_oe_o" IOSTANDARD = "LVCMOS25";
NET "dds_pll_vcxo_status_i" LOC = "B20";
NET "dds_pll_vcxo_status_i" IOSTANDARD = "LVCMOS25";
NET "dds_onewire_b" LOC = "A20";
NET "dds_onewire_b" IOSTANDARD = "LVCMOS25";
NET "dds_wr_ref_clk_n_i" LOC = "AB11";
NET "dds_wr_ref_clk_n_i" IOSTANDARD = "LVDS_25";
NET "dds_wr_ref_clk_p_i" LOC = "Y11";
NET "dds_wr_ref_clk_p_i" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[10]" LOC = "V7";
NET "dds_dac_p_o[10]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[10]" LOC = "W8";
NET "dds_dac_n_o[10]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[7]" LOC = "R9";
NET "dds_dac_p_o[7]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[7]" LOC = "R8";
NET "dds_dac_n_o[7]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[4]" LOC = "T10";
NET "dds_dac_p_o[4]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[4]" LOC = "U10";
NET "dds_dac_n_o[4]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[1]" LOC = "W12";
NET "dds_dac_p_o[1]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[1]" LOC = "Y12";
NET "dds_dac_n_o[1]" IOSTANDARD = "LVDS_25";
NET "dds_trig_term_en_o" LOC = "R11";
NET "dds_trig_term_en_o" IOSTANDARD = "LVCMOS25";
NET "dds_pll_sys_status_i" LOC = "T11";
NET "dds_pll_sys_status_i" IOSTANDARD = "LVCMOS25";
NET "dds_pll_sclk_o" LOC = "R13";
NET "dds_pll_sclk_o" IOSTANDARD = "LVCMOS25";
NET "dds_pll_sdio_b" LOC = "T14";
NET "dds_pll_sdio_b" IOSTANDARD = "LVCMOS25";
NET "dds_adc_cnv_o" LOC = "T15";
NET "dds_adc_cnv_o" IOSTANDARD = "LVCMOS25";
NET "dds_adc_sdi_o" LOC = "U15";
NET "dds_adc_sdi_o" IOSTANDARD = "LVCMOS25";
NET "dds_wr_dac_din_o" LOC = "W17";
NET "dds_wr_dac_din_o" IOSTANDARD = "LVCMOS25";
NET "dds_wr_dac_sync_n_o" LOC = "Y18";
NET "dds_wr_dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "dds_si57x_sda_b" LOC = "C18";
NET "dds_si57x_sda_b" IOSTANDARD = "LVCMOS25";
NET "dds_si57x_scl_b" LOC = "C19";
NET "dds_si57x_scl_b" IOSTANDARD = "LVCMOS25";
NET "dds_dac_p_o[13]" LOC = "AA12";
NET "dds_dac_p_o[13]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[13]" LOC = "AB12";
NET "dds_dac_n_o[13]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[8]" LOC = "AA6";
NET "dds_dac_p_o[8]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[8]" LOC = "AB6";
NET "dds_dac_n_o[8]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[5]" LOC = "Y7";
NET "dds_dac_p_o[5]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[5]" LOC = "AB7";
NET "dds_dac_n_o[5]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[2]" LOC = "Y9";
NET "dds_dac_p_o[2]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[2]" LOC = "AB9";
NET "dds_dac_n_o[2]" IOSTANDARD = "LVDS_25";
NET "dds_dac_pwdn_o" LOC = "AB13";
NET "dds_dac_pwdn_o" IOSTANDARD = "LVCMOS25";
NET "dds_pd_lockdet_i" LOC = "AA16";
NET "dds_pd_lockdet_i" IOSTANDARD = "LVCMOS25";
NET "dds_pd_clk_o" LOC = "AB16";
NET "dds_pd_clk_o" IOSTANDARD = "LVCMOS25";
NET "dds_pll_sys_cs_n_o" LOC = "Y17";
NET "dds_pll_sys_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "dds_dac_p_o[12]" LOC = "Y5";
NET "dds_dac_p_o[12]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[12]" LOC = "AB5";
NET "dds_dac_n_o[12]" IOSTANDARD = "LVDS_25";
NET "dds_trig_dir_o" LOC = "AA8";
NET "dds_trig_dir_o" IOSTANDARD = "LVCMOS25";
NET "dds_trig_act_o" LOC = "AB8";
NET "dds_trig_act_o" IOSTANDARD = "LVCMOS25";
NET "dds_pd_data_b" LOC = "AA18";
NET "dds_pd_data_b" IOSTANDARD = "LVCMOS25";
NET "dds_pd_le_o" LOC = "AB18";
NET "dds_pd_le_o" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
scripts/svec.pins 0 → 100644
View file @ 1bd30289
#
# Carrier FMC pins description file
#
# Syntax:
# carrier carrier_name numeber_of_fmc_slots
# pin FMC_Slot signal_name FPGA_pin
carrier svec-v0 2
pin 0 clk1m2c_p E16
pin 0 clk1m2c_n D16
pin 0 clk0m2c_p H15
pin 0 clk0m2c_n G15
pin 0 la_p33 J12
pin 0 la_p32 H11
pin 0 la_p31 L11
pin 0 la_p30 J13
pin 0 la_p29 F9
pin 0 la_p28 L12
pin 0 la_p27 M13
pin 0 la_p26 L14
pin 0 la_p25 F11
pin 0 la_p24 G10
pin 0 la_p23 M15
pin 0 la_p22 F13
pin 0 la_p21 G12
pin 0 la_p20 F15
pin 0 la_p19 G14
pin 0 la_p18 J14
pin 0 la_p17 B15
pin 0 la_p16 F19
pin 0 la_p15 H16
pin 0 la_p14 F17
pin 0 la_p13 G18
pin 0 la_p12 F21
pin 0 la_p11 G20
pin 0 la_p10 L21
pin 0 la_p9 M20
pin 0 la_p8 F23
pin 0 la_p7 G22
pin 0 la_p6 B25
pin 0 la_p5 M19
pin 0 la_p4 D24
pin 0 la_p3 E25
pin 0 la_p2 J22
pin 0 la_p1 H21
pin 0 la_p0 C16
pin 0 la_n33 H12
pin 0 la_n32 G11
pin 0 la_n31 K11
pin 0 la_n30 H13
pin 0 la_n29 E9
pin 0 la_n28 K12
pin 0 la_n27 L13
pin 0 la_n26 K14
pin 0 la_n25 E11
pin 0 la_n24 F10
pin 0 la_n23 K15
pin 0 la_n22 E13
pin 0 la_n21 F12
pin 0 la_n20 E15
pin 0 la_n19 F14
pin 0 la_n18 H14
pin 0 la_n17 A15
pin 0 la_n16 E19
pin 0 la_n15 G16
pin 0 la_n14 E17
pin 0 la_n13 F18
pin 0 la_n12 E21
pin 0 la_n11 F20
pin 0 la_n10 K21
pin 0 la_n9 L20
pin 0 la_n8 E23
pin 0 la_n7 F22
pin 0 la_n6 A25
pin 0 la_n5 L19
pin 0 la_n4 C24
pin 0 la_n3 D25
pin 0 la_n2 H22
pin 0 la_n1 G21
pin 0 la_n0 A16
pin 1 clk1m2c_p AH16
pin 1 clk1m2c_n AK16
pin 1 clk0m2c_p AF16
pin 1 clk0m2c_n AG16
pin 1 la_p33 AA19
pin 1 la_p32 W19
pin 1 la_p31 Y21
pin 1 la_p30 W20
pin 1 la_p29 AC24
pin 1 la_p28 AA22
pin 1 la_p27 AB20
pin 1 la_p26 AC19
pin 1 la_p25 AB17
pin 1 la_p24 AB21
pin 1 la_p23 AF25
pin 1 la_p22 AE24
pin 1 la_p21 AD22
pin 1 la_p20 AE19
pin 1 la_p19 AE23
pin 1 la_p18 AE21
pin 1 la_p17 AC16
pin 1 la_p16 AB14
pin 1 la_p15 Y17
pin 1 la_p14 Y15
pin 1 la_p13 AC15
pin 1 la_p12 AE15
pin 1 la_p11 Y16
pin 1 la_p10 Y14
pin 1 la_p9 W14
pin 1 la_p8 AB12
pin 1 la_p7 AD12
pin 1 la_p6 AD10
pin 1 la_p5 AE11
pin 1 la_p4 AJ15
pin 1 la_p3 AE13
pin 1 la_p2 AC11
pin 1 la_p1 AG8
pin 1 la_p0 AJ17
pin 1 la_n33 AB19
pin 1 la_n32 Y19
pin 1 la_n31 AA21
pin 1 la_n30 Y20
pin 1 la_n29 AD24
pin 1 la_n28 AC22
pin 1 la_n27 AC20
pin 1 la_n26 AD19
pin 1 la_n25 AD17
pin 1 la_n24 AC21
pin 1 la_n23 AG25
pin 1 la_n22 AF24
pin 1 la_n21 AE22
pin 1 la_n20 AF19
pin 1 la_n19 AF23
pin 1 la_n18 AF21
pin 1 la_n17 AD16
pin 1 la_n16 AC14
pin 1 la_n15 AA17
pin 1 la_n14 AA15
pin 1 la_n13 AD15
pin 1 la_n12 AF15
pin 1 la_n11 AB16
pin 1 la_n10 AA14
pin 1 la_n9 Y13
pin 1 la_n8 AC12
pin 1 la_n7 AE12
pin 1 la_n6 AE10
pin 1 la_n5 AF11
pin 1 la_n4 AK15
pin 1 la_n3 AF13
pin 1 la_n2 AD11
pin 1 la_n1 AH8
pin 1 la_n0 AK17
#eof
scripts/ucfgen.py 0 → 100755
View file @ 1bd30289
#!/usr/bin/python
import re, os
def find_first(cond, l):
x = filter(cond, l)
if len(x):
return x[0]
else:
return None
class MezzaninePin:
def __init__(self, fmc_line=None, port_name=None, io_standard=None):
self.fmc_line = fmc_line
self.port_name = port_name
self.io_standard = io_standard
def parse(self, s):
self.fmc_line = s[1]
self.port_name = s[2]
self.io_standard= s[3]
def __str__(self):
return "FMC Pin: name %s port %s io %s" % ( self.fmc_line, self.port_name, self.io_standard)
class CarrierPin:
def __init__(self, fmc_line=None, fmc_slot=None, fpga_pin=None):
self.fmc_slot = fmc_slot
self.fmc_line = fmc_line
self.fpga_pin = fpga_pin
def parse(self, s):
self.fmc_slot = int(s[1], 10)
self.fmc_line = s[2]
self.fpga_pin = s[3]
def __str__(self):
return "Carrier Pin: name %s slot %d pin %s" % ( self.fmc_line, self.fmc_slot, self.fpga_pin)
class Carrier:
def __init__(self, name, num_slots):
self.name = name
self.num_slots = num_slots
self.pins = []
def add_pin(self, pin):
self.pins.append(pin)
class Mezzanine:
def __init__(self, name):
self.name = name
self.pins = []
def add_pin(self, pin):
self.pins.append(pin)
class UCFGen:
desc_files_path = ["./", "./pin_defs"];
def __init__(self):
self.carriers = []
self.mezzanines = []
pass
def load_desc_file(self, name):
lines=open(name,"r").read().splitlines()
import re
m_ncomments = re.compile("^\s*([^#]+)\s*#?.*$")
car = mez = None
for l in lines:
m=re.match(m_ncomments, l)
if not m:
continue
tokens = m.group(1).split()
command = tokens[0]
if(command == "carrier"):
car = Carrier(tokens[1], int(tokens[2], 10))
elif(command == "mezzanine"):
mez = Mezzanine(tokens[1])
elif(command == "pin"):
if(car):
p=CarrierPin()
p.parse(tokens)
car.add_pin(p)
elif(mez):
p=MezzaninePin()
p.parse(tokens)
mez.add_pin(p)
else:
raise Exception("%s: define a carrier/mezzanine before defining pins." % name)
else:
raise Exception("%s: Unrecognized command '%s'." % (name, command))
if(car):
self.carriers.append(car)
elif(mez):
self.mezzanines.append(mez)
def load_descs(self):
for d in self.desc_files_path:
if not os.path.isdir(d):
continue
for f in os.listdir(d):
fname=d+"/"+f
if(os.path.isfile(fname) and fname.endswith(".pins")):
self.load_desc_file(fname)
# print("Loaded %d carrier and %d mezzanine pin descriptions." % ( len(self.carriers), len(self.mezzanines)))
def dump_descs(self):
print("Supported carriers:")
for c in self.carriers:
print("* %s" % c.name)
print("Supported mezzanines:")
for m in self.mezzanines:
print("* %s" % m.name)
def generate_ucf(self, ucf_filename, carrier_name, slot_mappings):
f = None
try:
f = open(ucf_filename,"r")
except:
pass
ucf_user=[]
if f:
ucf_lines=f.read().splitlines()
usermode = True
for l in ucf_lines:
if(l == "# <ucfgen_start>"):
usermode = False
if(usermode):
ucf_user.append(l)
if (l == "# <ucfgen_end>"):
usermode = True
f.close()
car = find_first(lambda car: car.name == carrier_name, self.carriers)
if not car:
raise Exception("Unsupported carrier: %s" % carrier_name)
ucf_ours=[]
ucf_ours.append("")
ucf_ours.append("# <ucfgen_start>")
ucf_ours.append("")
ucf_ours.append("# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.")
slot = 0
for mapping in slot_mappings:
if not mapping:
continue
mez = find_first(lambda mez: mez.name == mapping, self.mezzanines)
if not mez:
raise Exception("Unsupported mezzanine: %s " % mapping)
print("Found mezzanine %s for slot %d." % (mez.name, slot))
if(car.num_slots > 1):
slot_str = str(slot)
else:
slot_str=""
ucf_ours.append("# ucfgen pin assignments for mezzanine %s slot %d" % (mapping, slot))
for p in mez.pins:
p_carrier = find_first(lambda f : f.fmc_line == p.fmc_line and f.fmc_slot == slot, car.pins)
if (not p_carrier):
raise Exception("Mezzanine FMC line %s not defined in the carrier description" % p.fmc_line)
print(p.port_name.replace("%", slot_str))
ucf_ours.append("NET \"%s\" LOC = \"%s\";" % ( p.port_name.replace("%", slot_str), p_carrier.fpga_pin))
ucf_ours.append("NET \"%s\" IOSTANDARD = \"%s\";" % ( p.port_name.replace("%", slot_str), p.io_standard.upper()))
slot=slot+1
ucf_ours.append("# <ucfgen_end>")
f_out = open(ucf_filename, "w")
for l in ucf_user:
f_out.write(l+"\n")
for l in ucf_ours:
f_out.write(l+"\n")
f_out.close()
print("Successfully updated UCF file %s" % ucf_filename)
def usage():
import getopt, sys
print("Ucfgen, a trivial script for automatizing Xilinx UCF FMC Mezzanine-Carrier pin assignments.\n")
print("usage: %s [options] ucf_file" % sys.argv[0])
print("Options:")
print(" -h, --help: print this message");
print(" -c, --carrier <type>: select carrier type");
print(" -m, --mezzanine <slot:type>: select <type> of mezzanine inserted into carrier slot <slot>");
print(" -l, --list: list supported carriers and mezzanines");
def main():
import getopt, sys, os
if len(sys.argv) == 1:
print("Missing command line option. Type %s --help for spiritual guidance." % sys.argv[0])
sys.exit(0)
try:
opts, args = getopt.getopt(sys.argv[1:], "hlo:m:c:", ["help", "list", "output=", "mezzanine=slot:type", "carrier="])
except getopt.GetoptError, err:
print str(err)
usage()
sys.exit(1)
output = None
carrier = None
u = UCFGen()
u.desc_files_path.append(os.path.dirname(os.path.realpath(sys.argv[0])))
u.load_descs()
mezzanines=[]
for i in range(0,128):
mezzanines.append(None)
for o, a in opts:
if o in [ "-h", "--help" ]:
usage()
sys.exit()
elif o in ("-l", "--list"):
u.dump_descs()
sys.exit()
elif o in ("-c", "--carrier"):
carrier = a
elif o in ("-m", "--mezzanine"):
t=a.split(":")
mezzanines[int(t[0])] = t[1]
else:
assert False, "unhandled option"
ucf_name = sys.argv[len(sys.argv)-1]
u.generate_ucf(ucf_name, carrier, mezzanines)
main()
#u.generate_ucf("svec_top.ucf", "svec-v0", [ "fmc-delay-v4", "fmc-delay-v4" ])
\ No newline at end of file
syn/spec/Manifest.py 0 → 100644
View file @ 1bd30289
target = "xilinx"
action = "synthesis"
fetchto = "../../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_rf_demo.xise"
modules = { "local" : [ "../../top" ] }
files = "wrc.ram"
\ No newline at end of file
syn/spec/spec_rf_demo.xise 0 → 100644
View file @ 1bd30289
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_top|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../top/spec/wr/spec_top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="-g INIT_9K:Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="spec_top" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spec_top_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spec_top_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_top_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spec_top_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="spec_top" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/13.1/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="spec_fine_delay" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-09-01T16:21:56" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="AD47E2A8B67702228A4AADB4C2314B92" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<libraries/>
<files>
<file xil_pn:name="../../top/spec_top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../../wr-repos/wr-cores/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../top/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../top/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../rtl/dds_stage.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../rtl/pi_control.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../rtl/dds_quad_channel.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../rtl/mdsp.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../rtl/dds_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../rtl/max5870_serializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../../../wr-repos/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../rtl/cic_1024x.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../rtl/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../rtl/ad7980_if.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="225"/>
</file>
<file xil_pn:name="../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="226"/>
</file>
<file xil_pn:name="../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="227"/>
</file>
<file xil_pn:name="../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="228"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
</project>
testbench/dds_single/main.sv
View file @ 1bd30289
......@@ -9,19 +9,12 @@ module main;
reg clk = 0;
reg rst_n = 0;
reg [g_lut_sample_bits + g_lut_slope_bits-1:0] lut_data;
wire [g_lut_size_log2-1:0] lut_addr;
wire [13:0] y0, y1, y2 ,y3;
reg [g_lut_sample_bits + g_lut_slope_bits-1:0] lut[0:2**g_lut_size_log2-1];
wire signed [13:0] y;
reg [43:0] tune;
always@(posedge clk)
lut_data <= lut[lut_addr];
dds_single_channel #(
dds_quad_channel #(
.g_lut_sample_bits (g_lut_sample_bits),
.g_lut_slope_bits (g_lut_slope_bits),
.g_lut_size_log2 (g_lut_size_log2),
......@@ -32,17 +25,18 @@ module main;
.rst_n_i (rst_n),
.acc_i (44'h0),
.tune_i (44'd100000000000),
.tune_i (tune),
.acc_load_i (1'b0),
.tune_load_i(1'b1),
.dreq_i(1'b1),
// #y_o : out std_logic_vector(g_sample_bits-1 downto 0);
.lut_addr_o (lut_addr),
.lut_data_i (lut_data),
.y_o(y)
.y0_o(y0),
.y1_o(y1),
.y2_o(y2),
.y3_o(y3)
);
......@@ -55,10 +49,11 @@ module main;
int i, lut_size;
lut_size = 2**g_lut_size_log2;
// tune = 44'd100000000000;
//int'(real'(2**g_frac_bits) * real'(2**g_lut_size_log2) / fout / fs * 4.0);
// tune = int'(real'(2**32) * real'(2**g_lut_size_log2) / fout / fs * 2.0);
tune = 44'd1000000000000;
for (i=0;i<lut_size;i++)
begin
real y0,y1,ampl;
......@@ -76,7 +71,8 @@ module main;
lv [g_lut_sample_bits+g_lut_slope_bits-1:g_lut_sample_bits] = int' ((y1-y0) * 128.0);
lut[i] = lv;
// DUT.lut01[i] = lv;
// DUT.lut23[i] = lv;
end
......@@ -110,7 +106,7 @@ module main;
l_count <= l_count + 1;
$sformat(s, "%d\n", int'(y));
$sformat(s, "%d\n%d\n%d\n%d\n", int'(y0),int'(y1),int'(y2),int'(y3));
$fwrite(f_out, s);
......
testbench/dds_single/wave.do
View file @ 1bd30289
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/g_acc_frac_bits
add wave -noupdate /main/DUT/g_dither_init_value
add wave -noupdate /main/DUT/g_output_bits
add wave -noupdate /main/DUT/g_lut_sample_bits
add wave -noupdate /main/DUT/g_lut_slope_bits
add wave -noupdate /main/DUT/g_interp_shift
add wave -noupdate /main/DUT/g_lut_size_log2
add wave -noupdate /main/DUT/c_acc_bits
add wave -noupdate /main/DUT/c_output_shift
add wave -noupdate /main/DUT/clk_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/acc_load_i
add wave -noupdate /main/DUT/tune_load_i
add wave -noupdate /main/DUT/acc_i
add wave -noupdate /main/DUT/tune_i
add wave -noupdate /main/DUT/dreq_i
add wave -noupdate -format Analog-Step -height 100 -max 2048.0 -min -2048.0 /main/DUT/y_o
add wave -noupdate -format Analog-Step -height 50 -max 1000.0 -min -1000.0 -radix decimal /main/DUT/interp
add wave -noupdate /main/DUT/lut_addr_o
add wave -noupdate /main/DUT/lut_data_i
add wave -noupdate /main/DUT/acc0
add wave -noupdate /main/DUT/acc1
add wave -noupdate /main/DUT/tune
add wave -noupdate /main/DUT/phase
add wave -noupdate /main/DUT/frac
add wave -noupdate /main/DUT/half
add wave -noupdate /main/DUT/addr0
add wave -noupdate /main/DUT/addr1
add wave -noupdate /main/DUT/tmp
add wave -noupdate /main/DUT/tmp2
add wave -noupdate /main/DUT/sign
add wave -noupdate /main/DUT/lut_in
add wave -noupdate /main/DUT/lut_slope
add wave -noupdate -radix decimal /main/DUT/lut_sample
add wave -noupdate -radix decimal /main/DUT/qv
add wave -noupdate /main/DUT/interp_mul
add wave -noupdate /main/DUT/clk_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/acc_load_i
add wave -noupdate /main/DUT/tune_load_i
add wave -noupdate /main/DUT/acc_i
add wave -noupdate /main/DUT/tune_i
add wave -noupdate /main/DUT/dreq_i
add wave -noupdate -format Analog-Step -height 100 -max 2048.0 -min -2048.0 /main/DUT/y_o
add wave -noupdate /main/DUT/dither_in
add wave -noupdate /main/DUT/lfsr
add wave -noupdate /main/DUT/lut_addr_o
add wave -noupdate /main/DUT/lut_data_i
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/g_acc_frac_bits}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/g_dither_init_value}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/g_output_bits}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/g_lut_sample_bits}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/g_lut_slope_bits}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/g_interp_shift}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/g_lut_size_log2}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/g_dither_taps}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/g_dither_length}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/c_dither_bits}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/c_acc_bits}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/c_output_shift}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/dither_in}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/clk_i}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/rst_n_i}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/acc_i}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/dreq_i}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/y_o}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/lut_addr_o}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/lut_data_i}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/acc0}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/acc1}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/tune}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/phase}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/frac}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/frac_d0}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/frac_d1}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/frac_d2}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/frac_d3}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/half}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/addr0}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/addr1}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/tmp}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/tmp2}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/tmp3}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/sign}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/lut_in}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/lut_slope}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/slope_d0}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/lut_sample}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/sample_d0}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/interp}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/interp_d0}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/qv}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/yt}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/interp_mul}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/lfsr}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/clk_i}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/rst_n_i}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/acc_i}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/dreq_i}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/y_o}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/lut_addr_o}
add wave -noupdate {/main/DUT/genblk1[0]/U_Stage_X/lut_data_i}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {19833 ps} 0}
WaveRestoreCursors {{Cursor 1} {25426 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -64,4 +70,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {6845 ps} {33095 ps}
WaveRestoreZoom {0 ps} {210 ns}
testbench/lfsr/Manifest.py 0 → 100644
View file @ 1bd30289
action= "simulation"
target= "xilinx"
fetchto="../../ip_cores"
modules = { "local" : [ "../../rtl" ] }
files = ["main.sv"]
vlog_opt="+incdir+../../sim"
testbench/lfsr/main.sv 0 → 100644
View file @ 1bd30289
module main;
reg clk = 0;
reg rst_n = 0;
reg [1:0] en=0;
lfsr_gen #(
.g_length (16),
.g_taps (16'hb400),
.g_recurse(1),
.g_init_value(16'hace1)
) DUT (
.clk_i (clk),
.rst_n_i (rst_n),
.enable_i (1'b1)
);
lfsr_gen #(
.g_length (16),
.g_taps (16'hb400),
.g_recurse(4),
.g_init_value(16'hace1)
) DUT2 (
.clk_i (clk),
.rst_n_i (rst_n),
.enable_i (!en?1'b1:1'b0)
);
initial #100 rst_n = 1;
always #10 clk <= ~clk;
always@(posedge clk)
en<=en+1;
endmodule // main
testbench/lfsr/run.do 0 → 100644
View file @ 1bd30289
make
vlog -sv main.sv +incdir+../../sim
vsim -L unisim work.main -voptargs="+acc" -suppress 8684,8683
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
do wave.do
run 10us
wave zoomfull
radix -hex
testbench/lfsr/wave.do 0 → 100644
View file @ 1bd30289
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/q_o
add wave -noupdate /main/DUT/enable_i
add wave -noupdate /main/DUT2/enable_i
add wave -noupdate /main/DUT2/q_o
add wave -noupdate /main/DUT/r
add wave -noupdate /main/DUT/r
add wave -noupdate /main/DUT2/r
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {210 ns} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ns} {658 ns}
testbench/mdsp/Manifest.py 0 → 100644
View file @ 1bd30289
action= "simulation"
target= "xilinx"
fetchto="../../ip_cores"
modules = { "local" : [ "../../top" ] }
files = ["main.sv"]
vlog_opt="+incdir+../../sim +incdir+gn4124_bfm"
testbench/mdsp/dsp.py 0 → 100755
View file @ 1bd30289
#!/usr/bin/python
import math
class MDsp:
def __init__(self, code_size = 256, state_size = 256):
self.pc = 0
self.code_size = code_size
self.state_size = state_size
self.sidx = 0
self.code = []
def nop(self, _finish = False):
self._insn(self.MAC, 0, 0)
def finish(self):
self._insn(self.FINISH, 0, 0);
INPUT_FLAG = (1<<16)
COEF_SHIFT = (1<<30)
MUL = 0
MAC = 1
CLAMPH = 2
CLAMPL = 3
FINISH = 7
def input(self, id):
return id | self.INPUT_FLAG;
def _insn(self, opcode, coefficient, src, dest = None, move = None, output = None):
opc = (1<<63) if (opcode&(1<<2)) else 0
opc |= (1<<62) if (opcode&(1<<1)) else 0
opc |= (1<<35) if (opcode&(1<<0)) else 0
opc |= int(float(coefficient) * float(self.COEF_SHIFT)) & ((1<<35) - 1);
# opc |= (1<<62) if finish else 0
opc |= (1<<61) if dest != None or move != None else 0
opc |= (1<<60) if output != None else 0
opc |= (1<<59) if src & self.INPUT_FLAG else 0
opc |= (1<<58) if dest != None else 0
print("insn",opcode,"coef",coefficient,"src",src,"dest",dest,"move",move,"out",output)
if(output != None):
opc |= output << 56
opc |= (src & 0x1ff) << 46
if(move != None):
opc |= move << 36
if(dest != None):
opc |= dest << 36
self.code.append(opc)
self.pc += 1
pass
def save(self,filename):
f=open(filename,"w")
for opc in self.code:
f.write("0x%016x\n" % opc)
f.close()
def dump_sv(self,filename):
f=open(filename,"w")
i=0
f.write("uint64_t code[] = '{\n");
for opc in self.code:
f.write("64'h%016x%s\n" % (opc, '};' if i == len(self.code)-1 else ', '))
i += 1
f.close()
def state(self):
self.sidx += 1
return self.sidx
def clear(self):
self.pc = 0
self.sidx = 0
def fir(self, coefs, source, _dest= None, _output = None):
states = []
for c in coefs:
states.append(self.state())
# print(states)
self._insn(self.MUL, coefs[0], source, move = states[0])
for i in range(1, len(coefs) - 1):
# print("tap %d" % i);
self._insn(self.MAC, coefs[i], states[i - 1], move = states[i])
self._insn(self.MAC, coefs[-1], states[len(coefs)-2], dest = _dest, output = _output)
def fir_test(self, coefs, samples):
coefs_int = []
for c in coefs:
coefs_int.append(int(c * self.COEF_SHIFT))
delay = [0]*len(coefs)
output = []
for x in samples:
acc = 0
for i in range(len(coefs)-1, 0, -1):
delay[i] = delay[i-1];
delay[0] = x;
# print(delay)
for i in range(0, len(coefs)):
acc += delay[i] * coefs_int[i];
y = acc >> 30;
output.append(y)
return output
def biquad_lp(self, Q, f0, fs, source, _dest = None, _output = None):
w0 = 2*math.pi*f0/fs;
alpha = math.sin(w0)/(2*Q);
a0 = 1 + alpha;
a1 = (-2*math.cos(w0))/a0;
a2 = (1 - alpha)/a0;
b0 = ((1 - math.cos(w0))/2)/a0;
b1 = (1 - math.cos(w0))/a0;
b2 = ((1 - math.cos(w0))/2)/a0;
s=[ self.state() for i in range(1,5) ]
# print(s)
self._insn(self.MUL, b0, source, move = s[0])
self._insn(self.MAC, b1, s[0], move = s[1])
self._insn(self.MAC, b2, s[1])
self._insn(self.MAC, -a1, s[2], move = s[3])
self._insn(self.MAC, -a2, s[3], dest = s[2], output = _output)
if(_dest != None):
self._insn(self.MAC, 0, s[0], dest = _dest)
def biquad_test(self, Q, f0, fs, samples):
w0 = 2*math.pi*f0/fs;
alpha = math.sin(w0)/(2*Q);
a0 = (1 + alpha);
a1 = int(((-2*math.cos(w0))/a0) * float(self.COEF_SHIFT))
a2 = int(((1 - alpha)/a0) * float(self.COEF_SHIFT))
b0 = int(((1 - math.cos(w0))/2/a0) * float(self.COEF_SHIFT))
b1 = int(((1 - math.cos(w0))/a0) * float(self.COEF_SHIFT))
b2 = int(((1 - math.cos(w0))/2/a0) * float(self.COEF_SHIFT))
x0 = 0;
x1 = 0;
y0 = 0;
y1 = 0;
output = []
for x in samples:
acc = x * b0;
acc += x0 * b1
acc += x1 * b2
acc += y0 * (-a1)
acc += y1 * (-a2);
x1 = x0;
x0 = x;
y = acc >> 30;
output.append(y)
y1 = y0
y0 = y
return output
def pi_loop(self, kp, ki, source, _dest= None, _output = None):
integr=self.state()
tmp=self.state()
self._insn(self.MUL, ki, source, move = tmp)
self.nop()
self.nop()
self.nop()
self.nop()
self._insn(self.MAC, 1.0, integr, dest=integr )
self._insn(self.MAC, kp, tmp, dest = _dest, output = _output)
def pi_test(self, kp, ki, samples):
kp_q = int(kp * float(self.COEF_SHIFT))
ki_q = int(ki * 256.0 * float(self.COEF_SHIFT))
integr = 0
output = []
acc = 0
for x in samples:
acc += x >> 8
tmp = (ki_q * acc) >> self.COEF_SHIFT
acc = (tmp + x * kp_q)
y = acc >> 30
output.append(y)
return output
def load_coeffs(filename):
coeffs = []
l = open(filename,"r").readlines()[0]
for cs in l.split(" "):
coeffs.append(float(cs))
return coeffs
def main():
mdsp = MDsp(256, 256)
mdsp.pi_loop(0.2, 0.01, mdsp.input(0), _output=0)
mdsp.nop()
mdsp.nop()
mdsp.nop()
mdsp.nop()
# st = mdsp.state();
# mdsp.biquad_lp(0.7, 1.5e3, 125e6/1024, source = mdsp.input(0), _dest = st )
# mdsp.nop()
# mdsp.nop()
# mdsp.nop()
# mdsp.nop()
# mdsp.fir(load_coeffs("fir_compensator.dat"), st, _output = 0)
# mdsp.fir([1,1,1], mdsp.input(0), _output = 0)
# mdsp.nop()
# mdsp.nop()
# mdsp.nop()
# mdsp.nop()
# mdsp.nop()
# mdsp.nop()
mdsp.finish()
mdsp.nop()
mdsp.nop()
mdsp.nop()
mdsp.nop()
mdsp.nop()
mdsp.nop()
# mdsp.nop()
# mdsp.nop()
# mdsp.nop()
mdsp.dump_sv("dsp_microcode.sv")
mdsp.save("microcode.dat");
samples = range(0, 10000, 100)
y = mdsp.pi_test(0.2, 0.01, samples)
#y = mdsp.biquad_test(0.7, 1.5e3, 125e6/1024, samples)
#y = mdsp.fir_test(load_coeffs("fir_compensator.dat"), y)
print(samples)
print(y)
# print(mdsp.fir_test([ 1, 1, 1 ], samples ))
# print(mdsp.biquad_test(0.7, 1e3, 48e3, samples))
if __name__ == "__main__":
main()
testbench/mdsp/dsp_microcode.sv 0 → 100644
View file @ 1bd30289
uint64_t code[] = '{
64'h2800002000a3d70a,
64'h0000000800000000,
64'h0000000800000000,
64'h0000000800000000,
64'h0000000800000000,
64'h2400401840000000,
64'h100080080ccccccc,
64'h0000000800000000,
64'h0000000800000000,
64'h0000000800000000,
64'h0000000800000000,
64'hc000000800000000,
64'h0000000800000000,
64'h0000000800000000,
64'h0000000800000000,
64'h0000000800000000,
64'h0000000800000000,
64'h0000000800000000};
testbench/mdsp/fir_compensator.dat 0 → 100644
View file @ 1bd30289
-0.00038385 -0.0013273 -0.0015635 0.00091054 0.0047773 0.0039991 -0.0042284 -0.010424 -0.001365 0.016826 0.01661 -0.013276 -0.036778 -0.0081087 0.051718 0.054753 -0.038602 -0.12613 -0.049535 0.20453 0.43998 0.43998 0.20453 -0.049535 -0.12613 -0.038602 0.054753 0.051718 -0.0081087 -0.036778 -0.013276 0.01661 0.016826 -0.001365 -0.010424 -0.0042284 0.0039991 0.0047773 0.00091054 -0.0015635 -0.0013273 -0.00038385
testbench/mdsp/main.sv 0 → 100644
View file @ 1bd30289
`timescale 1ns/1ns
`include "simdrv_defs.svh"
`include "if_wb_master.svh"
module main;
reg clk = 0;
reg rst_n = 0;
reg signed [23:0] x;
wire signed [23:0] y;
wire x_req;
reg x_valid =0;
reg y_req = 1;
int x_data [$];
int out_data[$];
initial #10ns rst_n = 1;
always #1ns clk <= ~clk;
`include "dsp_microcode.sv"
initial begin
int i;
for (i=0;i<10000;i+=100)
x_data.push_back(-100);
end
IWishboneMaster #(32,32)
U_WB (
.clk_i(clk),
.rst_n_i(rst_n)
);
mdsp #(
.g_acc_shift(30)
) DUT (
.clk_i(clk),
.rst_n_i(rst_n),
.x_req_o(x_req),
.x_valid_i(x_valid),
.x_i(x),
.y_valid_o(y_valid),
.y_req_i(y_req),
.y_o(y),
.wb_cyc_i(U_WB.master.cyc),
.wb_stb_i(U_WB.master.stb),
.wb_we_i(U_WB.master.we),
.wb_adr_i(U_WB.master.adr),
.wb_dat_i(U_WB.master.dat_o),
.wb_ack_o(U_WB.master.ack),
.wb_stall_o(U_WB.master.stall)
);
int in_index = 0;
reg [7:0] count =0;
always@(posedge clk)
count <= count + 1;
always@(posedge clk)
if(x_req)// && count < 100)
begin
x_valid <= 1;
x <= x_data[in_index ++];
if(in_index >= x_data.size())
in_index =0;
end else
x_valid <= 0;
always@(posedge clk)
if(y_valid)
$display("%d", y);
initial begin
int i;
CWishboneAccessor acc;
#100ns;
acc = U_WB.get_accessor();
U_WB.settings.addr_gran = BYTE;
for(i=0;i<code.size();i++)
begin
// $display("%16x", code[i]);
acc.write((i*8 + 4) | (1<<11), (code[i]>>32));
acc.write((i*8) | (1<<11), (code[i]>>0));
end
#100ns;
acc.write(0, 0); // un-reset
end // initial begin
endmodule // main
testbench/mdsp/microcode.dat 0 → 100644
View file @ 1bd30289
0x2800002000a3d70a
0x0000000800000000
0x0000000800000000
0x0000000800000000
0x0000000800000000
0x2400401840000000
0x100080080ccccccc
0x0000000800000000
0x0000000800000000
0x0000000800000000
0x0000000800000000
0xc000000800000000
0x0000000800000000
0x0000000800000000
0x0000000800000000
0x0000000800000000
0x0000000800000000
0x0000000800000000
testbench/mdsp/run.do 0 → 100644
View file @ 1bd30289
#make
vlog -sv main.sv +incdir+../../sim +incdir+./gn4124_bfm
vsim -L unisim work.main -voptargs="+acc" -suppress 8684,8683
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
do wave.do
run 1000ns
wave zoomfull
radix -hex
testbench/mdsp/wave.do 0 → 100644
View file @ 1bd30289
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/x_req
add wave -noupdate /main/count
add wave -noupdate /main/x_valid
add wave -noupdate /main/in_index
add wave -noupdate -radix hexadecimal /main/DUT/g_data_bits
add wave -noupdate -radix hexadecimal /main/DUT/g_coef_bits
add wave -noupdate -radix hexadecimal /main/DUT/g_acc_shift
add wave -noupdate -radix hexadecimal /main/DUT/g_state_bits
add wave -noupdate -radix hexadecimal /main/DUT/g_microcode_size
add wave -noupdate -radix hexadecimal /main/DUT/c_acc_width
add wave -noupdate -radix hexadecimal /main/DUT/c_microcode_addr_bits
add wave -noupdate -radix hexadecimal /main/DUT/clk_i
add wave -noupdate -radix hexadecimal /main/DUT/rst_n_i
add wave -noupdate -radix hexadecimal /main/DUT/x_req_o
add wave -noupdate -radix hexadecimal /main/DUT/x_valid_i
add wave -noupdate -radix hexadecimal /main/DUT/x_i
add wave -noupdate -radix hexadecimal /main/DUT/y_valid_o
add wave -noupdate -radix hexadecimal /main/DUT/y_req_i
add wave -noupdate -radix hexadecimal /main/DUT/y_o
add wave -noupdate -radix hexadecimal /main/DUT/stall
add wave -noupdate /main/DUT/pd_use_in
add wave -noupdate -radix hexadecimal /main/DUT/f_use_in
add wave -noupdate /main/DUT/d_use_in
add wave -noupdate -radix hexadecimal /main/DUT/pc
add wave -noupdate /main/DUT/pc_d0
add wave -noupdate -radix hexadecimal /main/DUT/f_didx
add wave -noupdate -radix hexadecimal /main/DUT/f_sidx
add wave -noupdate -radix hexadecimal /main/DUT/f_coef
add wave -noupdate -radix hexadecimal /main/DUT/f_mul_only
add wave -noupdate -radix hexadecimal /main/DUT/f_write_dest
add wave -noupdate -radix hexadecimal /main/DUT/f_write_out
add wave -noupdate -radix hexadecimal /main/DUT/f_store_acc
add wave -noupdate -radix hexadecimal /main/DUT/f_oidx
add wave -noupdate /main/DUT/pd_didx
add wave -noupdate /main/DUT/pd_sidx
add wave -noupdate /main/DUT/pd_coef
add wave -noupdate /main/DUT/pd_mul_only
add wave -noupdate /main/DUT/pd_write_dest
add wave -noupdate /main/DUT/pd_write_out
add wave -noupdate /main/DUT/pd_store_acc
add wave -noupdate /main/DUT/pd_finish
add wave -noupdate /main/DUT/pd_oidx
add wave -noupdate /main/DUT/pd_state
add wave -noupdate -radix hexadecimal /main/DUT/d_didx
add wave -noupdate -radix hexadecimal /main/DUT/d_coef
add wave -noupdate -radix hexadecimal /main/DUT/d_mul_only
add wave -noupdate -radix hexadecimal /main/DUT/d_write_dest
add wave -noupdate -radix hexadecimal /main/DUT/d_write_out
add wave -noupdate -radix hexadecimal /main/DUT/d_store_acc
add wave -noupdate -radix hexadecimal /main/DUT/d_oidx
add wave -noupdate -radix hexadecimal /main/DUT/d_state
add wave -noupdate /main/DUT/d_opcode
add wave -noupdate -radix hexadecimal /main/DUT/e1_didx
add wave -noupdate -radix hexadecimal /main/DUT/e1_write_dest
add wave -noupdate -radix hexadecimal /main/DUT/e1_write_out
add wave -noupdate -radix hexadecimal /main/DUT/e1_store_acc
add wave -noupdate -radix hexadecimal /main/DUT/e1_oidx
add wave -noupdate -radix hexadecimal /main/DUT/e1_state
add wave -noupdate -radix hexadecimal /main/DUT/e2_didx
add wave -noupdate -radix hexadecimal /main/DUT/e2_write_dest
add wave -noupdate -radix hexadecimal /main/DUT/e2_write_out
add wave -noupdate -radix hexadecimal /main/DUT/e2_store_acc
add wave -noupdate -radix hexadecimal /main/DUT/e2_oidx
add wave -noupdate -radix hexadecimal /main/DUT/e2_state
add wave -noupdate -radix hexadecimal /main/DUT/acc0
add wave -noupdate -radix hexadecimal /main/DUT/acc1
add wave -noupdate -radix hexadecimal /main/DUT/acc_trunc
add wave -noupdate -radix hexadecimal /main/DUT/state_mem
add wave -noupdate -radix hexadecimal /main/DUT/reset_wb
add wave -noupdate -radix hexadecimal /main/DUT/rst_n
add wave -noupdate -radix hexadecimal /main/DUT/clk_i
add wave -noupdate -radix hexadecimal /main/DUT/rst_n_i
add wave -noupdate -radix hexadecimal /main/DUT/x_req_o
add wave -noupdate -radix hexadecimal /main/DUT/x_valid_i
add wave -noupdate -radix hexadecimal /main/DUT/x_i
add wave -noupdate -radix hexadecimal /main/DUT/y_valid_o
add wave -noupdate -radix hexadecimal /main/DUT/y_req_i
add wave -noupdate -radix hexadecimal /main/DUT/y_o
add wave -noupdate -radix hexadecimal /main/DUT/wb_cyc_i
add wave -noupdate -radix hexadecimal /main/DUT/wb_stb_i
add wave -noupdate -radix hexadecimal /main/DUT/wb_we_i
add wave -noupdate -radix hexadecimal /main/DUT/wb_adr_i
add wave -noupdate -radix hexadecimal /main/DUT/wb_dat_i
add wave -noupdate -radix hexadecimal /main/DUT/wb_dat_o
add wave -noupdate -radix hexadecimal /main/DUT/wb_stall_o
add wave -noupdate -radix hexadecimal /main/DUT/wb_ack_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {725 ns} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {365 ns} {893 ns}
testbench/pi_control/Manifest.py 0 → 100644
View file @ 1bd30289
action= "simulation"
target= "xilinx"
fetchto="../../ip_cores"
modules = { "local" : [ "../../top" ] }
files = ["main.sv"]
vlog_opt="+incdir+../../sim +incdir+gn4124_bfm"
testbench/pi_control/main.sv 0 → 100644
View file @ 1bd30289
`timescale 1ns/1ns
`include "simdrv_defs.svh"
`include "if_wb_master.svh"
module main;
reg clk = 0;
reg rst_n = 0;
reg [15:0] x;
wire [15:0] y;
wire x_req;
reg x_valid =0;
reg y_req = 1;
int x_data [$];
int out_data[$];
initial #10ns rst_n = 1;
always #1ns clk <= ~clk;
initial begin
int i;
for (i=0;i<10000;i+=100) begin
x_data.push_back(10000);
x_data.push_back(50000);
end
end
const real kp = 0.002;
const real ki = 0.000001;
const int kp_q = kp * 65536.0;
const int ki_q = ki * 65536.0 * 1024.0;
task automatic sim_pi(real kp, real ki, int x[$], ref int y[$]);
int i;
real acc = 0.0;
for (i = 0; i < x.size(); i++)
begin
acc += x[i];
y.push_back(int'(acc * ki + real'(x[i]) * kp));
end
endtask // sim_pi
reg [15:0] c_kp;
IWishboneMaster #(32,32)
U_WB (
.clk_i(clk),
.rst_n_i(rst_n)
);
pi_control DUT (
.clk_i(clk),
.rst_n_i(rst_n),
.d_valid_i(x_valid),
.d_i(x),
.q_valid_o(y_valid),
.q_o(y),
.ki_i(ki_q),
.kp_i(kp_q)
);
int in_index = 0;
always@(posedge clk)
begin
x_valid <= 1;
x <= x_data[in_index ++];
if(in_index >= x_data.size())
in_index =0;
end
always@(posedge clk)
if(y_valid)
$display("%d", y);
endmodule // main
testbench/pi_control/run.do 0 → 100644
View file @ 1bd30289
#make
vlog -sv main.sv +incdir+../../sim +incdir+./gn4124_bfm
vsim -L unisim work.main -voptargs="+acc" -suppress 8684,8683
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
do wave.do
run 1000ns
wave zoomfull
radix -hex
testbench/pi_control/wave.do 0 → 100644
View file @ 1bd30289
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/g_goal
add wave -noupdate /main/DUT/g_acc_shift
add wave -noupdate /main/DUT/clk_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/d_valid_i
add wave -noupdate /main/DUT/d_i
add wave -noupdate /main/DUT/q_valid_o
add wave -noupdate /main/DUT/q_o
add wave -noupdate /main/DUT/ki_i
add wave -noupdate /main/DUT/kp_i
add wave -noupdate /main/DUT/acc
add wave -noupdate /main/DUT/err
add wave -noupdate /main/DUT/d0
add wave -noupdate /main/DUT/d1
add wave -noupdate /main/DUT/stage
add wave -noupdate /main/DUT/ds
add wave -noupdate /main/DUT/acc0
add wave -noupdate /main/DUT/term_p
add wave -noupdate /main/DUT/term_i
add wave -noupdate /main/DUT/sum
add wave -noupdate /main/DUT/clk_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/d_valid_i
add wave -noupdate /main/DUT/d_i
add wave -noupdate /main/DUT/q_valid_o
add wave -noupdate /main/DUT/q_o
add wave -noupdate /main/DUT/ki_i
add wave -noupdate /main/DUT/kp_i
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {38 ns} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ns} {132 ns}
testbench/top/Manifest.py 0 → 100644
View file @ 1bd30289
action= "simulation"
target= "xilinx"
fetchto="../../ip_cores"
modules = { "local" : [ "../../top", "gn4124_bfm" ] }
files = ["main.sv"]
vlog_opt="+incdir+../../sim +incdir+gn4124_bfm"
testbench/top/gn4124_bfm/Manifest.py 0 → 100644
View file @ 1bd30289
files = ["mem_model.vhd", "textutil.vhd", "gn412x_bfm.vhd", "util.vhd"]
testbench/top/gn4124_bfm/gn4124_bfm.svh 0 → 100644
View file @ 1bd30289
/* Crude wrapper for Gennum-provided GN4124x BFM. Supports only single CSR reads/writes so far. */
`ifndef __GN4124_BFM_SVH
`define __GN4124_BFM_SVH 1
`include "simdrv_defs.svh"
interface IGN4124PCIMaster;
int cmd_str_int[256];
reg cmd_req = 0;
wire cmd_ack;
reg internal_rstn = 0;
wire lclk_p, lclk_n, l2p_clk_p, l2p_clk_n, p2l_clk_p, p2l_clk_n;
wire [15:0] l2p_data, p2l_data;
wire l2p_dframe, l2p_valid, l2p_edb;
wire p2l_dframe, p2l_valid, p2l_rdy;
wire [1:0] l_wr_rdy, p_rd_d_rdy;
wire [1:0] p_wr_req, p_wr_rdy, vc_rdy;
wire l2p_rdy, tx_error, rx_error;
wire [15:0] gpio;
// Local bus to Gennum
modport L2P
(
input l2p_clk_n,
input l2p_clk_p,
input l2p_data,
input l2p_dframe,
input l2p_valid,
input l2p_edb,
output l_wr_rdy,
output p_rd_d_rdy,
output l2p_rdy,
output tx_error
);
// Gennum to local bus
modport P2L
(
output p2l_clk_p,
output p2l_clk_n,
output p2l_dframe,
output p2l_data,
output p2l_valid,
input p2l_rdy,
output p_wr_req,
input p_wr_rdy,
input rx_error,
output vc_rdy
);
wire rst_n;
modport SYS
(
output lclk_p,
output lclk_n,
output rst_n,
inout gpio);
wire [31:0] cmd_rddata;
wire cmd_rddata_valid;
GN412X_BFM
U_BFM (
.CMD_INT (cmd_str_int),
.CMD_REQ (cmd_req),
.CMD_ACK (cmd_ack),
.CMD_CLOCK_EN (1'b1),
.CMD_RD_DATA(cmd_rddata),
.CMD_RD_DATA_VALID(cmd_rddata_valid),
.RSTINn (internal_rstn),
.RSTOUT33n(rst_n),
.LCLK (lclk_p),
.LCLKn (lclk_n),
.L2P_CLKp (l2p_clk_p),
.L2P_CLKn (l2p_clk_n),
.L2P_DATA (l2p_data),
.L2P_DFRAME (l2p_dframe),
.L2P_VALID (l2p_valid),
.L2P_EDB (l2p_edb),
.L_WR_RDY (l_wr_rdy),
.P_RD_D_RDY (p_rd_d_rdy),
.L2P_RDY (l2p_rdy),
.TX_ERROR (tx_error),
.P2L_CLKp (p2l_clk_p),
.P2L_CLKn (p2l_clk_n),
.P2L_DATA (p2l_data),
.P2L_DFRAME (p2l_dframe),
.P2L_VALID (p2l_valid),
.P2L_RDY (p2l_rdy),
.P_WR_REQ (p_wr_req),
.P_WR_RDY (p_wr_rdy),
.RX_ERROR (rx_error),
.VC_RDY (vc_rdy),
.GPIO (gpio)
);
int line_no = 1;
task send_cmd(string cmd);
int i;
string cmd_2;
$sformat(cmd_2, "%-1d %s", line_no++, cmd);
// $display("SendCmd '%s'", cmd_2);
for(i=0;i<cmd_2.len(); i++)
cmd_str_int[i] = int'(cmd_2[i]);
cmd_str_int[i] = 0;
#10ns;
cmd_req = 1;
while(!cmd_ack) #1ns;
cmd_req = 0;
while(cmd_ack) #1ns;
#10ns;
endtask // send_cmd
bit ready = 0;
task init();
#100ns;
internal_rstn <= 1;
#100ns;
send_cmd("init");
send_cmd("reset %d16");
send_cmd("bar 0 FF00000000000000 08000000 0 7 0");
send_cmd("bfm_bar 0 0000000040000000 20000000");
send_cmd("bfm_bar 1 0000000020000000 20000000");
send_cmd("wait %d64");
ready = 1;
// send_cmd("wr FF000000000A0004 F 007C0270");
// send_cmd("rd FF000000000A0004 F");
endtask // init
initial init();
task automatic readback(ref uint64_t value);
@(posedge cmd_rddata_valid);
value = cmd_rddata;
@(negedge cmd_rddata_valid);
endtask // readback
class CBusAccessor_Gennum extends CBusAccessor;
function new();
endfunction // new
task writem(uint64_t addr[], uint64_t data[], input int size, ref int result);
string cmd;
int i;
if(size != 4)
$fatal("CBusAccessor_Gennum: only size=4 supported");
for(i=0;i<addr.size();i++)
begin
$sformat(cmd,"wr FF000000%08X F %08X", addr[i], data[i]);
send_cmd(cmd);
end
endtask // writem
task readm(uint64_t addr[], ref uint64_t data[], input int size, ref int result);
string cmd;
int i;
uint64_t tmp;
if(size != 4)
$fatal("CBusAccessor_Gennum: only size=4 supported");
for(i=0;i<addr.size();i++)
begin
$sformat(cmd,"rd FF000000%08X F", addr[i]);
fork
send_cmd(cmd);
readback(tmp);
join
data[i] = tmp;
end
endtask // readm
endclass // CBusAccessor_Gennum
function CBusAccessor get_accessor();
CBusAccessor_Gennum g = new;
return g;
endfunction
endinterface
/* Helper macro for wiring Gennum-Xilinx ports in spec_top */
`define GENNUM_WIRE_SPEC_PINS(IF_NAME) \
.L_RST_N (IF_NAME.SYS.rst_n),\
// .L_CLKp (IF_NAME.SYS.lclk_p),\
// .L_CLKn (IF_NAME.SYS.lclk_n),\
.p2l_clkp (IF_NAME.P2L.p2l_clk_p),\
.p2l_clkn (IF_NAME.P2L.p2l_clk_n),\
.p2l_data (IF_NAME.P2L.p2l_data),\
.p2l_dframe (IF_NAME.P2L.p2l_dframe),\
.p2l_valid (IF_NAME.P2L.p2l_valid),\
.p2l_rdy (IF_NAME.P2L.p2l_rdy),\
.p_wr_req (IF_NAME.P2L.p_wr_req),\
.p_wr_rdy (IF_NAME.P2L.p_wr_rdy),\
.rx_error (IF_NAME.P2L.rx_error),\
.l2p_clkp (IF_NAME.L2P.l2p_clk_p),\
.l2p_clkn (IF_NAME.L2P.l2p_clk_n),\
.l2p_data (IF_NAME.L2P.l2p_data),\
.l2p_dframe (IF_NAME.L2P.l2p_dframe),\
.l2p_valid (IF_NAME.L2P.l2p_valid),\
.l2p_edb (IF_NAME.L2P.l2p_edb),\
.l2p_rdy (IF_NAME.L2P.l2p_rdy),\
.l_wr_rdy (IF_NAME.L2P.l_wr_rdy),\
.p_rd_d_rdy (IF_NAME.L2P.p_rd_d_rdy),\
.tx_error (IF_NAME.L2P.tx_error),\
.vc_rdy (IF_NAME.P2L.vc_rdy)
`endif // `ifndef __GN4124_BFM_SVH
testbench/top/gn4124_bfm/gn412x_bfm.vhd 0 → 100644
View file @ 1bd30289
This source diff could not be displayed because it is too large. You can view the blob instead.
testbench/top/gn4124_bfm/mem_model.vhd 0 → 100644
View file @ 1bd30289
This source diff could not be displayed because it is too large. You can view the blob instead.
testbench/top/gn4124_bfm/textutil.vhd 0 → 100644
View file @ 1bd30289
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
use work.util.all;
-----------------------------------------------------------------------------
-- *Module : textutil
--
-- *Description : Improved Free-format string and line manipulation
--
-- *History: M. Alford (originaly created 1993 with subsequent updates)
-----------------------------------------------------------------------------
package textutil is
procedure read_token(L : inout line; X : out STRING);
procedure sget_token(S : in string; P : inout integer; X : out STRING);
procedure sget_vector(S : in string; P : inout integer; VEC : out STD_ULOGIC_VECTOR);
procedure sget_vector_64(S : in string; P : inout integer; VEC : out STD_ULOGIC_VECTOR);
procedure sget_int(S : in string; P : inout integer; X : out integer);
function hex_char_to_vector(C : in character) return STD_ULOGIC_VECTOR;
function vector_to_hex_char(V : in STD_ULOGIC_VECTOR) return character;
function is_hex(C : in character) return BOOLEAN;
function hex_char_to_int(C : in character) return integer;
procedure read_vector(L : inout line; VEC : out STD_ULOGIC_VECTOR);
procedure read_int(L : inout line; I : out integer);
procedure write_hex_vector(L : inout line; V : in STD_ULOGIC_VECTOR);
function to_str(constant V: in STD_ULOGIC_VECTOR) return STRING;
function to_str(constant V: in STD_ULOGIC) return STRING;
function to_str(constant val : in INTEGER) return STRING;
function to_strn(constant val : in INTEGER; constant n : in INTEGER) return STRING;
end textutil;
package body textutil is
-----------------------------------------------------------------------------
-- *Module : read_token
--
-- *Description : Skip over spaces then load a token string from a line
-- until either the string is full or the token is finished
-- (i.e. another space). The output string is padded out
-- with blanks at the end if the token length is less then
-- the full string length.
-----------------------------------------------------------------------------
procedure read_token(L : inout line; X : out STRING) is
variable char : character;
begin
if(L'length > 0) then
char := ' ';
while((char = ' ') and (L'length > 0)) loop -- Skip spaces
read(L, char);
end loop;
for i in X'low to X'high loop
X(i) := char;
if(char /= ' ') then
if(L'length > 0) then
read(L, char);
else
char := ' ';
end if;
end if;
end loop;
else
assert false report "Couldn't read a token from file"
severity error;
end if;
end read_token;
-----------------------------------------------------------------------------
-- *Module : sget_token
--
-- *Description : Same as read_token except for strings.
-----------------------------------------------------------------------------
procedure sget_token(S : in string; P : inout integer; X : out STRING) is
variable char : character;
begin
if(S'length > P) then
char := ' ';
while((char = ' ') and (S'length >= P)) loop -- Skip spaces
char := S(P);
P := P + 1;
end loop;
for i in X'low to X'high loop
X(i) := char;
if(char /= ' ') then
if(S'length > P) then
char := S(P);
P := P + 1;
else
char := ' ';
end if;
end if;
end loop;
else
assert false report "Couldn't read a token from a string"
severity error;
end if;
end sget_token;
-----------------------------------------------------------------------------
-- *Module : hex_char_to_vector
--
-- *Description : Convert a hex character to a vector
-----------------------------------------------------------------------------
function hex_char_to_vector(C : in character) return STD_ULOGIC_VECTOR is
variable X : STD_ULOGIC_VECTOR( 3 downto 0);
begin
case C is
when '0' => X := "0000";
when '1' => X := "0001";
when '2' => X := "0010";
when '3' => X := "0011";
when '4' => X := "0100";
when '5' => X := "0101";
when '6' => X := "0110";
when '7' => X := "0111";
when '8' => X := "1000";
when '9' => X := "1001";
when 'A' => X := "1010";
when 'B' => X := "1011";
when 'C' => X := "1100";
when 'D' => X := "1101";
when 'E' => X := "1110";
when 'F' => X := "1111";
when 'a' => X := "1010";
when 'b' => X := "1011";
when 'c' => X := "1100";
when 'd' => X := "1101";
when 'e' => X := "1110";
when 'f' => X := "1111";
when others =>
X := "0000";
assert false report "Invalid Hex Character"
severity error;
end case;
return(X);
end hex_char_to_vector;
-----------------------------------------------------------------------------
-- *Module : vector_to_hex_char
--
-- *Description : Convert a vector to a hex character. Only uses low 4 bits.
-----------------------------------------------------------------------------
function vector_to_hex_char(V : in STD_ULOGIC_VECTOR) return character is
variable C : character;
variable VV : STD_ULOGIC_VECTOR(3 downto 0);
begin
if(V'length < 4) then
VV := To_X01(V(V'low + 3 downto V'low));
else
VV := To_X01(V(V'low + V'length - 1 downto V'low));
end if;
case VV is
when "0000" => C := '0';
when "0001" => C := '1';
when "0010" => C := '2';
when "0011" => C := '3';
when "0100" => C := '4';
when "0101" => C := '5';
when "0110" => C := '6';
when "0111" => C := '7';
when "1000" => C := '8';
when "1001" => C := '9';
when "1010" => C := 'A';
when "1011" => C := 'B';
when "1100" => C := 'C';
when "1101" => C := 'D';
when "1110" => C := 'E';
when "1111" => C := 'F';
when others => C := 'X';
end case;
return(C);
end vector_to_hex_char;
-----------------------------------------------------------------------------
-- *Module : is_hex
--
-- *Description : report if a char is ASCII hex
-----------------------------------------------------------------------------
function is_hex(C : in character) return BOOLEAN is
variable X : boolean;
begin
case C is
when '0' => X := TRUE;
when '1' => X := TRUE;
when '2' => X := TRUE;
when '3' => X := TRUE;
when '4' => X := TRUE;
when '5' => X := TRUE;
when '6' => X := TRUE;
when '7' => X := TRUE;
when '8' => X := TRUE;
when '9' => X := TRUE;
when 'A' => X := TRUE;
when 'B' => X := TRUE;
when 'C' => X := TRUE;
when 'D' => X := TRUE;
when 'E' => X := TRUE;
when 'F' => X := TRUE;
when 'a' => X := TRUE;
when 'b' => X := TRUE;
when 'c' => X := TRUE;
when 'd' => X := TRUE;
when 'e' => X := TRUE;
when 'f' => X := TRUE;
when others =>
X := FALSE;
end case;
return(X);
end is_hex;
-----------------------------------------------------------------------------
-- *Module : hex_char_to_int
--
-- *Description : Convert a hex character to an integer
-----------------------------------------------------------------------------
function hex_char_to_int(C : in character) return integer is
variable X : integer;
begin
case C is
when '0' => X := 0;
when '1' => X := 1;
when '2' => X := 2;
when '3' => X := 3;
when '4' => X := 4;
when '5' => X := 5;
when '6' => X := 6;
when '7' => X := 7;
when '8' => X := 8;
when '9' => X := 9;
when 'A' => X := 10;
when 'B' => X := 11;
when 'C' => X := 12;
when 'D' => X := 13;
when 'E' => X := 14;
when 'F' => X := 15;
when 'a' => X := 10;
when 'b' => X := 11;
when 'c' => X := 12;
when 'd' => X := 13;
when 'e' => X := 14;
when 'f' => X := 15;
when others =>
X := 0;
assert false report "Invalid Hex Character"
severity error;
end case;
return(X);
end hex_char_to_int;
-----------------------------------------------------------------------------
-- *Module : read_vector
--
-- *Description : load a vector from the input line in a free floating format
-----------------------------------------------------------------------------
procedure read_vector(L : inout line; VEC : out STD_ULOGIC_VECTOR) is
variable char : character;
variable base : integer;
variable q : integer;
variable v : STD_ULOGIC_VECTOR(31 downto 0);
begin
if(L'length > 0) then
char := ' ';
while(char = ' ') loop -- Skip spaces
read(L, char);
end loop;
base := 16; -- Hex is the default
if(char = '%') then -- determine base
read(L, char);
if(char = 'b' or char = 'B') then
base := 2;
elsif(char = 'x' or char = 'X') then
base := 16;
elsif(char = 'd' or char = 'D') then
base := 10;
else
assert false report "Unsupported Base detected when reading a Vector"
severity error;
end if;
read(L, char);
end if;
q := 0;
if(is_hex(char)) then
q := q * base + hex_char_to_int(char);
while(is_hex(char) and not (L'length = 0)) loop
read(L, char);
if(is_hex(char)) then
q := q * base + hex_char_to_int(char);
end if;
end loop;
end if;
if(q < 0) then
q := q-2147483648;
V(30 downto 0) := to_vector(q, 31);
V(31) := '1';
else
V(30 downto 0) := to_vector(q, 31);
V(31) := '0';
end if;
VEC := V((VEC'high - VEC'low) downto 0);
else
assert false report "Couldn't read a vector"
severity error;
end if;
end read_vector;
-----------------------------------------------------------------------------
-- *Module : sget_vector
--
-- *Description : Same as sget_vector except for strings
-----------------------------------------------------------------------------
procedure sget_vector(S : in string; P : inout integer; VEC : out STD_ULOGIC_VECTOR) is
variable char : character;
variable base : integer;
variable q : integer;
variable v : STD_ULOGIC_VECTOR(31 downto 0);
begin
while(S(P) = ' ') loop -- Skip spaces
if(P >= S'length) then
P := S'length;
exit;
end if;
P := P + 1;
end loop;
if(S'length > P) then
char := S(P);
if(char = '"') then -- read in as a literal
q := v'high;
v := (others => 'U');
VEC := v(VEC'range);
char := ' ';
P := P + 1;
while((char /= '"') and not (S'length = P)) loop
char := S(P);
P := P + 1;
case char is
when '0' =>
v(q) := '0';
when '1' =>
v(q) := '1';
when 'L' | 'l' =>
v(q) := 'L';
when 'H' | 'h' =>
v(q) := 'H';
when 'Z' | 'z' =>
v(q) := 'Z';
when 'X' | 'x' =>
v(q) := 'X';
when 'U' | 'u' =>
v(q) := 'U';
when others =>
-- char := '"';
exit;
end case;
q := q - 1;
end loop;
if(v'high-q < 2) then -- only a single bit was read
VEC(VEC'low) := v(v'high);
elsif((v'high - q) > VEC'length) then -- too many bits
VEC := v(q+VEC'length downto q+1);
else -- the number of bits read is same or less than required
VEC(v'high-q-1+VEC'low downto VEC'low) := v(v'high downto q+1);
end if;
else
base := 16; -- Hex is the default
if(char = '%') then -- determine base
P := P + 1;
char := S(P);
P := P + 1;
if(char = 'b' or char = 'B') then
base := 2;
elsif(char = 'x' or char = 'X') then
base := 16;
elsif(char = 'd' or char = 'D') then
base := 10;
else
assert false report "Unsupported Base detected when reading a Vector"
severity error;
end if;
elsif((char = '0') and ((S(P+1) = 'x') or (S(P+1) = 'X'))) then
P := P + 2;
end if;
q := 0;
char := S(P);
if(is_hex(char)) then
while(is_hex(char) and not (S'length = P)) loop
if(is_hex(char)) then
q := q * base + hex_char_to_int(char);
end if;
P := P + 1;
char := S(P);
end loop;
end if;
if(q < 0) then
q := q-2147483648;
V(30 downto 0) := to_vector(q, 31);
V(31) := '1';
else
V(30 downto 0) := to_vector(q, 31);
V(31) := '0';
end if;
VEC := V((VEC'high - VEC'low) downto 0);
end if;
else
assert false report "Couldn't read a vector"
severity error;
V := (others => '0');
VEC := V((VEC'high - VEC'low) downto 0);
end if;
end sget_vector;
-----------------------------------------------------------------------------
-- *Module : sget_vector_64
--
-- *Description : Same as sget_vector except can handle 64 bit quantities and hex or binary base (no base 10)
-----------------------------------------------------------------------------
procedure sget_vector_64(S : in string; P : inout integer; VEC : out STD_ULOGIC_VECTOR) is
variable char : character;
variable base : integer;
variable q : integer;
variable v : STD_ULOGIC_VECTOR(63 downto 0);
begin
while(S(P) = ' ') loop -- Skip spaces
if(P >= S'length) then
P := S'length;
exit;
end if;
P := P + 1;
end loop;
if(S'length > P) then
char := S(P);
if(char = '"') then -- read in as a literal
q := v'high;
v := (others => 'U');
VEC := v(VEC'range);
char := ' ';
P := P + 1;
while((char /= '"') and not (S'length = P)) loop
char := S(P);
P := P + 1;
case char is
when '0' =>
v(q) := '0';
when '1' =>
v(q) := '1';
when 'L' | 'l' =>
v(q) := 'L';
when 'H' | 'h' =>
v(q) := 'H';
when 'Z' | 'z' =>
v(q) := 'Z';
when 'X' | 'x' =>
v(q) := 'X';
when 'U' | 'u' =>
v(q) := 'U';
when others =>
-- char := '"';
exit;
end case;
q := q - 1;
end loop;
if(v'high-q < 2) then -- only a single bit was read
VEC(VEC'low) := v(v'high);
elsif((v'high - q) > VEC'length) then -- too many bits
VEC := v(q+VEC'length downto q+1);
else -- the number of bits read is same or less than required
VEC(v'high-q-1+VEC'low downto VEC'low) := v(v'high downto q+1);
end if;
else
base := 16; -- Hex is the default
if(char = '%') then -- determine base
P := P + 1;
char := S(P);
P := P + 1;
if(char = 'b' or char = 'B') then
base := 2;
elsif(char = 'x' or char = 'X') then
base := 16;
else
assert false report "Unsupported Base detected when reading a Vector"
severity error;
end if;
char := S(P);
-- P := P + 1;
elsif((char = '0') and ((S(P+1) = 'x') or (S(P+1) = 'X'))) then
P := P + 2;
end if;
v := (others => '0');
char := S(P);
if(base = 2) then
while(((char = '0') or (char = '1')) and not (P > S'length)) loop
if(char = '0') then
v := v(v'high-1 downto 0) & '0';
else
v := v(v'high-1 downto 0) & '1';
end if;
P := P + 1;
char := S(P);
end loop;
else
while(is_hex(char) and not (P > S'length)) loop
if(is_hex(char)) then
v := v(v'high-4 downto 0) & hex_char_to_vector(char);
end if;
P := P + 1;
char := S(P);
end loop;
end if;
VEC := V((VEC'high - VEC'low) downto 0);
end if;
else
assert false report "Couldn't read a vector"
severity error;
V := (others => '0');
VEC := V((VEC'high - VEC'low) downto 0);
end if;
end sget_vector_64;
-----------------------------------------------------------------------------
-- *Module : read_int
--
-- *Description : load an integer from the input line in a free floating format
-----------------------------------------------------------------------------
procedure read_int(L : inout line; I : out integer) is
variable char : character;
variable base : integer;
variable q : integer;
begin
if(L'length > 0) then
char := ' ';
while(char = ' ') loop -- Skip spaces
read(L, char);
end loop;
base := 16; -- Hex is the default
if(char = '%') then -- determine base
read(L, char);
if(char = 'b' or char = 'B') then
base := 2;
elsif(char = 'x' or char = 'X') then
base := 16;
elsif(char = 'd' or char = 'D') then
base := 10;
else
assert false report "Unsupported Base detected when reading an integer"
severity error;
end if;
read(L, char);
end if;
q := 0;
if(is_hex(char)) then
q := q * base + hex_char_to_int(char);
while(is_hex(char) and not (L'length = 0)) loop
read(L, char);
if(is_hex(char)) then
q := q * base + hex_char_to_int(char);
end if;
end loop;
end if;
I := q;
else
assert false report "Couldn't read an integer"
severity error;
end if;
end read_int;
-----------------------------------------------------------------------------
-- *Module : sget_int
--
-- *Description : Same as read_int except for strings
-----------------------------------------------------------------------------
procedure sget_int(S : in string; P : inout integer; X : out integer) is
variable char : character;
variable base : integer;
variable q : integer;
begin
if(S'length > P) then
char := ' ';
while(char = ' ') loop -- Skip spaces
char := S(P);
P := P + 1;
end loop;
base := 16; -- Hex is the default
if(char = '%') then -- determine base
char := S(P);
P := P + 1;
if(char = 'b' or char = 'B') then
base := 2;
elsif(char = 'x' or char = 'X') then
base := 16;
elsif(char = 'd' or char = 'D') then
base := 10;
else
assert false report "Unsupported Base detected when reading an integer"
severity error;
end if;
char := S(P);
P := P + 1;
end if;
q := 0;
if(is_hex(char)) then
q := q * base + hex_char_to_int(char);
while(is_hex(char) and not (S'length = P)) loop
char := S(P);
P := P + 1;
if(is_hex(char)) then
q := q * base + hex_char_to_int(char);
end if;
end loop;
end if;
X := q;
else
assert false report "Couldn't read an integer"
severity error;
end if;
end sget_int;
-----------------------------------------------------------------------------
-- *Module : write_hex_vector
--
-- *Description : writes out a vector as hex
-----------------------------------------------------------------------------
procedure write_hex_vector(L : inout line; V : in STD_ULOGIC_VECTOR) is
variable C : character;
variable VV : STD_ULOGIC_VECTOR(((V'length + 3)/4) * 4 - 1 downto 0);
begin
VV := (others => '0');
VV(V'length -1 downto 0) := V;
for i in VV'length/4 - 1 downto 0 loop
C := vector_to_hex_char(VV(i*4+3 downto i*4));
write(L, C);
end loop;
end write_hex_vector;
-----------------------------------------------------------------------------
-- *Module : to_str
--
-- *Description : Converts a STD_ULOGIC_VECTOR to a string of the same length
-----------------------------------------------------------------------------
function to_str(constant V: in STD_ULOGIC_VECTOR) return STRING is
variable S : STRING(1 to V'length);
variable sp : integer;
begin
sp := 1;
for i in V'range loop
case V(i) is
when '1' | 'H' =>
S(sp) := '1';
when '0' | 'L' =>
S(sp) := '0';
when others =>
S(sp) := 'X';
end case;
sp := sp + 1;
end loop;
return(S);
end to_str;
-----------------------------------------------------------------------------
-- *Module : to_str
--
-- *Description : Converts a STD_ULOGIC to a string
-----------------------------------------------------------------------------
function to_str(constant V: in STD_ULOGIC) return STRING is
-- variable S : STRING(1);
begin
case V is
when '1' | 'H' =>
return("1");
when '0' | 'L' =>
return("0");
when others =>
return("X");
end case;
return("X");
end to_str;
-----------------------------------------------------------------------------
-- *Module : to_str
--
-- *Description : Converts a integer to a string
-----------------------------------------------------------------------------
function to_str(constant val : in INTEGER) return STRING is
variable result : STRING(11 downto 1) := "-2147483648"; -- smallest integer and longest string
variable tmp : INTEGER;
variable pos : NATURAL := 1;
variable digit : NATURAL;
begin
-- for the smallest integer MOD does not seem to work...
--if val = -2147483648 then : compilation error with Xilinx tools...
if val < -2147483647 then
pos := 12;
else
tmp := abs(val);
loop
digit := abs(tmp MOD 10);
tmp := tmp / 10;
result(pos) := character'val(character'pos('0') + digit);
pos := pos + 1;
exit when tmp = 0;
end loop;
if val < 0 then
result(pos) := '-';
pos := pos + 1;
end if;
end if;
return result((pos-1) downto 1);
end to_str;
-----------------------------------------------------------------------------
-- *Module : to_strn
--
-- *Description : Converts an integer to a string of length N
-----------------------------------------------------------------------------
function to_strn(constant val : in INTEGER; constant n : in INTEGER) return STRING is
variable result : STRING(11 downto 1) := "-2147483648"; -- smallest integer and longest string
variable tmp : INTEGER;
variable pos : NATURAL := 1;
variable digit : NATURAL;
begin
-- for the smallest integer MOD does not seem to work...
--if val = -2147483648 then : compilation error with Xilinx tools...
if val < -2147483647 then
pos := 12;
else
result := (others => ' ');
tmp := abs(val);
loop
digit := abs(tmp MOD 10);
tmp := tmp / 10;
result(pos) := character'val(character'pos('0') + digit);
pos := pos + 1;
exit when tmp = 0;
end loop;
if val < 0 then
result(pos) := '-';
pos := pos + 1;
end if;
end if;
return result(n downto 1);
end to_strn;
end textutil;
testbench/top/gn4124_bfm/util.vhd 0 → 100644
View file @ 1bd30289
library ieee;
use ieee.std_logic_1164.all;
--library synopsys;
--use synopsys.arithmetic.all;
package UTIL is
type t_cmd_array is array (1 to 256) of integer;
function to_mvl ( b: in boolean ) return STD_ULOGIC;
function to_mvl ( i: in integer ) return STD_ULOGIC;
function to_vector(input,num_bits:integer) return STD_ULOGIC_VECTOR;
-- function to_signed( b: in std_ulogic_vector ) return signed;
-- function to_std_ulogic_vector( b: in signed ) return std_ulogic_vector;
-- function std_logic_to_std_ulogic( b: in std_logic ) return std_ulogic;
-- function std_ulogic_to_std_logic( b: in std_ulogic ) return std_logic;
function "and"(l: STD_ULOGIC_VECTOR; r: STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and"(l: STD_ULOGIC; r: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "and"(l: STD_ULOGIC_VECTOR; r: BOOLEAN) return STD_ULOGIC_VECTOR;
function "and"(l: BOOLEAN; r: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "and"(l: BOOLEAN; r: STD_ULOGIC) return STD_ULOGIC;
function "and"(l: STD_ULOGIC; r: BOOLEAN) return STD_ULOGIC;
function exp(input: STD_ULOGIC; num_bits: integer) return STD_ULOGIC_VECTOR;
function exp(input: STD_ULOGIC_VECTOR; num_bits: integer) return STD_ULOGIC_VECTOR;
function conv_integer ( ARG: in STD_ULOGIC_VECTOR ) return integer;
function "+"(l: STD_ULOGIC_VECTOR; r: STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- function "+"(l: STD_ULOGIC_VECTOR; r: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- function "-"(l: STD_ULOGIC_VECTOR; r: STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- function "-"(l: STD_ULOGIC_VECTOR; r: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function to_int(l: std_ulogic_vector) return natural;
function to_int(l: std_ulogic) return natural;
function and_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC;
function or_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC;
function ge ( l, r : STD_ULOGIC_VECTOR ) return BOOLEAN;
function gt ( l, r : STD_ULOGIC_VECTOR ) return BOOLEAN;
function lt ( l, r : STD_ULOGIC_VECTOR ) return BOOLEAN;
function eq ( l, r : STD_ULOGIC_VECTOR ) return BOOLEAN;
function maximum ( arg1, arg2 : INTEGER) return INTEGER;
function minimum ( arg1, arg2 : INTEGER) return INTEGER;
procedure keep(signal X: inout STD_LOGIC);
function log2(A: in integer) return integer;
-------------------------------------------------------------------
-- Declaration of Synthesis directive attributes
-------------------------------------------------------------------
ATTRIBUTE synthesis_return : string ;
end UTIL;
package body UTIL is
--------------------------------------------------------------------
-- function to_signed ( b: in std_ulogic_vector ) return signed is
-- variable result : signed(b'range);
-- begin
-- for i in b'range loop
-- result(i) := b(i);
-- end loop;
-- return result;
-- end to_signed;
--------------------------------------------------------------------
-- function to_std_ulogic_vector ( b: in signed ) return std_ulogic_vector is
-- variable result : std_ulogic_vector(b'range);
-- begin
-- for i in b'range loop
-- result(i) := b(i);
-- end loop;
-- return result;
-- end to_std_ulogic_vector;
--------------------------------------------------------------------
function to_mvl ( b: in boolean ) return STD_ULOGIC is
begin
if ( b = TRUE ) then
return( '1' );
else
return( '0' );
end if;
end to_mvl;
--------------------------------------------------------------------
function to_mvl ( i: in integer ) return STD_ULOGIC is
begin
if ( i = 1 ) then
return( '1' );
else
return( '0' );
end if;
end to_mvl;
--------------------------------------------------------------------
function "and"(l: STD_ULOGIC; r: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
variable rr: STD_ULOGIC_vector(r'range);
begin
if (l = '1') then
rr := r;
else
rr := (others => '0');
end if;
return(rr);
end;
--------------------------------------------------------------------
function "and"(l: STD_ULOGIC_VECTOR; r: STD_ULOGIC) return STD_ULOGIC_VECTOR is
variable ll: STD_ULOGIC_vector(l'range);
begin
if (r = '1') then
ll := l;
else
ll := (others => '0');
end if;
return(ll);
end;
--------------------------------------------------------------------
function "and"(l: BOOLEAN; r: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
variable rr: STD_ULOGIC_vector(r'range);
begin
if (l) then
rr := r;
else
rr := (others => '0');
end if;
return(rr);
end;
--------------------------------------------------------------------
function "and"(l: STD_ULOGIC_VECTOR; r: BOOLEAN) return STD_ULOGIC_VECTOR is
variable ll: STD_ULOGIC_vector(l'range);
begin
if (r) then
ll := l;
else
ll := (others => '0');
end if;
return(ll);
end;
--------------------------------------------------------------------
function "and"(l: BOOLEAN; r: STD_ULOGIC) return STD_ULOGIC is
variable ll: STD_ULOGIC;
begin
if (l) then
ll := r;
else
ll := '0';
end if;
return(ll);
end;
--------------------------------------------------------------------
function "and"(l: STD_ULOGIC; r: BOOLEAN) return STD_ULOGIC is
variable ll: STD_ULOGIC;
begin
if (r) then
ll := l;
else
ll := '0';
end if;
return(ll);
end;
--------------------------------------------------------------------
-- function std_ulogic_to_std_logic(b : std_ulogic) return std_logic is
-- variable result: std_logic;
-- begin
-- result := b;
-- return result;
-- end;
--------------------------------------------------------------------
-- function std_logic_to_std_ulogic(b : std_logic) return std_ulogic is
-- variable result: std_ulogic;
-- begin
-- result := b;
-- return result;
-- end;
--------------------------------------------------------------------
function to_vector(input,num_bits: integer) return std_ulogic_vector is
variable vec: std_ulogic_vector(num_bits-1 downto 0);
variable a: integer;
begin
a := input;
for i in 0 to num_bits-1 loop
if ((a mod 2) = 1) then
vec(i) := '1';
else
vec(i) := '0';
end if;
a := a / 2;
end loop;
return vec;
end to_vector;
-- FUNCTION to_vector(input,num_bits:integer) RETURN STD_ULOGIC_VECTOR IS
-- VARIABLE result:STD_ULOGIC_VECTOR(num_bits-1 DOWNTO 0);
-- VARIABLE weight:integer;
-- VARIABLE temp:integer;
-- BEGIN
-- weight := 2**(num_bits-1);
-- temp := input;
-- FOR i in result'HIGH DOWNTO result'LOW LOOP
-- IF temp >= weight THEN
-- result(i) := '1';
-- temp := temp - weight;
-- ELSE
-- result(i) := '0';
-- END IF;
-- weight := weight/2;
-- END LOOP;
-- RETURN result;
-- END to_vector;
--------------------------------------------------------------------
-- exp: Expand one bit into many
--------------------------------------------------------------------
FUNCTION exp(input:STD_ULOGIC; num_bits:integer) RETURN STD_ULOGIC_VECTOR IS
VARIABLE result:STD_ULOGIC_VECTOR(num_bits-1 DOWNTO 0);
BEGIN
FOR i in result'HIGH DOWNTO result'LOW LOOP
result(i) := input;
END LOOP;
RETURN result;
END exp;
--------------------------------------------------------------------
-- exp: Expand n bits into m bits
--------------------------------------------------------------------
FUNCTION exp(input:STD_ULOGIC_VECTOR; num_bits:integer) RETURN STD_ULOGIC_VECTOR IS
VARIABLE result:STD_ULOGIC_VECTOR(num_bits-1 DOWNTO 0);
BEGIN
result(input'high-input'low downto 0) := input;
result(num_bits-1 downto input'high-input'low+1) := (others => '0');
RETURN result;
END exp;
--------------------------------------------------------------------
-- conv_integer
--------------------------------------------------------------------
function conv_integer ( ARG: in STD_ULOGIC_VECTOR ) return integer is
variable result: INTEGER;
begin
assert ARG'length <= 31
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
result := result * 2;
if(ARG(i) = 'H' or ARG(i) = '1') then
result := result + 1;
end if;
end loop;
return result;
end;
--------------------------------------------------------------------
-- "+" Increment function
--------------------------------------------------------------------
function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is
variable Q: STD_ULOGIC_VECTOR(L'range);
variable A: STD_ULOGIC;
begin
A := R;
for i in L'low to L'high loop
Q(i) := L(i) xor A;
A := A and L(i);
end loop;
return Q;
end;
--------------------------------------------------------------------
-- "+" adder function
--------------------------------------------------------------------
-- function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
-- variable Q : SIGNED(L'range);
-- variable result: STD_ULOGIC_VECTOR(L'range);
-- begin
-- Q := to_signed(L) + to_signed(R);
-- result := to_std_ulogic_vector(Q);
-- return result;
-- end;
--------------------------------------------------------------------
-- "-" Decrement function
--------------------------------------------------------------------
-- function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is
-- variable Q: STD_ULOGIC_VECTOR(L'range);
-- variable A: STD_ULOGIC;
-- begin
-- A := R;
-- for i in L'low to L'high loop
-- Q(i) := L(i) xor A;
-- A := A and not L(i);
-- end loop;
-- return Q;
-- end;
--------------------------------------------------------------------
-- "-" subtractor function
--------------------------------------------------------------------
-- function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
-- variable Q : SIGNED(L'range);
-- variable result: STD_ULOGIC_VECTOR(L'range);
-- begin
-- Q := to_signed(L) - to_signed(R);
-- result := to_std_ulogic_vector(Q);
-- return result;
-- end;
--------------------------------------------------------------------
-- to_int : Convert std_ulogic_vector to an integer
--------------------------------------------------------------------
function to_int(l: std_ulogic_vector) return natural is
variable result: natural := 0;
begin
for t1 in l'range loop
result := result * 2;
if (l(t1) = '1') or (l(t1) = 'H') then
result := result + 1;
end if;
end loop;
return result;
end to_int;
--------------------------------------------------------------------
-- to_int : Convert std_ulogic_vector to an integer
--------------------------------------------------------------------
function to_int(l: std_ulogic) return natural is
variable result: natural := 0;
begin
if (l = '1') or (l = 'H') then
result := 1;
else
result := 0;
end if;
return result;
end to_int;
--------------------------------------------------------------------
-- Reduce Functions
--------------------------------------------------------------------
function and_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result: STD_ULOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function nand_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not and_reduce(ARG);
end;
function or_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result: STD_ULOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function nor_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not or_reduce(ARG);
end;
function xor_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result: STD_ULOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function xnor_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not xor_reduce(ARG);
end;
--------------------------------------------------------------------
-- Some useful generic functions
--------------------------------------------------------------------
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : STD_ULOGIC_VECTOR; i : INTEGER ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE qs : STD_ULOGIC_VECTOR (1 TO i);
VARIABLE qt : STD_ULOGIC_VECTOR (1 TO q'length);
-- Hidden function. Synthesis directives are present in its callers
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
FUNCTION maximum (arg1,arg2:INTEGER) RETURN INTEGER IS
BEGIN
IF(arg1 > arg2) THEN
RETURN(arg1) ;
ELSE
RETURN(arg2) ;
END IF;
END ;
FUNCTION minimum (arg1,arg2:INTEGER) RETURN INTEGER IS
BEGIN
IF(arg1 < arg2) THEN
RETURN(arg1) ;
ELSE
RETURN(arg2) ;
END IF;
END ;
--------------------------------------------------------------------
-- Comparision functions
--------------------------------------------------------------------
--
-- Equal functions.
--
TYPE stdlogic_boolean_table IS ARRAY(std_ulogic, std_ulogic) OF BOOLEAN;
CONSTANT eq_table : stdlogic_boolean_table := (
--
----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
--
----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION eq ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
-- Equal for two logic types
VARIABLE result : BOOLEAN ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "EQ" ;
BEGIN
result := eq_table( l, r );
RETURN result ;
END;
FUNCTION eq ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
-- Arithmetic Equal for two Unsigned vectors
VARIABLE result : BOOLEAN ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "EQ" ;
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
result := FALSE;
RETURN result ;
END IF;
END LOOP;
RETURN TRUE;
END;
TYPE std_ulogic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
TYPE std_ulogic_fuzzy_state_table IS ARRAY ( std_ulogic, std_ulogic ) OF std_ulogic_fuzzy_state;
CONSTANT ge_fuzzy_table : std_ulogic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ), -- | U |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | X |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | 0 |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | 1 |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | Z |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | W |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | L |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | H |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ) -- | D |
);
FUNCTION ge ( L,R : std_ulogic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_fuzzy_state;
-- Greater-than-or-equal for two Unsigned vectors
VARIABLE result : BOOLEAN ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "GTE" ;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_fuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
result := TRUE ;
RETURN result;
end ;
--
-- Greater Than functions.
--
CONSTANT gtb_table : stdlogic_boolean_table := (
--
----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
--
----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION gt ( l, r : std_logic ) RETURN BOOLEAN IS
-- Greater-than for two logic types
VARIABLE result : BOOLEAN ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "GT" ;
BEGIN
result := gtb_table( l, r );
RETURN result ;
END ;
FUNCTION gt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
-- Greater-than for two logic unsigned vectors
VARIABLE result : BOOLEAN ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "GT" ;
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
result := gt( lt(i), rt(i) );
RETURN result ;
END IF;
END LOOP;
RETURN FALSE;
END;
--
-- Less Than functions.
--
CONSTANT ltb_table : stdlogic_boolean_table := (
--
----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
--
----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION lt ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
-- Less-than for two logic types
VARIABLE result : BOOLEAN ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "LT" ;
BEGIN
result := ltb_table( l, r );
RETURN result ;
END;
FUNCTION lt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rtt : STD_ULOGIC_VECTOR ( 1 TO ml );
-- Less-than for two Unsigned vectors
VARIABLE result : BOOLEAN ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "LT" ;
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
result := lt( ltt(i), rtt(i) );
RETURN result ;
END IF;
END LOOP;
RETURN FALSE;
END;
--------------------------------------------------------------------
-- "keep" Retain Last value when floated
--------------------------------------------------------------------
procedure keep(signal X: inout STD_LOGIC) is
begin
if(X = 'Z') then
if(X'last_value = '0') then
X <= 'L';
elsif(X'last_value = '1') then
X <= 'H';
else
X <= 'Z';
end if;
else
X <= 'Z';
end if;
end keep;
---------------------------------------------------------------------
-- log base 2 function
---------------------------------------------------------------------
function log2 ( A: in integer ) return integer is
variable B : integer;
begin
B := 1;
for i in 0 to 31 loop
if not ( A > B ) then
return ( i );
exit;
end if;
B := B * 2;
end loop;
end log2;
end UTIL;
testbench/top/main.sv 0 → 100644
View file @ 1bd30289
`timescale 1ns/1ps
`include "simdrv_defs.svh"
`include "gn4124_bfm.svh"
`include "../../dds_regs.vh"
const uint64_t BASE_WRPC = 'h00c0000;
const uint64_t BASE_DDS = 'h0080000;
class CDDSCore;
protected CBusAccessor m_acc;
protected uint64_t m_base;
task writel(uint64_t addr, uint64_t val);
m_acc.write(m_base + addr, val);
endtask
task readl(uint64_t addr, ref uint64_t val);
m_acc.read(m_base + addr, val);
endtask
function new(CBusAccessor acc, uint64_t base);
m_acc = acc;
m_base = base;
endfunction // new
task set_center_frequency( real freq, real fs );
real tune;
tune = (real'(1<<16) * real'(1<<16) * real'(1<<10) * (freq / fs) * 4.0);
$display("CDDSCore: center frequnecy %.3f MHz [tune = %.3f, 0x%x]", freq/1e6, tune, uint64_t'(tune));
writel(`ADDR_DDS_FREQ_HI, uint64_t'(tune) >> 32);
writel(`ADDR_DDS_FREQ_LO, uint64_t'(tune));
writel(`ADDR_DDS_GAIN, 50000);
endtask // set_center_frequency
task tune_write(int value);
writel(`ADDR_DDS_TUNE_FIFO_R0, value);
endtask // tune_write
task boot_mdsp(uint64_t code[]);
int i;
writel('h4000, 1); // reset
for(i=0;i<code.size();i++)
begin
// $display("%16x", code[i]);
writel('h4000+(i*8 + 4) | (1<<11), (code[i]>>32));
writel('h4000+(i*8) | (1<<11), (code[i]>>0));
end
writel('h4000, 0); // un-reset
endtask // boot_mdsp
endclass // CDDSCore
module main;
reg clk_wr_ref = 0;
reg clk_20m_vcxo = 0;
reg tdc_start = 0;
always #4ns clk_wr_ref <= ~clk_wr_ref;
always #20ns clk_20m_vcxo <= ~clk_20m_vcxo;
IGN4124PCIMaster I_Gennum ();
wire [13:0] dac_p;
`include "../mdsp/dsp_microcode.sv"
spec_top
#(
.g_simulation(1)
)
DUT
(
.clk_20m_vcxo_i(clk_20m_vcxo),
.dds_wr_ref_clk_p_i(clk_wr_ref),
.dds_wr_ref_clk_n_i(~clk_wr_ref),
.dds_adc_sdo_i(1'b0),
.dds_dac_p_o(dac_p),
`GENNUM_WIRE_SPEC_PINS(I_Gennum)
);
const real kp = 0.002;
const real ki = 0.000001;
const int kp_q = 100;
// kp * 65536.0;
const int ki_q =10000;
// ki * 65536.0 * 1024.0;
initial begin
uint64_t rval;
int i;
CBusAccessor acc ;
CDDSCore dds;
acc = I_Gennum.get_accessor();
@(posedge I_Gennum.ready);
acc.read(0, rval);
$display("Startup: SDB signature = 0x%08x", rval);
acc.write(BASE_DDS + `ADDR_DDS_RSTR, `DDS_RSTR_SW_RST);
acc.write(BASE_DDS + `ADDR_DDS_RSTR, 0);
dds = new(acc, BASE_DDS);
dds.set_center_frequency(10e6, 250e6);
//dds.boot_mdsp(code);
acc.write(BASE_DDS + `ADDR_DDS_PIR, (ki_q << 16) | (kp_q));
dds.writel(`ADDR_DDS_CR, `DDS_CR_MASTER);
/* for(i=0;i<30;i++)
dds.tune_write(-10000);
for(i=0;i<30;i++)
dds.tune_write(10000);
for(i=0;i<30;i++)
dds.tune_write(0);*/
end
int s_count = 0, l_count = 0;
integer f_out;
initial begin
f_out = $fopen("/tmp/dds-hw.dat","w");
$display("File opened, handle %d", f_out);
end
always@(posedge DUT.clk_ref)
begin
s_count <= s_count + 1;
if(s_count > 10000)
begin
string s;
l_count <= l_count + 1;
$sformat(s, "%d\n", dac_p);
$fwrite(f_out, s);
if(l_count == 262144)
begin
$fclose(f_out);
$stop;
end
end
end
endmodule // main
testbench/top/run.do 0 → 100644
View file @ 1bd30289
#make
vlog -sv main.sv +incdir+../../sim +incdir+gn4124_bfm
vsim -L unisim work.main -voptargs="+acc" -suppress 8684,8683 -novopt
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
do wave.do
run 50000ns
wave zoomfull
radix -hex
testbench/top/wave.do 0 → 100644
View file @ 1bd30289
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/g_goal
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/g_acc_shift
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/clk_i
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/rst_n_i
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/d_valid_i
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/d_i
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/q_valid_o
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/clip_plus
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/clip_minus
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/q_o
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/ki_i
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/kp_i
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/acc
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/err
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/d0
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/d1
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/stage
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/ds
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/acc0
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/term_p
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/term_i
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/sum
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/mul_p
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/mul_i
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/clk_i
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/rst_n_i
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/d_valid_i
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/d_i
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/q_valid_o
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/q_o
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/ki_i
add wave -noupdate -expand -group PI /main/DUT/U_The_DDS_Core/pi_control_1/kp_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/clk_sys_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/clk_dds_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/clk_ref_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/rst_n_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/tm_time_valid_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/tm_tai_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/tm_cycles_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/dac_n_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/dac_p_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/dac_pwdn_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/clk_dds_locked_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pll_vcxo_cs_n_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pll_vcxo_function_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pll_vcxo_sdo_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pll_vcxo_status_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pll_sys_cs_n_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pll_sys_refmon_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pll_sys_ld_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pll_sys_reset_n_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pll_sys_status_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pll_sys_sync_n_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pll_sclk_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pll_sdio_b
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pd_ce_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pd_lockdet_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pd_clk_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pd_data_b
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pd_le_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/adc_sdo_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/adc_sck_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/adc_cnv_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/adc_sdi_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/si57x_oe_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/si57x_sda_b
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/si57x_scl_b
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/slave_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/slave_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/src_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/src_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/snk_i
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/snk_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/swrst_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/fpll_reset_o
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/dac_data_par
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/cnx_out
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/cnx_in
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/synth_tune
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/synth_tune_d0
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/synth_tune_d1
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/synth_tune_bias
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/synth_acc_in
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/synth_acc_out
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/synth_tune_load
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/synth_acc_load
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/synth_y0
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/synth_y1
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/synth_y2
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/synth_y3
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/regs_in
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/regs_out
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/swrst
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/swrst_n
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/rst_n_ref
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/rst_ref
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/cic_out
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/cic_in
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/cic_out_clamp
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/cic_ce
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/tune_empty_d0
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/adc_data
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/adc_dvalid
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/mdsp_out
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/pi_out
add wave -noupdate -radix decimal /main/DUT/U_The_DDS_Core/mdsp_in
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {247278867 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {194778867 ps} {299778867 ps}
top/Manifest.py 0 → 100644
View file @ 1bd30289
files = ["spec_top.vhd", "spec_top.ucf", "spec_serial_dac.vhd", "spec_serial_dac_arb.vhd", "spec_reset_gen.vhd"]
modules = { "local" : [ "../rtl" ],
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git" ],
"svn" : [ "http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl" ] }
top/spec_reset_gen.vhd 0 → 100644
View file @ 1bd30289
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
top/spec_serial_dac.vhd 0 → 100644
View file @ 1bd30289
-------------------------------------------------------------------------------
-- Title : Serial DAC interface
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : serial_dac.vhd
-- Author : paas, slayer
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2011-05-10
-- Platform : fpga-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: The dac unit provides an interface to a 16 bit serial Digita to Analogue converter (max5441, SPI?/QSPI?/MICROWIRE? compatible)
--
-------------------------------------------------------------------------------
-- Copyright (c) 2010 CERN
-------------------------------------------------------------------------------
-- Revisions :1
-- Date Version Author Description
-- 2009-01-24 1.0 paas Created
-- 2010-02-25 1.1 slayer Modified for rev 1.1 switch
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity spec_serial_dac is
generic (
g_num_data_bits : integer := 16;
g_num_extra_bits : integer := 8;
g_num_cs_select : integer := 2
);
port (
-- clock & reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- channel 1 value and value load strobe
value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0);
load_i : in std_logic;
-- SCLK divider: 000 = clk_i/8 ... 111 = clk_i/1024
sclk_divsel_i : in std_logic_vector(2 downto 0);
-- DAC I/F
dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0);
dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic;
xdone_o : out std_logic
);
end spec_serial_dac;
architecture syn of spec_serial_dac is
signal divider : unsigned(11 downto 0);
signal dataSh : std_logic_vector(g_num_data_bits + g_num_extra_bits-1 downto 0);
signal bitCounter : std_logic_vector(g_num_data_bits + g_num_extra_bits+1 downto 0);
signal endSendingData : std_logic;
signal sendingData : std_logic;
signal iDacClk : std_logic;
signal iValidValue : std_logic;
signal divider_muxed : std_logic;
signal cs_sel_reg : std_logic_vector(g_num_cs_select-1 downto 0);
begin
select_divider : process (divider, sclk_divsel_i)
begin -- process
case sclk_divsel_i is
when "000" => divider_muxed <= divider(1); -- sclk = clk_i/8
when "001" => divider_muxed <= divider(2); -- sclk = clk_i/16
when "010" => divider_muxed <= divider(3); -- sclk = clk_i/32
when "011" => divider_muxed <= divider(4); -- sclk = clk_i/64
when "100" => divider_muxed <= divider(5); -- sclk = clk_i/128
when "101" => divider_muxed <= divider(6); -- sclk = clk_i/256
when "110" => divider_muxed <= divider(7); -- sclk = clk_i/512
when "111" => divider_muxed <= divider(8); -- sclk = clk_i/1024
when others => null;
end case;
end process;
iValidValue <= load_i;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
sendingData <= '0';
else
if iValidValue = '1' and sendingData = '0' then
sendingData <= '1';
elsif endSendingData = '1' then
sendingData <= '0';
end if;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if iValidValue = '1' then
divider <= (others => '0');
elsif sendingData = '1' then
if(divider_muxed = '1') then
divider <= (others => '0');
else
divider <= divider + 1;
end if;
elsif endSendingData = '1' then
divider <= (others => '0');
end if;
end if;
end process;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
iDacClk <= '1'; -- 0
else
if iValidValue = '1' then
iDacClk <= '1'; -- 0
elsif divider_muxed = '1' then
iDacClk <= not(iDacClk);
elsif endSendingData = '1' then
iDacClk <= '1'; -- 0
end if;
end if;
end if;
end process;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
dataSh <= (others => '0');
else
if iValidValue = '1' and sendingData = '0' then
cs_sel_reg <= cs_sel_i;
dataSh(g_num_data_bits-1 downto 0) <= value_i;
dataSh(dataSh'left downto g_num_data_bits) <= (others => '0');
elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then
dataSh(0) <= dataSh(dataSh'left);
dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0);
end if;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if iValidValue = '1' and sendingData = '0' then
bitCounter(0) <= '1';
bitCounter(bitCounter'left downto 1) <= (others => '0');
elsif sendingData = '1' and to_integer(divider) = 0 and iDacClk = '1' then
bitCounter(0) <= '0';
bitCounter(bitCounter'left downto 1) <= bitCounter(bitCounter'left - 1 downto 0);
end if;
end if;
end process;
endSendingData <= bitCounter(bitCounter'left);
xdone_o <= not SendingData;
dac_sdata_o <= dataSh(dataSh'left);
gen_cs_out : for i in 0 to g_num_cs_select-1 generate
dac_cs_n_o(i) <= not(sendingData) or (not cs_sel_reg(i));
end generate gen_cs_out;
dac_sclk_o <= iDacClk;
end syn;
top/spec_serial_dac_arb.vhd 0 → 100644
View file @ 1bd30289
library ieee;
use ieee.std_logic_1164.all;
entity spec_serial_dac_arb is
generic(
g_invert_sclk : boolean;
g_num_extra_bits : integer
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
val1_i : in std_logic_vector(15 downto 0);
load1_i : in std_logic;
val2_i : in std_logic_vector(15 downto 0);
load2_i : in std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_clr_n_o : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic);
end spec_serial_dac_arb;
architecture behavioral of spec_serial_dac_arb is
component spec_serial_dac
generic (
g_num_data_bits : integer;
g_num_extra_bits : integer;
g_num_cs_select : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0);
load_i : in std_logic;
sclk_divsel_i : in std_logic_vector(2 downto 0);
dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0);
dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic;
xdone_o : out std_logic);
end component;
signal d1, d2 : std_logic_vector(15 downto 0);
signal d1_ready, d2_ready : std_logic;
signal dac_data : std_logic_vector(15 downto 0);
signal dac_load : std_logic;
signal dac_cs_sel : std_logic_vector(1 downto 0);
signal dac_done : std_logic;
signal dac_sclk_int : std_logic;
type t_state is (WAIT_DONE, LOAD_DAC, WAIT_DATA);
signal state : t_state;
signal trig0 : std_logic_vector(31 downto 0);
signal trig1 : std_logic_vector(31 downto 0);
signal trig2 : std_logic_vector(31 downto 0);
signal trig3 : std_logic_vector(31 downto 0);
signal CONTROL0 : std_logic_vector(35 downto 0);
begin -- behavioral
dac_clr_n_o <= '1';
U_DAC : spec_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => g_num_extra_bits,
g_num_cs_select => 2)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
value_i => dac_data,
cs_sel_i => dac_cs_sel,
load_i => dac_load,
sclk_divsel_i => "001",
dac_cs_n_o => dac_cs_n_o,
dac_sclk_o => dac_sclk_int,
dac_sdata_o => dac_din_o,
xdone_o => dac_done);
p_drive_sclk: process(dac_sclk_int)
begin
if(g_invert_sclk) then
dac_sclk_o <= not dac_sclk_int;
else
dac_sclk_o <= dac_sclk_int;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
d1 <= (others => '0');
d1_ready <= '0';
d2 <= (others => '0');
d2_ready <= '0';
dac_load <= '0';
dac_cs_sel <= (others => '0');
state <= WAIT_DATA;
else
if(load1_i = '1' or load2_i = '1') then
if(load1_i = '1') then
d1_ready <= '1';
d1 <= val1_i;
end if;
if(load2_i = '1') then
d2_ready <= '1';
d2 <= val2_i;
end if;
else
case state is
when WAIT_DATA =>
if(d1_ready = '1') then
dac_cs_sel <= "01";
dac_data <= d1;
dac_load <= '1';
d1_ready <= '0';
state <= LOAD_DAC;
elsif(d2_ready = '1') then
dac_cs_sel <= "10";
dac_data <= d2;
dac_load <= '1';
d2_ready <= '0';
state <= LOAD_DAC;
end if;
when LOAD_DAC=>
dac_load <= '0';
state <= WAIT_DONE;
when WAIT_DONE =>
if(dac_done = '1') then
state <= WAIT_DATA;
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
end behavioral;
top/spec_top.ucf 0 → 100644
View file @ 1bd30289
#bank 0
NET "CLK_20M_VCXO_I" LOC = H12;
NET "CLK_20M_VCXO_I" IOSTANDARD = "LVCMOS25";
#NET "clk_125m_pllref_n_i" LOC = F10;
#NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
#NET "clk_125m_pllref_p_i" LOC = G9;
#NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#NET "clk_125m_gtp_n_i" LOC = D11;
#NET "clk_125m_gtp_p_i" LOC = C11;
#####################################################################
### Gennum ports
#####################################################################
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "GPIO[1]" LOC = U16;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO[0]" LOC = AB19;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
#####################################################################
### SPEC Generic Stuff
#####################################################################
NET "LED_RED" LOC = D5;
NET "LED_RED" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN" LOC = E5;
NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
NET "dac_cs1_n_o" LOC = A3;
NET "dac_cs1_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_cs2_n_o" LOC = B3;
NET "dac_cs2_n_o" IOSTANDARD = "LVCMOS25";
#NET "dac_clr_n_o" LOC = F7;
#NET "dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "BUTTON1_I" LOC = C22;
NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
NET "BUTTON2_I" LOC = D21;
NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
NET "fmc_scl_b" LOC = F7 ;
NET "fmc_scl_b" IOSTANDARD =LVCMOS25;
NET "fmc_sda_b" LOC = F8 ;
NET "fmc_sda_b" IOSTANDARD =LVCMOS25;
#net "led_n_o[0]" loc=c20;
#net "led_n_o[0]" IOSTANDARD=LVCMOS18;
#net "led_n_o[1]" loc=F18;
#net "led_n_o[1]" IOSTANDARD=LVCMOS18;
#net "led_n_o[2]" loc=f20;
#net "led_n_o[2]" IOSTANDARD=LVCMOS18;
#net "led_n_o[3]" loc=G19;
#net "led_n_o[3]" IOSTANDARD=LVCMOS18;
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc_PRSNT_M2C_L_i" LOC="AB14";
#NET "sfp_rxp_i" LOC= D15;
#NET "sfp_rxn_i" LOC= C15;
#NET "sfp_txp_o" LOC= B16;
#NET "sfp_txn_o" LOC= A16;
#NET "SFP_MOD_DEF1_b" LOC = C17;
#NET "SFP_MOD_DEF1_b" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF0_b" LOC = G15;
#NET "SFP_MOD_DEF0_b" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF2_b" LOC = G16;
#NET "SFP_MOD_DEF2_b" IOSTANDARD = "LVCMOS25";
#NET "SFP_RATE_SELECT_b" LOC = H14;
#NET "SFP_RATE_SELECT_b" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_FAULT_i" LOC = A17;
#NET "SFP_TX_FAULT_i" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_DISABLE_o" LOC = F17;
#NET "SFP_TX_DISABLE_o" IOSTANDARD = "LVCMOS25";
#NET "SFP_LOS_i" LOC = D18;
#NET "SFP_LOS_i" IOSTANDARD = "LVCMOS25";
####################################################################################
# Misc
####################################################################################
#NET "uart_rxd_i" LOC= A2;
#NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
#NET "uart_txd_o" LOC= B2;
#NET "uart_txd_o" IOSTANDARD=LVCMOS25;
#bank 0
# <ucfgen_start>
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-dds-600m slot 0
NET "dds_dac_n_o[11]" LOC = "Y6";
NET "dds_dac_n_o[11]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[11]" LOC = "W6";
NET "dds_dac_p_o[11]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[9]" LOC = "U8";
NET "dds_dac_n_o[9]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[9]" LOC = "T8";
NET "dds_dac_p_o[9]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[6]" LOC = "V9";
NET "dds_dac_n_o[6]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[6]" LOC = "U9";
NET "dds_dac_p_o[6]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[3]" LOC = "Y10";
NET "dds_dac_n_o[3]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[3]" LOC = "W10";
NET "dds_dac_p_o[3]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[0]" LOC = "W11";
NET "dds_dac_n_o[0]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[0]" LOC = "V11";
NET "dds_dac_p_o[0]" IOSTANDARD = "LVDS_25";
NET "dds_pll_sys_sync_n_o" LOC = "AA4";
NET "dds_pll_sys_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "dds_pd_ce_o" LOC = "AB4";
NET "dds_pd_ce_o" IOSTANDARD = "LVCMOS25";
NET "dds_pll_sys_refmon_i" LOC = "Y15";
NET "dds_pll_sys_refmon_i" IOSTANDARD = "LVCMOS25";
NET "dds_pll_sys_ld_i" LOC = "AB15";
NET "dds_pll_sys_ld_i" IOSTANDARD = "LVCMOS25";
NET "dds_pll_vcxo_sdo_i" LOC = "V13";
NET "dds_pll_vcxo_sdo_i" IOSTANDARD = "LVCMOS25";
NET "dds_pll_sys_reset_n_o" LOC = "W13";
NET "dds_pll_sys_reset_n_o" IOSTANDARD = "LVCMOS25";
NET "dds_adc_sdo_i" LOC = "W14";
NET "dds_adc_sdo_i" IOSTANDARD = "LVCMOS25";
NET "dds_adc_sck_o" LOC = "Y14";
NET "dds_adc_sck_o" IOSTANDARD = "LVCMOS25";
NET "dds_wr_dac_sclk_o" LOC = "Y16";
NET "dds_wr_dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "dds_pll_vcxo_cs_n_o" LOC = "W15";
NET "dds_pll_vcxo_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "dds_pll_vcxo_function_o" LOC = "V17";
NET "dds_pll_vcxo_function_o" IOSTANDARD = "LVCMOS25";
NET "dds_si57x_oe_o" LOC = "W18";
NET "dds_si57x_oe_o" IOSTANDARD = "LVCMOS25";
NET "dds_pll_vcxo_status_i" LOC = "B20";
NET "dds_pll_vcxo_status_i" IOSTANDARD = "LVCMOS25";
NET "dds_onewire_b" LOC = "A20";
NET "dds_onewire_b" IOSTANDARD = "LVCMOS25";
NET "dds_wr_ref_clk_n_i" LOC = "L22";
NET "dds_wr_ref_clk_n_i" IOSTANDARD = "LVDS_25";
NET "dds_wr_ref_clk_p_i" LOC = "L20";
NET "dds_wr_ref_clk_p_i" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[10]" LOC = "V7";
NET "dds_dac_p_o[10]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[10]" LOC = "W8";
NET "dds_dac_n_o[10]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[7]" LOC = "R9";
NET "dds_dac_p_o[7]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[7]" LOC = "R8";
NET "dds_dac_n_o[7]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[4]" LOC = "T10";
NET "dds_dac_p_o[4]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[4]" LOC = "U10";
NET "dds_dac_n_o[4]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[1]" LOC = "W12";
NET "dds_dac_p_o[1]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[1]" LOC = "Y12";
NET "dds_dac_n_o[1]" IOSTANDARD = "LVDS_25";
NET "dds_trig_term_en_o" LOC = "R11";
NET "dds_trig_term_en_o" IOSTANDARD = "LVCMOS25";
NET "dds_pll_sys_status_i" LOC = "T11";
NET "dds_pll_sys_status_i" IOSTANDARD = "LVCMOS25";
NET "dds_pll_sclk_o" LOC = "R13";
NET "dds_pll_sclk_o" IOSTANDARD = "LVCMOS25";
NET "dds_pll_sdio_b" LOC = "T14";
NET "dds_pll_sdio_b" IOSTANDARD = "LVCMOS25";
NET "dds_adc_cnv_o" LOC = "T15";
NET "dds_adc_cnv_o" IOSTANDARD = "LVCMOS25";
NET "dds_adc_sdi_o" LOC = "U15";
NET "dds_adc_sdi_o" IOSTANDARD = "LVCMOS25";
NET "dds_wr_dac_din_o" LOC = "W17";
NET "dds_wr_dac_din_o" IOSTANDARD = "LVCMOS25";
NET "dds_wr_dac_sync_n_o" LOC = "Y18";
NET "dds_wr_dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "dds_si57x_sda_b" LOC = "C18";
NET "dds_si57x_sda_b" IOSTANDARD = "LVCMOS25";
NET "dds_si57x_scl_b" LOC = "C19";
NET "dds_si57x_scl_b" IOSTANDARD = "LVCMOS25";
NET "dds_dac_p_o[13]" LOC = "AA12";
NET "dds_dac_p_o[13]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[13]" LOC = "AB12";
NET "dds_dac_n_o[13]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[8]" LOC = "AA6";
NET "dds_dac_p_o[8]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[8]" LOC = "AB6";
NET "dds_dac_n_o[8]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[5]" LOC = "Y7";
NET "dds_dac_p_o[5]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[5]" LOC = "AB7";
NET "dds_dac_n_o[5]" IOSTANDARD = "LVDS_25";
NET "dds_dac_p_o[2]" LOC = "Y9";
NET "dds_dac_p_o[2]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[2]" LOC = "AB9";
NET "dds_dac_n_o[2]" IOSTANDARD = "LVDS_25";
NET "dds_dac_pwdn_o" LOC = "AB13";
NET "dds_dac_pwdn_o" IOSTANDARD = "LVCMOS25";
NET "dds_pd_lockdet_i" LOC = "AA16";
NET "dds_pd_lockdet_i" IOSTANDARD = "LVCMOS25";
NET "dds_pd_clk_o" LOC = "AB16";
NET "dds_pd_clk_o" IOSTANDARD = "LVCMOS25";
NET "dds_pll_sys_cs_n_o" LOC = "Y17";
NET "dds_pll_sys_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "dds_dac_p_o[12]" LOC = "Y5";
NET "dds_dac_p_o[12]" IOSTANDARD = "LVDS_25";
NET "dds_dac_n_o[12]" LOC = "AB5";
NET "dds_dac_n_o[12]" IOSTANDARD = "LVDS_25";
NET "dds_trig_dir_o" LOC = "AA8";
NET "dds_trig_dir_o" IOSTANDARD = "LVCMOS25";
NET "dds_trig_act_o" LOC = "AB8";
NET "dds_trig_act_o" IOSTANDARD = "LVCMOS25";
NET "dds_pd_data_b" LOC = "AA18";
NET "dds_pd_data_b" IOSTANDARD = "LVCMOS25";
NET "dds_pd_le_o" LOC = "AB18";
NET "dds_pd_le_o" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2013/05/05
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "dds_wr_ref_clk_n_i" TNM_NET = dds_wr_ref_clk_n_i;
TIMESPEC TS_dds_wr_ref_clk_n_i = PERIOD "dds_wr_ref_clk_n_i" 8 ns HIGH 50%;
NET "dds_wr_ref_clk_p_i" TNM_NET = dds_wr_ref_clk_p_i;
TIMESPEC TS_dds_wr_ref_clk_p_i = PERIOD "dds_wr_ref_clk_p_i" 8 ns HIGH 50%;
#===============================================================================
# Timing constraints
#===============================================================================
# GN4124
#gennum
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
INST "cmp_gn4124_core/l2p_rdy_t" IOB=FALSE;
INST "cmp_gn4124_core/l_wr_rdy_t*" IOB=FALSE;
#NET "L_CLKp" TNM_NET = "l_clkp_grp";
#TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 5 ns HIGH 50%;
NET "L2P_CLKN" TNM = "gn4124_data_bus_out";
NET "L2P_CLKP" TNM = "gn4124_data_bus_out";
NET "L2P_VALID" TNM = "gn4124_data_bus_out";
NET "L2P_DFRAME" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[0]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[1]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[2]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[3]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[4]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[5]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[6]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[7]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[8]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[9]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[10]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[11]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[12]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[13]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[14]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[15]" TNM = "gn4124_data_bus_out";
#TIMEGRP "gn4124_data_bus_out" OFFSET = OUT AFTER "cmp_gn4124_core/io_clk" REFERENCE_PIN "L2P_CLKP";
NET "P2L_CLKN" TNM = "gn4124_data_bus_in";
NET "P2L_CLKP" TNM = "gn4124_data_bus_in";
NET "P2L_DFRAME" TNM = "gn4124_data_bus_in";
NET "P2L_VALID" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[0]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[1]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[2]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[3]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[4]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[5]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[6]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[7]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[8]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[9]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[10]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[11]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[12]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[13]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[14]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[15]" TNM = "gn4124_data_bus_in";
#TIMEGRP "gn4124_data_bus_in" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE "cmp_gn4124_core/io_clk" RISING;
#TIMEGRP "gn4124_data_bus_in" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE "cmp_gn4124_core/io_clk" FALLING;
top/spec_top.vhd 0 → 100644
View file @ 1bd30289
library ieee;
use ieee.std_logic_1164.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity spec_top is
generic
(
g_simulation : integer := 0
);
port
(
-------------------------------------------------------------------------
-- Standard SPEC ports (Gennum bridge, LEDS, Etc. Do not modify
-------------------------------------------------------------------------
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
--clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
--clk_125m_pllref_n_i : in std_logic;
--clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
--clk_125m_gtp_p_i : in std_logic;
l_rst_n : in std_logic; -- reset from gn4124 (rstout18_n)
-- general purpose interface
gpio : inout std_logic_vector(1 downto 0); -- gpio[0] -> gn4124 gpio8
-- gpio[1] -> gn4124 gpio9
-- pcie to local [inbound data] - rx
p2l_rdy : out std_logic; -- rx buffer full flag
p2l_clkn : in std_logic; -- receiver source synchronous clock-
p2l_clkp : in std_logic; -- receiver source synchronous clock+
p2l_data : in std_logic_vector(15 downto 0); -- parallel receive data
p2l_dframe : in std_logic; -- receive frame
p2l_valid : in std_logic; -- receive data valid
-- inbound buffer request/status
p_wr_req : in std_logic_vector(1 downto 0); -- pcie write request
p_wr_rdy : out std_logic_vector(1 downto 0); -- pcie write ready
rx_error : out std_logic; -- receive error
-- local to parallel [outbound data] - tx
l2p_data : out std_logic_vector(15 downto 0); -- parallel transmit data
l2p_dframe : out std_logic; -- transmit data frame
l2p_valid : out std_logic; -- transmit data valid
l2p_clkn : out std_logic; -- transmitter source synchronous clock-
l2p_clkp : out std_logic; -- transmitter source synchronous clock+
l2p_edb : out std_logic; -- packet termination and discard
-- outbound buffer status
l2p_rdy : in std_logic; -- tx buffer full flag
l_wr_rdy : in std_logic_vector(1 downto 0); -- local-to-pcie write
p_rd_d_rdy : in std_logic_vector(1 downto 0); -- pcie-to-local read response data ready
tx_error : in std_logic; -- transmit error
vc_rdy : in std_logic_vector(1 downto 0); -- channel ready
-- font panel leds
led_red : out std_logic;
led_green : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
--dac_clr_n_o : out std_logic;
dac_cs1_n_o : out std_logic;
dac_cs2_n_o : out std_logic;
button1_i : in std_logic := '1';
button2_i : in std_logic := '1';
fmc_scl_b : inout std_logic := '1';
fmc_sda_b : inout std_logic := '1';
carrier_onewire_b : inout std_logic := '1';
fmc_prsnt_m2c_l_i : in std_logic;
-- DDS Dac I/F (Maxim)
dds_dac_n_o : out std_logic_vector(13 downto 0);
dds_dac_p_o : out std_logic_vector(13 downto 0);
dds_dac_pwdn_o : out std_logic;
-- AD9516 (SYS) and AD9510 (VCXO cleaner) PLL control
dds_pll_vcxo_cs_n_o : out std_logic;
dds_pll_vcxo_function_o : out std_logic;
dds_pll_vcxo_sdo_i : in std_logic;
dds_pll_vcxo_status_i : in std_logic;
dds_pll_sys_cs_n_o : out std_logic;
dds_pll_sys_refmon_i : in std_logic;
dds_pll_sys_ld_i : in std_logic;
dds_pll_sys_reset_n_o : out std_logic;
dds_pll_sys_status_i : in std_logic;
dds_pll_sys_sync_n_o : out std_logic;
dds_pll_sclk_o : out std_logic;
dds_pll_sdio_b : inout std_logic;
-- WR refernce clock & VCO control
dds_wr_ref_clk_p_i : in std_logic;
dds_wr_ref_clk_n_i : in std_logic;
dds_wr_dac_sclk_o : out std_logic;
dds_wr_dac_din_o : out std_logic;
dds_wr_dac_sync_n_o : out std_logic;
-- Phase Detector & its ADC
dds_pd_ce_o : out std_logic;
dds_pd_lockdet_i : in std_logic;
dds_pd_clk_o : out std_logic;
dds_pd_data_b : inout std_logic;
dds_pd_le_o : out std_logic;
dds_adc_sdo_i : in std_logic;
dds_adc_sck_o : out std_logic;
dds_adc_cnv_o : out std_logic;
dds_adc_sdi_o : out std_logic;
-- Silabs clock gen control
dds_si57x_oe_o : out std_logic;
dds_si57x_sda_b : inout std_logic;
dds_si57x_scl_b : inout std_logic;
-- GPIO, misc stuff
dds_onewire_b : inout std_logic;
dds_trig_term_en_o : out std_logic;
dds_trig_dir_o : out std_logic;
dds_trig_act_o : out std_logic
);
end spec_top;
architecture rtl of spec_top is
constant c_NUM_WB_MASTERS : integer := 2;
constant c_NUM_WB_SLAVES : integer := 2;
constant c_MASTER_GENNUM : integer := 0;
constant c_MASTER_ETHERBONE : integer := 1;
constant c_SLAVE_DDS_CORE : integer := 0;
constant c_SLAVE_WRCORE : integer := 1;
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_DDS_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0000ffff", x"0000c000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS-1 downto 0) :=
(c_SLAVE_WRCORE => f_sdb_embed_bridge(c_WRCORE_BRIDGE_SDB, x"000c0000"),
c_SLAVE_DDS_CORE => f_sdb_embed_bridge(c_DDS_BRIDGE_SDB, x"00080000"));
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
component spec_reset_gen
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end component;
signal clk_125m_pllref : std_logic;
signal clk_dmtd, clk_dds, clk_ref : std_logic;
signal pllout_clk_dmtd, pllout_clk_dds, pllout_clk_ref : std_logic;
signal clk_20m_vcxo_buf : std_logic;
signal gn_wb_adr : std_logic_vector(31 downto 0);
alias clk_sys is clk_dmtd;
signal local_reset_n : std_logic;
signal fpll_locked, pllout_clk_fb_pllref : std_logic;
signal swrst, swrst_n, fpll_reset : std_logic;
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal pllout_clk_fb_dmtd : std_logic;
component dds_core
port (
clk_sys_i : in std_logic;
clk_dds_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
tm_time_valid_i : in std_logic;
tm_tai_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
dac_n_o : out std_logic_vector(13 downto 0);
dac_p_o : out std_logic_vector(13 downto 0);
dac_pwdn_o : out std_logic;
clk_dds_locked_i : in std_logic;
pll_vcxo_cs_n_o : out std_logic;
pll_vcxo_function_o : out std_logic;
pll_vcxo_sdo_i : in std_logic;
pll_vcxo_status_i : in std_logic;
pll_sys_cs_n_o : out std_logic;
pll_sys_refmon_i : in std_logic;
pll_sys_ld_i : in std_logic;
pll_sys_reset_n_o : out std_logic;
pll_sys_status_i : in std_logic;
pll_sys_sync_n_o : out std_logic;
pll_sclk_o : out std_logic;
pll_sdio_b : inout std_logic;
pd_ce_o : out std_logic;
pd_lockdet_i : in std_logic;
pd_clk_o : out std_logic;
pd_data_b : inout std_logic;
pd_le_o : out std_logic;
adc_sdo_i : in std_logic;
adc_sck_o : out std_logic;
adc_cnv_o : out std_logic;
adc_sdi_o : out std_logic;
si57x_oe_o : out std_logic;
si57x_sda_b : inout std_logic;
si57x_scl_b : inout std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
swrst_o : out std_logic;
fpll_reset_o : out std_logic);
end component;
begin -- rtl
U_Buf_CLK_PLL : IBUFGDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => false -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => clk_125m_pllref, -- Buffer output
I => dds_wr_ref_clk_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => dds_wr_ref_clk_n_i -- Diff_n buffer input (connect directly to top-level port)
);
U_Reset_Generator : spec_reset_gen
port map (
clk_sys_i => clk_sys,
rst_pcie_n_a_i => l_rst_n,
rst_button_n_a_i => button1_i,
rst_n_o => local_reset_n);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2, -- 125 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 500 GHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16, -- 62.5 MHz
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT1 => pllout_clk_ref,
CLKOUT0 => clk_dds,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => fpll_locked,
RST => fpll_reset,
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_125m_pllref);
cmp_clk_vcxo : BUFG
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
cmp_dmtd_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- 62.5 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_dmtd,
CLKOUT0 => pllout_clk_dmtd,
CLKOUT1 => open, --pllout_clk_sys,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_dmtd,
CLKIN => clk_20m_vcxo_buf);
cmp_clk_sys_buf : BUFG
port map (
O => clk_dmtd,
I => pllout_clk_dmtd);
-- cmp_clk_dds_buf : BUFG
-- port map (
-- O => clk_dds,
-- I => pllout_clk_dds);
cmp_clk_ref_buf : BUFG
port map (
O => clk_ref,
I => pllout_clk_ref);
cmp_gn4124_core : gn4124_core
port map
(
---------------------------------------------------------
-- Control and status
rst_n_a_i => L_RST_N,
status_o => open,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
-- L2P Control
l2p_edb_o => L2P_EDB,
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
---------------------------------------------------------
-- Interrupt interface
dma_irq_o => open,
irq_p_i => '0',
irq_p_o => open,
dma_reg_clk_i => clk_sys,
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i => clk_sys,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
csr_sel_o => cnx_slave_in(c_MASTER_GENNUM).sel,
csr_stb_o => cnx_slave_in(c_MASTER_GENNUM).stb,
csr_we_o => cnx_slave_in(c_MASTER_GENNUM).we,
csr_cyc_o => cnx_slave_in(c_MASTER_GENNUM).cyc,
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
dma_clk_i => clk_sys,
dma_ack_i => '1',
dma_stall_i => '0',
dma_dat_i => (others => '0'),
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
dma_reg_stb_i => '0',
dma_reg_cyc_i => '0',
dma_reg_we_i => '0'
);
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
cnx_slave_in(c_MASTER_ETHERBONE).cyc <= '0';
U_Intercon : xwb_sdb_crossbar
generic map (
g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map (
clk_sys_i => clk_sys,
rst_n_i => local_reset_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
U_The_DDS_Core : dds_core
port map (
clk_sys_i => clk_sys,
clk_dds_i => clk_dds,
clk_ref_i => clk_ref,
rst_n_i => local_reset_n,
tm_time_valid_i => '0',
tm_tai_i => x"0000000000",
tm_cycles_i => x"0000000",
dac_n_o => dds_dac_n_o,
dac_p_o => dds_dac_p_o,
dac_pwdn_o => dds_dac_pwdn_o,
clk_dds_locked_i => fpll_locked,
pll_vcxo_cs_n_o => dds_pll_vcxo_cs_n_o,
pll_vcxo_function_o => dds_pll_vcxo_function_o,
pll_vcxo_sdo_i => dds_pll_vcxo_sdo_i,
pll_vcxo_status_i => dds_pll_vcxo_status_i,
pll_sys_cs_n_o => dds_pll_sys_cs_n_o,
pll_sys_refmon_i => dds_pll_sys_refmon_i,
pll_sys_ld_i => dds_pll_sys_ld_i,
pll_sys_reset_n_o => dds_pll_sys_reset_n_o,
pll_sys_status_i => dds_pll_sys_status_i,
pll_sys_sync_n_o => dds_pll_sys_sync_n_o,
pll_sclk_o => dds_pll_sclk_o,
pll_sdio_b => dds_pll_sdio_b,
pd_ce_o => dds_pd_ce_o,
pd_lockdet_i => dds_pd_lockdet_i,
pd_clk_o => dds_pd_clk_o,
pd_data_b => dds_pd_data_b,
pd_le_o => dds_pd_le_o,
adc_sdo_i => dds_adc_sdo_i,
adc_sck_o => dds_adc_sck_o,
adc_cnv_o => dds_adc_cnv_o,
adc_sdi_o => dds_adc_sdi_o,
slave_i => cnx_master_out(c_SLAVE_DDS_CORE),
slave_o => cnx_master_in(c_SLAVE_DDS_CORE),
src_i => c_dummy_src_in,
src_o => open,
snk_i => c_dummy_snk_in,
snk_o => open,
swrst_o => swrst,
fpll_reset_o => fpll_reset,
si57x_scl_b => dds_si57x_scl_b,
si57x_sda_b => dds_si57x_sda_b,
si57x_oe_o => dds_si57x_oe_o
);
cnx_master_in(1).ack <= '1';
cnx_master_in(1).stall <= '0';
cnx_master_in(1).err <= '0';
cnx_master_in(1).rty <= '0';
-- Drive unused signals
dds_onewire_b <= 'Z';
dds_trig_term_en_o <= '0';
dds_trig_dir_o <= '0';
dds_trig_act_o <= '0';
end rtl;
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