Commit 2e8c4217 authored by root's avatar root Committed by Tomasz Wlostowski

software:wip, PI in HW working

parent f75d5bed
......@@ -324,37 +324,62 @@ void boot_mdsp(struct wr_rf_device *dev, const char *mc_file)
void test_pid(struct wr_rf_device *dev)
{
struct fir_filter *flt_comp = fir_load("fir_compensator.dat");
struct iir_1st *flt_loop = lowpass_init(2e3/(125e6/1024.0));
struct iir_1st *flt_loop = lowpass_init(1000.0/(125e6/1024.0));
double kp = 0.001;
double kp = 0.002;
double ki = 0.000001;
int i;
rf_writel(dev, 2000, DDS_REG_GAIN); /* tuning gain = 0 dB */
rf_writel(dev, DDS_CR_TEST, DDS_REG_CR);
int s;
for(i=0;i<10000;i++)
read_adc(dev, &s , 1);
double integ = 0.0;
int ki_q = (int) ((1024.0 * ki) * (double)(1<<16));
int kp_q = (int) ((1.0 * kp) * (double)(1<<16));
// printf("ki_q %d kp_q %d\n", ki_q, kp_q);
#define ACC_BITS 30
int64_t acc = 0;
for(i=0;i<100000;i++)
read_adc(dev, &s , 1);
for(;;)
{
int s,err;
read_adc(dev, &s , 1);
// s = lowpass_process(flt_loop, s);
s-=32768;
err = s;
// s*=-1;
integ += (double)err;
// integ += (double)err;
acc += err >> 10;
acc &= (1<<ACC_BITS) - 1;
if(acc & (1<<(ACC_BITS-1)))
acc |= ~((1<<ACC_BITS)-1);
s = (int) (integ * ki + (double) err * kp);
s = lowpass_process(flt_loop, s);
s = fir_process(flt_comp, s);
s = ((int64_t)(acc) * (int64_t) ki_q + (int64_t)err * (int64_t)kp_q) >> 16;
// s = (int) (integ * ki + (double) err * kp);
// s = fir_process(flt_comp, s);
// integ *= 0.999999;
// printf("%d\n", s);
if(s < -32000) s = -32000;
......@@ -396,9 +421,9 @@ int main(int argc, char *argv[])
struct fir_filter *flt_comp = fir_load("fir_compensator.dat");
struct iir_1st *flt_loop = lowpass_init(0.02);
rf_writel(&dev, 3000, DDS_REG_GAIN); /* tuning gain = 0 dB */
test_pid(&dev);
// test_pid(&dev);
// test_pid2(&dev);
//for(;;) write_tune(&dev, 15000);
......@@ -420,10 +445,26 @@ int main(int argc, char *argv[])
int i;
int s;
rf_writel(&dev, 3000, DDS_REG_GAIN); /* tuning gain = 0 dB */
rf_writel(&dev, DDS_CR_TEST, DDS_REG_CR);
boot_mdsp(&dev, "microcode.dat");
// rf_writel(dev, 2000, DDS_REG_GAIN); /* tuning gain = 0 dB */
double kp = 0.05;
double ki = 0.0000005;
int ki_q = (int) ((1024.0 * ki) * (double)(1<<16));
int kp_q = (int) ((1.0 * kp) * (double)(1<<16));
printf("kp_q %d ki_q %d\n", kp_q, ki_q);
// boot_mdsp(&dev, "microcode.dat");
rf_writel(&dev, DDS_RSTR_SW_RST, DDS_REG_RSTR);
udelay(10);
rf_writel(&dev, 0, DDS_REG_RSTR);
rf_writel(&dev, DDS_PIR_KI_W(ki_q) | DDS_PIR_KP_W(kp_q), DDS_REG_PIR);
rf_writel(&dev, DDS_CR_MASTER, DDS_REG_CR);
return 0;
for(i=0;i<10000;i++)
......
......@@ -3,7 +3,7 @@
* File : dds_regs.h
* Author : auto-generated by wbgen2 from dds_wb_slave.wb
* Created : Mon May 6 17:52:47 2013
* Created : Fri May 10 01:11:43 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dds_wb_slave.wb
......@@ -132,6 +132,20 @@
/* definitions for field: SDA Line in in reg: I2C bitbanged IO register */
#define DDS_I2CR_SDA_IN WBGEN2_GEN_MASK(3, 1)
/* definitions for register: PI register */
/* definitions for field: KP in reg: PI register */
#define DDS_PIR_KP_MASK WBGEN2_GEN_MASK(0, 16)
#define DDS_PIR_KP_SHIFT 0
#define DDS_PIR_KP_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define DDS_PIR_KP_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: KI in reg: PI register */
#define DDS_PIR_KI_MASK WBGEN2_GEN_MASK(16, 16)
#define DDS_PIR_KI_SHIFT 16
#define DDS_PIR_KI_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define DDS_PIR_KI_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: FIFO 'PD ADC Test FIFO (test mode)' data output register 0 */
/* definitions for field: ADC data in reg: FIFO 'PD ADC Test FIFO (test mode)' data output register 0 */
......@@ -177,12 +191,14 @@
#define DDS_REG_RSTR 0x00000014
/* [0x18]: REG I2C bitbanged IO register */
#define DDS_REG_I2CR 0x00000018
/* [0x1c]: REG FIFO 'PD ADC Test FIFO (test mode)' data output register 0 */
#define DDS_REG_PD_FIFO_R0 0x0000001c
/* [0x20]: REG FIFO 'PD ADC Test FIFO (test mode)' control/status register */
#define DDS_REG_PD_FIFO_CSR 0x00000020
/* [0x24]: REG FIFO 'DDS Tuning FIFO (test mode)' data input register 0 */
#define DDS_REG_TUNE_FIFO_R0 0x00000024
/* [0x28]: REG FIFO 'DDS Tuning FIFO (test mode)' control/status register */
#define DDS_REG_TUNE_FIFO_CSR 0x00000028
/* [0x1c]: REG PI register */
#define DDS_REG_PIR 0x0000001c
/* [0x20]: REG FIFO 'PD ADC Test FIFO (test mode)' data output register 0 */
#define DDS_REG_PD_FIFO_R0 0x00000020
/* [0x24]: REG FIFO 'PD ADC Test FIFO (test mode)' control/status register */
#define DDS_REG_PD_FIFO_CSR 0x00000024
/* [0x28]: REG FIFO 'DDS Tuning FIFO (test mode)' data input register 0 */
#define DDS_REG_TUNE_FIFO_R0 0x00000028
/* [0x2c]: REG FIFO 'DDS Tuning FIFO (test mode)' control/status register */
#define DDS_REG_TUNE_FIFO_CSR 0x0000002c
#endif
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