Commit 5c0d6a7f authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

removed old project

parent ca9b19b8
WR RF Distribution Demo
Tomasz Wlostowski/CERN BE-CO-HT 2013
IMPORTANT: This repository contains the first proof-of-concept version of the
WR DDS system. It is no longer maintained. Please visit the 'wr-d3s' project Wiki
to access the newest version of the WR DDS solution.
---------------------------------------
Project structure:
1) rtl - HDL sources (mixed Verilog/VHDL)
dds_stage.v single DDS generator (in our case, 125 MHz)
dds_quad_channel.v 500 MHz version consisting of 4 "single stages", phase-shifted by 90 degrees
dds_rx_path.vhd
dds_tx_path.vhd WR streamer data formatting and decoding
dds_wb_slave.vhd
dds_wb_slave.wb
dds_wbgen2_pkg.vhd Wishbone slave (wbgen2-generated)
ad7890_if.vhd SPI interface for the PLL ADC
max5870_serializer.vhd SelectIO serdes for driving the DDS DAC
pi_control.v As the name says
pll_init.v Hardware SPI master for initializing the on-board clock generator (AD9516)
pll_init_data.v
cic_1024x.vhd 1024x CIC interpolator. Matlab-generated.
timestamp_adder.vhd
timestamp_compare.vhd WR timestamp arithmetic cores
2) software - a C test program
3) top/spec - top level for the SPEC (connects the WR core and Gennum PCI-Express core)
4) syn/spec - synthesis directory
5) sim - simulation models (symlink to wr-cores/sim)
6) scripts - ucfgen script for pin assignment
Synthesizing:
cd syn/spec
hdlmake --ise-proj
open project in ISE, click Synthesize...
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`define ADDR_DDS_CR 7'h0
`define DDS_CR_TEST_OFFSET 0
`define DDS_CR_TEST 32'h00000001
`define DDS_CR_SLAVE_OFFSET 1
`define DDS_CR_SLAVE 32'h00000002
`define DDS_CR_MASTER_OFFSET 2
`define DDS_CR_MASTER 32'h00000004
`define DDS_CR_ADC_BB_ENABLE_OFFSET 3
`define DDS_CR_ADC_BB_ENABLE 32'h00000008
`define DDS_CR_WR_LINK_OFFSET 4
`define DDS_CR_WR_LINK 32'h00000010
`define DDS_CR_WR_TIME_OFFSET 5
`define DDS_CR_WR_TIME 32'h00000020
`define DDS_CR_CLK_ID_OFFSET 16
`define DDS_CR_CLK_ID 32'hffff0000
`define ADDR_DDS_GPIOR 7'h4
`define DDS_GPIOR_PLL_SYS_CS_N_OFFSET 0
`define DDS_GPIOR_PLL_SYS_CS_N 32'h00000001
`define DDS_GPIOR_PLL_SYS_RESET_N_OFFSET 1
`define DDS_GPIOR_PLL_SYS_RESET_N 32'h00000002
`define DDS_GPIOR_PLL_SCLK_OFFSET 2
`define DDS_GPIOR_PLL_SCLK 32'h00000004
`define DDS_GPIOR_PLL_SDIO_OFFSET 3
`define DDS_GPIOR_PLL_SDIO 32'h00000008
`define DDS_GPIOR_PLL_SDIO_DIR_OFFSET 4
`define DDS_GPIOR_PLL_SDIO_DIR 32'h00000010
`define DDS_GPIOR_PLL_VCXO_RESET_N_OFFSET 5
`define DDS_GPIOR_PLL_VCXO_RESET_N 32'h00000020
`define DDS_GPIOR_PLL_VCXO_CS_N_OFFSET 6
`define DDS_GPIOR_PLL_VCXO_CS_N 32'h00000040
`define DDS_GPIOR_PLL_VCXO_FUNCTION_OFFSET 7
`define DDS_GPIOR_PLL_VCXO_FUNCTION 32'h00000080
`define DDS_GPIOR_PLL_VCXO_SDO_OFFSET 8
`define DDS_GPIOR_PLL_VCXO_SDO 32'h00000100
`define DDS_GPIOR_ADF_CE_OFFSET 9
`define DDS_GPIOR_ADF_CE 32'h00000200
`define DDS_GPIOR_ADF_CLK_OFFSET 10
`define DDS_GPIOR_ADF_CLK 32'h00000400
`define DDS_GPIOR_ADF_LE_OFFSET 11
`define DDS_GPIOR_ADF_LE 32'h00000800
`define DDS_GPIOR_ADF_DATA_OFFSET 12
`define DDS_GPIOR_ADF_DATA 32'h00001000
`define DDS_GPIOR_ADC_SDI_OFFSET 13
`define DDS_GPIOR_ADC_SDI 32'h00002000
`define DDS_GPIOR_ADC_CNV_OFFSET 14
`define DDS_GPIOR_ADC_CNV 32'h00004000
`define DDS_GPIOR_ADC_SCK_OFFSET 15
`define DDS_GPIOR_ADC_SCK 32'h00008000
`define DDS_GPIOR_ADC_SDO_OFFSET 16
`define DDS_GPIOR_ADC_SDO 32'h00010000
`define ADDR_DDS_FREQ_HI 7'h8
`define ADDR_DDS_FREQ_LO 7'hc
`define ADDR_DDS_GAIN 7'h10
`define ADDR_DDS_RSTR 7'h14
`define DDS_RSTR_PLL_RST_OFFSET 0
`define DDS_RSTR_PLL_RST 32'h00000001
`define DDS_RSTR_SW_RST_OFFSET 1
`define DDS_RSTR_SW_RST 32'h00000002
`define ADDR_DDS_I2CR 7'h18
`define DDS_I2CR_SCL_OUT_OFFSET 0
`define DDS_I2CR_SCL_OUT 32'h00000001
`define DDS_I2CR_SDA_OUT_OFFSET 1
`define DDS_I2CR_SDA_OUT 32'h00000002
`define DDS_I2CR_SCL_IN_OFFSET 2
`define DDS_I2CR_SCL_IN 32'h00000004
`define DDS_I2CR_SDA_IN_OFFSET 3
`define DDS_I2CR_SDA_IN 32'h00000008
`define ADDR_DDS_PIR 7'h1c
`define DDS_PIR_KP_OFFSET 0
`define DDS_PIR_KP 32'h0000ffff
`define DDS_PIR_KI_OFFSET 16
`define DDS_PIR_KI 32'hffff0000
`define ADDR_DDS_DLYR 7'h20
`define DDS_DLYR_DELAY_OFFSET 0
`define DDS_DLYR_DELAY 32'h0000ffff
`define ADDR_DDS_PHASER 7'h24
`define DDS_PHASER_PHASE_OFFSET 0
`define DDS_PHASER_PHASE 32'h0000ffff
`define ADDR_DDS_MACL 7'h28
`define DDS_MACL_MACL_OFFSET 0
`define DDS_MACL_MACL 32'hffffffff
`define ADDR_DDS_MACH 7'h2c
`define DDS_MACH_MACH_OFFSET 0
`define DDS_MACH_MACH 32'h0000ffff
`define ADDR_DDS_HIT_CNT 7'h30
`define DDS_HIT_CNT_HIT_CNT_OFFSET 0
`define DDS_HIT_CNT_HIT_CNT 32'h00ffffff
`define ADDR_DDS_MISS_CNT 7'h34
`define DDS_MISS_CNT_MISS_CNT_OFFSET 0
`define DDS_MISS_CNT_MISS_CNT 32'h00ffffff
`define ADDR_DDS_RX_CNT 7'h38
`define DDS_RX_CNT_RX_CNT_OFFSET 0
`define DDS_RX_CNT_RX_CNT 32'h00ffffff
`define ADDR_DDS_TX_CNT 7'h3c
`define DDS_TX_CNT_TX_CNT_OFFSET 0
`define DDS_TX_CNT_TX_CNT 32'h00ffffff
`define ADDR_DDS_PD_FIFO_R0 7'h40
`define DDS_PD_FIFO_R0_DATA_OFFSET 0
`define DDS_PD_FIFO_R0_DATA 32'h0000ffff
`define ADDR_DDS_PD_FIFO_CSR 7'h44
`define DDS_PD_FIFO_CSR_FULL_OFFSET 16
`define DDS_PD_FIFO_CSR_FULL 32'h00010000
`define DDS_PD_FIFO_CSR_EMPTY_OFFSET 17
`define DDS_PD_FIFO_CSR_EMPTY 32'h00020000
`define ADDR_DDS_TUNE_FIFO_R0 7'h48
`define DDS_TUNE_FIFO_R0_DATA_OFFSET 0
`define DDS_TUNE_FIFO_R0_DATA 32'hffffffff
`define ADDR_DDS_TUNE_FIFO_CSR 7'h4c
`define DDS_TUNE_FIFO_CSR_FULL_OFFSET 16
`define DDS_TUNE_FIFO_CSR_FULL 32'h00010000
`define DDS_TUNE_FIFO_CSR_EMPTY_OFFSET 17
`define DDS_TUNE_FIFO_CSR_EMPTY 32'h00020000
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function [y,acc]=dds(inc,lut,lsize,frac)
disp('x')
fs = 125e6; % Input sampling frequency.
fpass = 0.02e6; % Frequency band of interest.
m = 1024; % Decimation factor.
hcic = design(fdesign.interpolator(m,'cic',1,fpass,90,fs));
hcic
gain(hcic, 6)
g = 1/ (2^70)
hd = cascade(dfilt.scalar(g),hcic);
comp = fdesign.ciccomp(hcic.differentialdelay, ...
hcic.numberofsections,fpass,fpass * 1.6,.1,90,fs/m)
hd(2) = design(comp,'fir')
fvtool(hd(1),hd(2),...
cascade(hd(2),hd(1)),'Fs',[fs fs/m fs])
%fvtool(hd)
\ No newline at end of file
f=10e6;
fs=500e6;
tune = (2^42) * (f/fs) * 8;
f2 = fs * (tune+1) / (2^42 * 8);
span = abs(f - f2) * 65536
y=csvread('/tmp/dds-hw.dat');
nsamples=length(y)
%y=y+randi([-1,1],nsamples,1)
f = 20*log10(abs(fft(y.*hanning(nsamples))));
hold on;
plot(f - max(f),'r-');
grid on;
lut_size=32768;
dac_bits=12;
dac_bias = 2^(dac_bits-1);
dac_ampl = 2^(dac_bits-1) - 1;
acc_frac=32;
n_sub_taps = 512;
lut_real=cos(linspace(0, 2*pi * lut_size/(lut_size + 1), lut_size)) .* dac_ampl
lut = round(lut_real);
for i = 1:lut_size
ni = i+1;
if(ni > lut_size)
ni=1;
end
x0 = 2 * pi * (i-1) / lut_size;
x1 = 2 * pi * i / lut_size;
sub = cos(linspace(x0, x1, n_sub_taps)).*dac_ampl;
for j=1+1:n_sub_taps-1
if(abs(sub(j) - sub(1)) >= abs(sub(n_sub_taps)-sub(j)))
break
end
end
offs(i)= j / n_sub_taps * (2^acc_frac);
end
fs=500e6;
fout=11.1111e6;
tune_res = 0.01;
acc_bits=acc_frac + log2(lut_size);
acc_max = 2^acc_bits;
acc = 0;
nsamples = 32768;
y=zeros(nsamples,1);
y2=zeros(nsamples,1);
delta = round((lut_size * fout/fs) * (2^acc_frac))
for i =1:nsamples
idx = floor(acc / (2^acc_frac)) + 1;
fb = floor(mod(acc, 2^acc_frac));
if(idx > lut_size)
idx = idx - lut_size;
end
if(fb < offs(idx))
yt=lut(idx);
elseif(idx == lut_size)
yt=lut(1);
else
yt=lut(idx+1);
end
y(i)= yt + randi([0, 1],1,1);
y2(i) = round(cos(2*pi*(acc/(2^acc_frac))) * dac_ampl);
acc = acc + delta;
if (acc >= acc_max)
acc = acc - acc_max;
end
end
%y=y+randi([-1,1],nsamples,1)
f = 20*log10(abs(fft(y.*hanning(nsamples))));
f2 = 20*log10(abs(fft(y2.*hanning(nsamples))));
plot(f - max(f));
hold on;
plot(f2 - max(f2),'r-');
hold off;
grid on;
length(y)
length(hanning(nsamples))
length(y)
lut_size=4096;
dac_bits=12;
lut_bits=18;
dac_bias = 2^(dac_bits-1);
dac_ampl = 2^(dac_bits-1) - 1;
lut_ampl = 2^(lut_bits-1) - 1;
acc_frac=32;
n_sub_taps = 512;
lut_real=cos(linspace(0, 2*pi * lut_size/(lut_size + 1), lut_size)) .* lut_ampl;
lut = round(lut_real);
for i = 1:lut_size
ni = i+1;
if(ni > lut_size)
ni=1;
end
y0 = lut(i);
y1 = lut(ni);
slope(i) = (y1-y0)/(2^acc_frac);
end
disp('maxs');
disp(max(slope));
fs=500e6;
fout=40.079e6;
tune_res = 0.01;
acc_bits=acc_frac + log2(lut_size);
acc_max = 2^acc_bits;
acc = 0;
nsamples = 32768;
y=zeros(nsamples,1);
y2=zeros(nsamples,1);
delta = round((lut_size * fout/fs) * (2^acc_frac))
disp('ls')
lut_size
for i =1:nsamples
idx = floor(acc / (2^acc_frac)) + 1;
fb = floor(mod(acc, 2^acc_frac));
if(idx > lut_size)
idx = idx - lut_size;
end
yt=round((lut(idx) + floor(slope(idx) * fb)) / 2^(lut_bits-dac_bits));
y(i)= yt; % + randi([-1, 1],1,1);
y2(i) = round(cos(2*pi*(acc/(2^acc_frac))) * dac_ampl);
acc = acc + delta;
if (acc >= acc_max)
acc = acc - acc_max;
end
end
%y=y+randi([-1,1],nsamples,1)
f = 20*log10(abs(fft(y.*hanning(nsamples))));
f2 = 20*log10(abs(fft(y2.*hanning(nsamples))));
plot(f - max(f));
hold on;
plot(f2 - max(f2),'r-');
hold off;
grid on;
length(y)
length(hanning(nsamples))
length(y)
files = ["dds_stage.v", "pi_control.v", "dds_quad_channel.v", "dds_wb_slave.vhd", "dds_wbgen2_pkg.vhd", "max5870_serializer.vhd", "dds_core.vhd", "cic_1024x.vhd", "spi_master.vhd", "ad7980_if.vhd","timestamp_adder.vhd","dds_tx_path.vhd","dds_rx_path.vhd","timestamp_compare.vhd","pll_init.v" ]
modules = {"local":"streamers"}
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dds_wbgen2_pkg.all;
entity ad7980_if is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
trig_i : in std_logic;
d_o : out std_logic_vector(15 downto 0);
d_valid_o : out std_logic;
adc_sdo_i : in std_logic;
adc_sck_o : out std_logic;
adc_cnv_o : out std_logic;
adc_sdi_o : out std_logic
);
end ad7980_if;
architecture rtl of ad7980_if is
component spi_master
generic (
g_div_ratio_log2 : integer;
g_num_data_bits : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
start_i : in std_logic;
cpol_i : in std_logic;
data_i : in std_logic_vector(g_num_data_bits - 1 downto 0);
drdy_o : out std_logic;
ready_o : out std_logic;
data_o : out std_logic_vector(g_num_data_bits - 1 downto 0);
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic);
end component;
signal count : unsigned(7 downto 0);
signal do_acq : std_logic;
type t_state is (WAIT_TRIG, START_CNV, READBACK);
signal state : t_state;
signal d_rdy : std_logic;
begin -- rtl
U_SPI_Master : spi_master
generic map (
g_div_ratio_log2 => 3,
g_num_data_bits => 16)
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
start_i => do_acq,
cpol_i => '0',
data_i => x"0000",
data_o => d_o,
drdy_o => d_rdy,
spi_sclk_o => adc_sck_o,
spi_miso_i => adc_sdo_i);
d_valid_o <= d_rdy;
adc_sdi_o <= '1';
p_acquire : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count <= (others => '0');
adc_cnv_o <= '0';
do_acq <= '0';
state <= WAIT_TRIG;
else
case state is
when WAIT_TRIG =>
if(trig_i = '1') then
count <= (others => '0');
adc_cnv_o <= '1';
state <= START_CNV;
end if;
when START_CNV =>
count<= count +1;
if(count = 100) then
adc_cnv_o <= '0';
do_acq <= '1';
state <= READBACK;
end if;
when READBACK =>
do_acq <= '0';
if(d_rdy = '1') then
state <= WAIT_TRIG;
end if;
end case;
end if;
end if;
end process;
end rtl;
#!/bin/bash
wbgen2 -V dds_wb_slave.vhd -H record -p dds_wbgen2_pkg.vhd -K ../dds_regs.vh -s defines -C dds_regs.h -D doc/dds_regs.html dds_wb_slave.wb
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`timescale 1ns/1ps
module dds_quad_channel
(
clk_i,
rst_n_i,
acc_i,
acc_o,
dreq_i,
tune_i,
tune_load_i,
acc_load_i,
y0_o,
y1_o,
y2_o,
y3_o);
parameter integer g_acc_frac_bits = 32;
parameter integer g_output_bits = 14;
parameter integer g_lut_sample_bits= 18;
parameter integer g_lut_slope_bits = 18;
parameter integer g_interp_shift = 7;
parameter integer g_lut_size_log2 = 10;
parameter integer g_dither_taps = 32'hD0000001;
parameter integer g_dither_length = 32;
localparam c_acc_bits = g_acc_frac_bits + g_lut_size_log2 + 1;
localparam c_lut_cell_size = g_lut_sample_bits + g_lut_slope_bits;
input clk_i;
input rst_n_i;
input acc_load_i;
input tune_load_i;
input [g_acc_frac_bits + g_lut_size_log2 : 0] acc_i;
output reg [g_acc_frac_bits + g_lut_size_log2 : 0] acc_o;
input [g_acc_frac_bits + g_lut_size_log2 : 0] tune_i;
input dreq_i;
output wire [g_output_bits-1:0] y0_o, y1_o, y2_o, y3_o;
wire [g_lut_size_log2-1:0] lut_addr[0:3];
reg [c_lut_cell_size-1:0] lut_data[0:3];
reg [c_acc_bits-1:0] acc, acc_d0, acc_f[0:3], tune;
wire [g_output_bits-1:0] y[0:3];
always@(posedge clk_i)
begin
if(!rst_n_i)begin
tune <= 0;
acc <= 0;
end else begin
if(tune_load_i)
tune <= tune_i;
if(acc_load_i)
acc <= acc_i;
else if(dreq_i) begin
acc <= acc + tune;
acc_d0 <= acc;
acc_o <= acc;
acc_f[0] <= acc_d0;
acc_f[1] <= acc_d0 + (tune >> 2);
acc_f[2] <= acc_d0 + (tune >> 1);
acc_f[3] <= acc_d0 + (tune >> 2) + (tune >> 1);
end
end // else: !if(!rst_n_i)
end // always@ (posedge clk_i)
generate
genvar i;
for(i=0;i<4;i=i+1)
begin
dds_stage
#(
.g_acc_frac_bits(g_acc_frac_bits),
.g_output_bits(g_output_bits),
.g_lut_size_log2(g_lut_size_log2),
.g_dither_init_value(i*1234567)
)
U_Stage_X
(
.clk_i(clk_i),
.rst_n_i(rst_n_i),
.acc_i(acc_f[i]),
.y_o(y[i]),
.dreq_i(dreq_i),
.lut_addr_o(lut_addr[i]),
.lut_data_i(lut_data[i])
);
end // for (i=0;i<4;i++)
endgenerate
reg [g_lut_sample_bits + g_lut_slope_bits-1:0] lut01[0:2**g_lut_size_log2-1];
reg [g_lut_sample_bits + g_lut_slope_bits-1:0] lut23[0:2**g_lut_size_log2-1];
`include "lut_init.v"
initial begin
`INIT_LUT(01)
`INIT_LUT(23)
end
always@(posedge clk_i)
lut_data[0] <= lut01[lut_addr[0]];
always@(posedge clk_i)
lut_data[1] <= lut01[lut_addr[1]];
always@(posedge clk_i)