Commit 81fef64c authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

license info, uploaded missing HDL files

parent 18fa03ce
*~
*#
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WR RF Distribution Demo
Tomasz Wlostowski/CERN BE-CO-HT 2013
---------------------------------------
(c) Copyright CERN 2013
All of the code in this repository is licensed under GNU General Public License version 2 unless otherwise
stated in the file headers.
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WR RF Distribution Demo
Tomasz Wlostowski/CERN BE-CO-HT 2013
---------------------------------------
Project structure:
1) rtl - HDL sources (mixed Verilog/VHDL)
dds_stage.v single DDS generator (in our case, 125 MHz)
dds_quad_channel.v 500 MHz version consisting of 4 "single stages", phase-shifted by 90 degrees
dds_rx_path.vhd
dds_tx_path.vhd WR streamer data formatting and decoding
dds_wb_slave.vhd
dds_wb_slave.wb
dds_wbgen2_pkg.vhd Wishbone slave (wbgen2-generated)
ad7890_if.vhd SPI interface for the PLL ADC
max5870_serializer.vhd SelectIO serdes for driving the DDS DAC
pi_control.v As the name says
pll_init.v Hardware SPI master for initializing the on-board clock generator (AD9516)
pll_init_data.v
cic_1024x.vhd 1024x CIC interpolator. Matlab-generated.
timestamp_adder.vhd
timestamp_compare.vhd WR timestamp arithmetic cores
2) software - a C test program
3) top/spec - top level for the SPEC (connects the WR core and Gennum PCI-Express core)
4) syn/spec - synthesis directory
5) sim - simulation models (symlink to wr-cores/sim)
6) scripts - ucfgen script for pin assignment
Synthesizing:
cd syn/spec
hdlmake --ise-proj
open project in ISE, click Synthesize...
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files = ["dds_stage.v", "pi_control.v", "dds_quad_channel.v", "mdsp.v", "dds_wb_slave.vhd", "dds_wbgen2_pkg.vhd", "max5870_serializer.vhd", "dds_core.vhd", "cic_1024x.vhd", "spi_master.vhd", "ad7980_if.vhd","timestamp_adder.vhd","dds_tx_path.vhd","dds_rx_path.vhd","timestamp_compare.vhd","pll_init.v" ] files = ["dds_stage.v", "pi_control.v", "dds_quad_channel.v", "dds_wb_slave.vhd", "dds_wbgen2_pkg.vhd", "max5870_serializer.vhd", "dds_core.vhd", "cic_1024x.vhd", "spi_master.vhd", "ad7980_if.vhd","timestamp_adder.vhd","dds_tx_path.vhd","dds_rx_path.vhd","timestamp_compare.vhd","pll_init.v" ]
modules = {"local":"streamers"} modules = {"local":"streamers"}
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : dds_wb_slave.vhd -- File : dds_wb_slave.vhd
-- Author : auto-generated by wbgen2 from dds_wb_slave.wb -- Author : auto-generated by wbgen2 from dds_wb_slave.wb
-- Created : Mon May 13 01:42:01 2013 -- Created : Thu May 16 10:47:05 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dds_wb_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dds_wb_slave.wb
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : dds_wbgen2_pkg.vhd -- File : dds_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from dds_wb_slave.wb -- Author : auto-generated by wbgen2 from dds_wb_slave.wb
-- Created : Mon May 13 01:42:01 2013 -- Created : Thu May 16 10:47:05 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dds_wb_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dds_wb_slave.wb
......
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