Commit ca9b19b8 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

adding files worth saving...

parent 5284284f
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function [y,acc]=dds(inc,lut,lsize,frac)
disp('x')
fs = 125e6; % Input sampling frequency.
fpass = 0.02e6; % Frequency band of interest.
m = 1024; % Decimation factor.
hcic = design(fdesign.interpolator(m,'cic',1,fpass,90,fs));
hcic
gain(hcic, 6)
g = 1/ (2^70)
hd = cascade(dfilt.scalar(g),hcic);
comp = fdesign.ciccomp(hcic.differentialdelay, ...
hcic.numberofsections,fpass,fpass * 1.6,.1,90,fs/m)
hd(2) = design(comp,'fir')
fvtool(hd(1),hd(2),...
cascade(hd(2),hd(1)),'Fs',[fs fs/m fs])
%fvtool(hd)
\ No newline at end of file
f=10e6;
fs=500e6;
tune = (2^42) * (f/fs) * 8;
f2 = fs * (tune+1) / (2^42 * 8);
span = abs(f - f2) * 65536
y=csvread('/tmp/dds-hw.dat');
nsamples=length(y)
%y=y+randi([-1,1],nsamples,1)
f = 20*log10(abs(fft(y.*hanning(nsamples))));
hold on;
plot(f - max(f),'r-');
grid on;
lut_size=32768;
dac_bits=12;
dac_bias = 2^(dac_bits-1);
dac_ampl = 2^(dac_bits-1) - 1;
acc_frac=32;
n_sub_taps = 512;
lut_real=cos(linspace(0, 2*pi * lut_size/(lut_size + 1), lut_size)) .* dac_ampl
lut = round(lut_real);
for i = 1:lut_size
ni = i+1;
if(ni > lut_size)
ni=1;
end
x0 = 2 * pi * (i-1) / lut_size;
x1 = 2 * pi * i / lut_size;
sub = cos(linspace(x0, x1, n_sub_taps)).*dac_ampl;
for j=1+1:n_sub_taps-1
if(abs(sub(j) - sub(1)) >= abs(sub(n_sub_taps)-sub(j)))
break
end
end
offs(i)= j / n_sub_taps * (2^acc_frac);
end
fs=500e6;
fout=11.1111e6;
tune_res = 0.01;
acc_bits=acc_frac + log2(lut_size);
acc_max = 2^acc_bits;
acc = 0;
nsamples = 32768;
y=zeros(nsamples,1);
y2=zeros(nsamples,1);
delta = round((lut_size * fout/fs) * (2^acc_frac))
for i =1:nsamples
idx = floor(acc / (2^acc_frac)) + 1;
fb = floor(mod(acc, 2^acc_frac));
if(idx > lut_size)
idx = idx - lut_size;
end
if(fb < offs(idx))
yt=lut(idx);
elseif(idx == lut_size)
yt=lut(1);
else
yt=lut(idx+1);
end
y(i)= yt + randi([0, 1],1,1);
y2(i) = round(cos(2*pi*(acc/(2^acc_frac))) * dac_ampl);
acc = acc + delta;
if (acc >= acc_max)
acc = acc - acc_max;
end
end
%y=y+randi([-1,1],nsamples,1)
f = 20*log10(abs(fft(y.*hanning(nsamples))));
f2 = 20*log10(abs(fft(y2.*hanning(nsamples))));
plot(f - max(f));
hold on;
plot(f2 - max(f2),'r-');
hold off;
grid on;
length(y)
length(hanning(nsamples))
length(y)
lut_size=4096;
dac_bits=12;
lut_bits=18;
dac_bias = 2^(dac_bits-1);
dac_ampl = 2^(dac_bits-1) - 1;
lut_ampl = 2^(lut_bits-1) - 1;
acc_frac=32;
n_sub_taps = 512;
lut_real=cos(linspace(0, 2*pi * lut_size/(lut_size + 1), lut_size)) .* lut_ampl;
lut = round(lut_real);
for i = 1:lut_size
ni = i+1;
if(ni > lut_size)
ni=1;
end
y0 = lut(i);
y1 = lut(ni);
slope(i) = (y1-y0)/(2^acc_frac);
end
disp('maxs');
disp(max(slope));
fs=500e6;
fout=40.079e6;
tune_res = 0.01;
acc_bits=acc_frac + log2(lut_size);
acc_max = 2^acc_bits;
acc = 0;
nsamples = 32768;
y=zeros(nsamples,1);
y2=zeros(nsamples,1);
delta = round((lut_size * fout/fs) * (2^acc_frac))
disp('ls')
lut_size
for i =1:nsamples
idx = floor(acc / (2^acc_frac)) + 1;
fb = floor(mod(acc, 2^acc_frac));
if(idx > lut_size)
idx = idx - lut_size;
end
yt=round((lut(idx) + floor(slope(idx) * fb)) / 2^(lut_bits-dac_bits));
y(i)= yt; % + randi([-1, 1],1,1);
y2(i) = round(cos(2*pi*(acc/(2^acc_frac))) * dac_ampl);
acc = acc + delta;
if (acc >= acc_max)
acc = acc - acc_max;
end
end
%y=y+randi([-1,1],nsamples,1)
f = 20*log10(abs(fft(y.*hanning(nsamples))));
f2 = 20*log10(abs(fft(y2.*hanning(nsamples))));
plot(f - max(f));
hold on;
plot(f2 - max(f2),'r-');
hold off;
grid on;
length(y)
length(hanning(nsamples))
length(y)
#
# Mezzanine top level pin assignment file:
# syntax: pin FMC_pin_name Core_Pin_name IO_Standard
# % is replaced with FMC number if the carrier supports more than 1 mezzanine
#
mezzanine fmc-dds-600m
pin la_n2 dds%_dac_n_o[11] lvds_25
pin la_p2 dds%_dac_p_o[11] lvds_25
pin la_n4 dds%_dac_n_o[9] lvds_25
pin la_p4 dds%_dac_p_o[9] lvds_25
pin la_n7 dds%_dac_n_o[6] lvds_25
pin la_p7 dds%_dac_p_o[6] lvds_25
pin la_n11 dds%_dac_n_o[3] lvds_25
pin la_p11 dds%_dac_p_o[3] lvds_25
pin la_n15 dds%_dac_n_o[0] lvds_25
pin la_p15 dds%_dac_p_o[0] lvds_25
pin la_p19 dds%_pll_vcxo_status_i lvcmos25
pin la_n19 dds%_pll_sys_ld_i lvcmos25
pin la_p21 dds%_pll_sdo_i lvcmos25
pin la_n21 dds%_pll_sys_reset_n_o lvcmos25
pin la_p24 dds%_adc_sdo_i lvcmos25
pin la_n24 dds%_adc_sck_o lvcmos25
pin la_p28 dds%_wr_dac_sclk_o lvcmos25
pin la_n28 dds%_delay_d_o[1] lvcmos25
pin la_p30 dds%_delay_d_o[3] lvcmos25
pin la_n30 dds%_delay_d_o[5] lvcmos25
pin la_p32 dds%_delay_d_o[7] lvcmos25
pin la_n32 dds%_delay_d_o[9] lvcmos25
#clk0out = DDS raw output
#clk1out = system pll output
#clk2out = vcxo pll output
pin clk1m2c_n dds%_vcxo_pll_clk_n_i lvds_25
pin clk1m2c_p dds%_vcxo_pll_clk_p_i lvds_25
pin la_n0 dds%_wr_ref_clk_n_i lvds_25
pin la_p0 dds%_wr_ref_clk_p_i lvds_25
pin la_p3 dds%_dac_p_o[10] lvds_25
pin la_n3 dds%_dac_n_o[10] lvds_25
pin la_p8 dds%_dac_p_o[7] lvds_25
pin la_n8 dds%_dac_n_o[7] lvds_25
pin la_p12 dds%_dac_p_o[4] lvds_25
pin la_n12 dds%_dac_n_o[4] lvds_25
pin la_p16 dds%_dac_p_o[1] lvds_25
pin la_n16 dds%_dac_n_o[1] lvds_25
pin la_p20 dds%_wr_dac_din_o lvcmos25
pin la_n20 dds%_id_temp_b lvcmos25
pin la_p22 dds%_pll_sclk_o lvcmos25
pin la_n22 dds%_pll_sdio_b lvcmos25
pin la_p25 dds%_adc_cnv_o lvcmos25
pin la_n25 dds%_adc_sdi_o lvcmos25
pin la_p29 dds%_wr_dac_sync_n_o lvcmos25
pin la_n29 dds%_delay_d_o[0] lvcmos25
pin la_p31 dds%_delay_d_o[2] lvcmos25
pin la_n31 dds%_delay_d_o[4] lvcmos25
pin la_p33 dds%_delay_d_o[6] lvcmos25
pin la_n33 dds%_delay_d_o[8] lvcmos25
pin la_p1 dds%_dac_p_o[13] lvds_25
pin la_n1 dds%_dac_n_o[13] lvds_25
pin la_p5 dds%_dac_p_o[8] lvds_25
pin la_n5 dds%_dac_n_o[8] lvds_25
pin la_p9 dds%_dac_p_o[5] lvds_25
pin la_n9 dds%_dac_n_o[5] lvds_25
pin la_p13 dds%_dac_p_o[2] lvds_25
pin la_n13 dds%_dac_n_o[2] lvds_25
pin la_p17 dds%_pll_vcxo_csb_o lvcmos25
pin la_n17 dds%_delay_fb_i lvcmos25
pin la_p23 dds%_pd_lockdet_i lvcmos25
pin la_n23 dds%_pd_clk_o lvcmos25
pin la_p26 dds%_pll_sys_cs_n_o lvcmos25
pin la_n26 dds%_delay_len_o lvcmos25
pin la_p6 dds%_dac_p_o[12] lvds_25
pin la_n6 dds%_dac_n_o[12] lvds_25
pin la_n10 dds%_delay_pulse_o lvcmos25
pin la_p14 dds%_pll_sys_sync_n_o lvcmos25
pin la_n14 dds%_pll_vcxo_syncb_o lvcmos25
pin la_p18 dds_trig_p_i lvds_25
pin la_n18 dds_trig_n_i lvds_25
pin la_p27 dds_pd_data_b lvcmos25
pin la_n27 dds_pd_le_o lvcmos25
#eof
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