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Distributed Direct Digital Synthesis over White Rabbit D3S
Commit cf566000 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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software/gw: initial working commit

parent 2e8c4217
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Showing with 274 additions and 80 deletions
software/Makefile
View file @ cf566000
OBJS = ad9516.o speclib/speclib.o filters.o OBJS = rf-lib.o rf-test.o speclib/speclib.o filters.o
CFLAGS = -I../include -g -Imini_bone -Ispeclib -I. CFLAGS = -I../include -g -Imini_bone -Ispeclib -I.
......
software/load.sh
View file @ cf566000
#!/bin/bash #!/bin/bash
insmod /home/user/pts/test/fmcdelay1ns4cha/lib/spec/kernel/spec.ko insmod /home/user/pts/test/fmcdelay1ns4cha/lib/spec/kernel/spec.ko
spec-fwloader /home/user/rf18.bin spec-fwloader -b 1 /home/user/rf55-wr.bin
spec-fwloader -b 2 /home/user/rf55-wr.bin
sleep 1
./rf-test
#spec-fwloader /home/user/rf45-wr.bin
software/regs/dds_regs.h
View file @ cf566000
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : dds_regs.h * File : dds_regs.h
* Author : auto-generated by wbgen2 from dds_wb_slave.wb * Author : auto-generated by wbgen2 from dds_wb_slave.wb
* Created : Fri May 10 01:11:43 2013 * Created : Mon May 13 01:42:01 2013
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dds_wb_slave.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dds_wb_slave.wb
...@@ -45,11 +45,17 @@ ...@@ -45,11 +45,17 @@
/* definitions for field: ADC Bitbanged Access Enable in reg: Control Register */ /* definitions for field: ADC Bitbanged Access Enable in reg: Control Register */
#define DDS_CR_ADC_BB_ENABLE WBGEN2_GEN_MASK(3, 1) #define DDS_CR_ADC_BB_ENABLE WBGEN2_GEN_MASK(3, 1)
/* definitions for field: WR Link status in reg: Control Register */
#define DDS_CR_WR_LINK WBGEN2_GEN_MASK(4, 1)
/* definitions for field: WR Time status in reg: Control Register */
#define DDS_CR_WR_TIME WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Broadcast Clock ID in reg: Control Register */ /* definitions for field: Broadcast Clock ID in reg: Control Register */
#define DDS_CR_CLK_ID_MASK WBGEN2_GEN_MASK(4, 16) #define DDS_CR_CLK_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define DDS_CR_CLK_ID_SHIFT 4 #define DDS_CR_CLK_ID_SHIFT 16
#define DDS_CR_CLK_ID_W(value) WBGEN2_GEN_WRITE(value, 4, 16) #define DDS_CR_CLK_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define DDS_CR_CLK_ID_R(reg) WBGEN2_GEN_READ(reg, 4, 16) #define DDS_CR_CLK_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: GPIO register */ /* definitions for register: GPIO register */
...@@ -146,6 +152,70 @@ ...@@ -146,6 +152,70 @@
#define DDS_PIR_KI_W(value) WBGEN2_GEN_WRITE(value, 16, 16) #define DDS_PIR_KI_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define DDS_PIR_KI_R(reg) WBGEN2_GEN_READ(reg, 16, 16) #define DDS_PIR_KI_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Delay Adjust Register */
/* definitions for field: Delay in reg: Delay Adjust Register */
#define DDS_DLYR_DELAY_MASK WBGEN2_GEN_MASK(0, 16)
#define DDS_DLYR_DELAY_SHIFT 0
#define DDS_DLYR_DELAY_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define DDS_DLYR_DELAY_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Phase Shift Adjust Register */
/* definitions for field: PHASE in reg: Phase Shift Adjust Register */
#define DDS_PHASER_PHASE_MASK WBGEN2_GEN_MASK(0, 16)
#define DDS_PHASER_PHASE_SHIFT 0
#define DDS_PHASER_PHASE_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define DDS_PHASER_PHASE_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: MAC Lo reg */
/* definitions for field: MACL in reg: MAC Lo reg */
#define DDS_MACL_MACL_MASK WBGEN2_GEN_MASK(0, 32)
#define DDS_MACL_MACL_SHIFT 0
#define DDS_MACL_MACL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define DDS_MACL_MACL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: MAC Hi reg */
/* definitions for field: MACH in reg: MAC Hi reg */
#define DDS_MACH_MACH_MASK WBGEN2_GEN_MASK(0, 16)
#define DDS_MACH_MACH_SHIFT 0
#define DDS_MACH_MACH_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define DDS_MACH_MACH_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Hit Count Reg */
/* definitions for field: HIT_CNT in reg: Hit Count Reg */
#define DDS_HIT_CNT_HIT_CNT_MASK WBGEN2_GEN_MASK(0, 24)
#define DDS_HIT_CNT_HIT_CNT_SHIFT 0
#define DDS_HIT_CNT_HIT_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define DDS_HIT_CNT_HIT_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for register: Miss Count Reg */
/* definitions for field: MISS_CNT in reg: Miss Count Reg */
#define DDS_MISS_CNT_MISS_CNT_MASK WBGEN2_GEN_MASK(0, 24)
#define DDS_MISS_CNT_MISS_CNT_SHIFT 0
#define DDS_MISS_CNT_MISS_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define DDS_MISS_CNT_MISS_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for register: RX Count Reg */
/* definitions for field: RX_CNT in reg: RX Count Reg */
#define DDS_RX_CNT_RX_CNT_MASK WBGEN2_GEN_MASK(0, 24)
#define DDS_RX_CNT_RX_CNT_SHIFT 0
#define DDS_RX_CNT_RX_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define DDS_RX_CNT_RX_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for register: TX Count Reg */
/* definitions for field: TX_CNT in reg: TX Count Reg */
#define DDS_TX_CNT_TX_CNT_MASK WBGEN2_GEN_MASK(0, 24)
#define DDS_TX_CNT_TX_CNT_SHIFT 0
#define DDS_TX_CNT_TX_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define DDS_TX_CNT_TX_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for register: FIFO 'PD ADC Test FIFO (test mode)' data output register 0 */ /* definitions for register: FIFO 'PD ADC Test FIFO (test mode)' data output register 0 */
/* definitions for field: ADC data in reg: FIFO 'PD ADC Test FIFO (test mode)' data output register 0 */ /* definitions for field: ADC data in reg: FIFO 'PD ADC Test FIFO (test mode)' data output register 0 */
...@@ -193,12 +263,28 @@ ...@@ -193,12 +263,28 @@
#define DDS_REG_I2CR 0x00000018 #define DDS_REG_I2CR 0x00000018
/* [0x1c]: REG PI register */ /* [0x1c]: REG PI register */
#define DDS_REG_PIR 0x0000001c #define DDS_REG_PIR 0x0000001c
/* [0x20]: REG FIFO 'PD ADC Test FIFO (test mode)' data output register 0 */ /* [0x20]: REG Delay Adjust Register */
#define DDS_REG_PD_FIFO_R0 0x00000020 #define DDS_REG_DLYR 0x00000020
/* [0x24]: REG FIFO 'PD ADC Test FIFO (test mode)' control/status register */ /* [0x24]: REG Phase Shift Adjust Register */
#define DDS_REG_PD_FIFO_CSR 0x00000024 #define DDS_REG_PHASER 0x00000024
/* [0x28]: REG FIFO 'DDS Tuning FIFO (test mode)' data input register 0 */ /* [0x28]: REG MAC Lo reg */
#define DDS_REG_TUNE_FIFO_R0 0x00000028 #define DDS_REG_MACL 0x00000028
/* [0x2c]: REG FIFO 'DDS Tuning FIFO (test mode)' control/status register */ /* [0x2c]: REG MAC Hi reg */
#define DDS_REG_TUNE_FIFO_CSR 0x0000002c #define DDS_REG_MACH 0x0000002c
/* [0x30]: REG Hit Count Reg */
#define DDS_REG_HIT_CNT 0x00000030
/* [0x34]: REG Miss Count Reg */
#define DDS_REG_MISS_CNT 0x00000034
/* [0x38]: REG RX Count Reg */
#define DDS_REG_RX_CNT 0x00000038
/* [0x3c]: REG TX Count Reg */
#define DDS_REG_TX_CNT 0x0000003c
/* [0x40]: REG FIFO 'PD ADC Test FIFO (test mode)' data output register 0 */
#define DDS_REG_PD_FIFO_R0 0x00000040
/* [0x44]: REG FIFO 'PD ADC Test FIFO (test mode)' control/status register */
#define DDS_REG_PD_FIFO_CSR 0x00000044
/* [0x48]: REG FIFO 'DDS Tuning FIFO (test mode)' data input register 0 */
#define DDS_REG_TUNE_FIFO_R0 0x00000048
/* [0x4c]: REG FIFO 'DDS Tuning FIFO (test mode)' control/status register */
#define DDS_REG_TUNE_FIFO_CSR 0x0000004c
#endif #endif
software/ad9516.c → software/rf-lib.c
View file @ cf566000
...@@ -4,12 +4,10 @@ ...@@ -4,12 +4,10 @@
#include <sys/time.h> #include <sys/time.h>
#include <math.h> #include <math.h>
#include "speclib.h" #include "speclib.h"
#include "regs/dds_regs.h" #include "regs/dds_regs.h"
#include "filters.h" #include "filters.h"
#include "rf-lib.h"
void loader_low_level() {}; void loader_low_level() {};
...@@ -29,6 +27,11 @@ static inline uint32_t rf_readl(struct wr_rf_device *dev, uint32_t addr) ...@@ -29,6 +27,11 @@ static inline uint32_t rf_readl(struct wr_rf_device *dev, uint32_t addr)
return spec_readl (dev->card, addr + dev->base); return spec_readl (dev->card, addr + dev->base);
} }
int gp_pos = 0;
int pll_init = 0;
int gp_seq = 0x7;
static void gpio_set(struct wr_rf_device *dev, uint32_t pin, int value) static void gpio_set(struct wr_rf_device *dev, uint32_t pin, int value)
{ {
uint32_t g = rf_readl(dev, DDS_REG_GPIOR); uint32_t g = rf_readl(dev, DDS_REG_GPIOR);
...@@ -36,6 +39,32 @@ static void gpio_set(struct wr_rf_device *dev, uint32_t pin, int value) ...@@ -36,6 +39,32 @@ static void gpio_set(struct wr_rf_device *dev, uint32_t pin, int value)
rf_writel(dev, g | pin, DDS_REG_GPIOR); rf_writel(dev, g | pin, DDS_REG_GPIOR);
else else
rf_writel(dev, g & ~pin, DDS_REG_GPIOR); rf_writel(dev, g & ~pin, DDS_REG_GPIOR);
if(pll_init)
{
int bit;
if(pin == DDS_GPIOR_PLL_SCLK)
bit = 1;
else if(pin == DDS_GPIOR_PLL_SDIO)
bit = 2;
else if(pin == DDS_GPIOR_PLL_SYS_CS_N)
bit = 0;
int gp_seq_prev = gp_seq;
if(value)
gp_seq |= (1<<bit);
else
gp_seq &= ~(1<<bit);
if(gp_seq_prev!=gp_seq)
printf("pll_init_seq[%d] = 3'h%x;\n", gp_pos++, gp_seq);
}
} }
static int gpio_get(struct wr_rf_device *dev, uint32_t pin) static int gpio_get(struct wr_rf_device *dev, uint32_t pin)
...@@ -132,6 +161,8 @@ static int ad9516_init(struct wr_rf_device *dev) ...@@ -132,6 +161,8 @@ static int ad9516_init(struct wr_rf_device *dev)
gpio_set(dev, DDS_GPIOR_PLL_SYS_RESET_N, 1); gpio_set(dev, DDS_GPIOR_PLL_SYS_RESET_N, 1);
udelay(1000); udelay(1000);
pll_init = 1;
ad951x_write_reg(dev, DDS_GPIOR_PLL_SYS_CS_N, 0, 0x99); ad951x_write_reg(dev, DDS_GPIOR_PLL_SYS_CS_N, 0, 0x99);
ad951x_write_reg(dev, DDS_GPIOR_PLL_SYS_CS_N, 0x232, 1); ad951x_write_reg(dev, DDS_GPIOR_PLL_SYS_CS_N, 0x232, 1);
...@@ -160,6 +191,7 @@ static int ad9516_init(struct wr_rf_device *dev) ...@@ -160,6 +191,7 @@ static int ad9516_init(struct wr_rf_device *dev)
ad951x_write_reg(dev, DDS_GPIOR_PLL_SYS_CS_N, 0x232, 0); ad951x_write_reg(dev, DDS_GPIOR_PLL_SYS_CS_N, 0x232, 0);
ad951x_write_reg(dev, DDS_GPIOR_PLL_SYS_CS_N, 0x232, 1); ad951x_write_reg(dev, DDS_GPIOR_PLL_SYS_CS_N, 0x232, 1);
pll_init = 0;
/* Wait until the PLL has locked */ /* Wait until the PLL has locked */
uint64_t start_tics = get_tics(); uint64_t start_tics = get_tics();
uint64_t lock_timeout = 1000000ULL; uint64_t lock_timeout = 1000000ULL;
...@@ -182,6 +214,7 @@ static int ad9516_init(struct wr_rf_device *dev) ...@@ -182,6 +214,7 @@ static int ad9516_init(struct wr_rf_device *dev)
ad951x_write_reg(dev, DDS_GPIOR_PLL_SYS_CS_N, 0x230, 0); ad951x_write_reg(dev, DDS_GPIOR_PLL_SYS_CS_N, 0x230, 0);
ad951x_write_reg(dev, DDS_GPIOR_PLL_SYS_CS_N, 0x232, 1); ad951x_write_reg(dev, DDS_GPIOR_PLL_SYS_CS_N, 0x232, 1);
dbg("%s: AD9516 locked.\n", __FUNCTION__); dbg("%s: AD9516 locked.\n", __FUNCTION__);
...@@ -275,23 +308,6 @@ void write_tune(struct wr_rf_device *dev, int tune) ...@@ -275,23 +308,6 @@ void write_tune(struct wr_rf_device *dev, int tune)
rf_writel(dev, tune, DDS_REG_TUNE_FIFO_R0); rf_writel(dev, tune, DDS_REG_TUNE_FIFO_R0);
} }
void modulation_test(struct wr_rf_device *dev)
{
rf_writel(dev, 80, DDS_REG_GAIN); /* tuning gain = 0 dB */
double f_test = 1e3;
double f_samp = 125e6/1024.0;
int n;
for(;;)
{
double x = 32767.0 * cos(2.0*M_PI*(double)n * f_test / f_samp);
// printf("S %d\n", (int)x);
write_tune(dev, (int) x);
n++;
}
}
void boot_mdsp(struct wr_rf_device *dev, const char *mc_file) void boot_mdsp(struct wr_rf_device *dev, const char *mc_file)
{ {
...@@ -321,76 +337,82 @@ void boot_mdsp(struct wr_rf_device *dev, const char *mc_file) ...@@ -321,76 +337,82 @@ void boot_mdsp(struct wr_rf_device *dev, const char *mc_file)
} }
void test_pid(struct wr_rf_device *dev) struct wr_rf_device *rf_create(void *handle, uint32_t base_addr)
{ {
struct fir_filter *flt_comp = fir_load("fir_compensator.dat"); struct wr_rf_device *dev;
struct iir_1st *flt_loop = lowpass_init(1000.0/(125e6/1024.0)); dev = malloc(sizeof(struct wr_rf_device));
double kp = 0.002;
double ki = 0.000001;
int i;
dev->card = handle;
dev->base = base_addr;
return dev;
}
rf_writel(dev, 2000, DDS_REG_GAIN); /* tuning gain = 0 dB */ int rf_init(struct wr_rf_device *dev, double freq, int mode, int bcid)
{
dbg("SDB signature = 0x%x\n", spec_readl(dev->card, 0));
rf_writel(dev, DDS_CR_TEST, DDS_REG_CR); rf_writel(dev, 0, DDS_REG_CR);
// ad9516_init(dev);
reset_core(dev);
int s; spec_load_lm32(dev->card, "/home/user/wrc-test.bin", 0xc0000);
double integ = 0.0; sleep(1);
set_center_freq(dev, freq, 500e6);
adf4002_configure(dev, 2, 2, 4);
int ki_q = (int) ((1024.0 * ki) * (double)(1<<16)); rf_writel(dev, 3000, DDS_REG_GAIN);
int kp_q = (int) ((1.0 * kp) * (double)(1<<16));
// printf("ki_q %d kp_q %d\n", ki_q, kp_q); //08:00:30:61:86:89
rf_writel(dev, 0x0800, DDS_REG_MACH);
rf_writel(dev, 0x30618689, DDS_REG_MACL);
#define ACC_BITS 30 printf("MAC:%04x%08x\n", rf_readl(dev, DDS_REG_MACH), rf_readl(dev, DDS_REG_MACL));
int64_t acc = 0; if(mode == RF_MODE_MASTER)
for(i=0;i<100000;i++)
read_adc(dev, &s , 1);
for(;;)
{ {
int s,err;
read_adc(dev, &s , 1);
// s = lowpass_process(flt_loop, s); double kp = 0.05;
double ki = 0.0000005;
s-=32768; int ki_q = (int) ((1024.0 * ki) * (double)(1<<16));
err = s; int kp_q = (int) ((1.0 * kp) * (double)(1<<16));
// s*=-1;
// integ += (double)err;
acc += err >> 10; // dbg("kp_q %d ki_q %d\n", kp_q, ki_q);
acc &= (1<<ACC_BITS) - 1; rf_writel(dev, DDS_PIR_KI_W(ki_q) | DDS_PIR_KP_W(kp_q), DDS_REG_PIR);
if(acc & (1<<(ACC_BITS-1))) rf_writel(dev, DDS_CR_MASTER | DDS_CR_CLK_ID_W(bcid), DDS_REG_CR) ;
acc |= ~((1<<ACC_BITS)-1);
s = ((int64_t)(acc) * (int64_t) ki_q + (int64_t)err * (int64_t)kp_q) >> 16; // dbg("master mode %d\n", rf_readl(dev, DDS_REG_CR) & DDS_CR_MASTER?1:0);
return 0;
} else if (mode == RF_MODE_SLAVE) {
rf_writel(dev, DDS_RSTR_SW_RST, DDS_REG_RSTR);
udelay(10);
rf_writel(dev, 0, DDS_REG_RSTR);
rf_writel(dev, 10000, DDS_REG_DLYR);
rf_writel(dev, DDS_CR_CLK_ID_W(bcid) | DDS_CR_SLAVE, DDS_REG_CR) ;
// s = (int) (integ * ki + (double) err * kp); }
// s = fir_process(flt_comp, s); return 0;
}
// integ *= 0.999999;
// printf("%d\n", s);
if(s < -32000) s = -32000; int rf_get_counters(struct wr_rf_device *dev, struct rf_counters *cnt)
else if (s > 32000) s = 32000; {
// s = 30000; cnt->hit = rf_readl(dev, DDS_REG_HIT_CNT) & 0xffffff;
write_tune(dev, s); cnt->miss = rf_readl(dev, DDS_REG_MISS_CNT) & 0xffffff;
// printf("%d %d\n", s, err); cnt->rx = rf_readl(dev, DDS_REG_RX_CNT) & 0xffffff;
cnt->tx = rf_readl(dev, DDS_REG_TX_CNT) & 0xffffff;
return 0;
}
} #if 0
}
int main(int argc, char *argv[]) int main(int argc, char *argv[])
{ {
...@@ -498,3 +520,5 @@ int main(int argc, char *argv[]) ...@@ -498,3 +520,5 @@ int main(int argc, char *argv[])
return 0; return 0;
} }
#endif
\ No newline at end of file
software/rf-lib.h 0 → 100644
View file @ cf566000
#ifndef __RF_LIB_H
#define __RF_LIB_H
#include <stdint.h>
#define RF_MODE_MASTER 0
#define RF_MODE_SLAVE 1
#define RF_MODE_TEST 2
#define RF_WR_OFFLINE 0
#define RF_WR_SYNCING 1
#define RF_WR_READY 2
struct rf_counters {
int miss, hit, rx,tx;
};
struct wr_rf_device;
struct wr_rf_device *rf_create(void *handle, uint32_t base_addr);
int rf_init(struct wr_rf_device *dev, double freq, int mode, int bcid);
int rf_search_streams(struct wr_rf_device *dev, int *bcids, int *max_bcids);
int rf_poll_histogram(struct wr_rf_device *dev, int *bcids, int *max_bcids);
int rf_init_histogram(struct wr_rf_device *dev, double bias, double scale);
int rf_read_histogram(struct wr_rf_device *dev, int *hist, int *size);
int rf_get_wr_state(struct wr_rf_device *dev);
int rf_get_counters(struct wr_rf_device *dev, struct rf_counters *);
#endif
software/rf-test.c 0 → 100644
View file @ cf566000
#include <stdio.h>
#include "rf-lib.h"
#include "speclib.h"
int main(int argc, char *argv[])
{
struct wr_rf_device *dev_master, *dev_slave;
void *card_master, *card_slave;
card_master = spec_open(1, -1);
card_slave = spec_open(2, -1);
// dev.base = 0x80000;
if(!card_master || !card_slave)
{
dbg("SPEC open failed\n");
return -1;
}
dev_master = rf_create(card_master, 0x80000);
dev_slave = rf_create(card_slave, 0x80000);
printf("SDB ID A = %x\n", spec_readl(card_master, 0));
printf("SDB ID B = %x\n", spec_readl(card_slave, 0));
rf_init(dev_slave, 10e6, RF_MODE_SLAVE, 11);
sleep(10);
rf_init(dev_master, 10e6, RF_MODE_MASTER, 11);
struct rf_counters cnt_m, cnt_s;
for(;;)
{
rf_get_counters(dev_master, &cnt_m);
rf_get_counters(dev_slave, &cnt_s);
printf("Master cnt: tx %d rx %d hits %d misses %d\n", cnt_m.tx, cnt_m.rx, cnt_m.hit, cnt_m.miss);
printf("Slave cnt: tx %d rx %d hits %d misses %d\n", cnt_s.tx, cnt_s.rx, cnt_s.hit, cnt_s.miss);
sleep(1);
}
spec_close(card_master);
spec_close(card_slave);
return 0;
}
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