RF distribution demo
Specification
- Default frequency: 40.079 MHz (LHC bunch clock). Can be reprogrammed to 1-70 MHz.
- Single master node sending to single slave node.
- Hardware: a DDS mezzanine hosted on a SPEC FMC carrier and a White Rabbit switch.
System diagram
Clocks:*
- Everything except the DAC is clocked with 125 MHz WR clock, coming from the FMC (not the SPEC local oscillator).
- The DAC is driven with a 500 MHz clock, in-phase with the 125 MHz WR reference.
DDS core:*
- Lookup table-based DDS with configurable resolution & tuning word width.
- LUT interpolation and dithering - no spurs in the output (~90 dB SFDR).
- Output sample rate: 500 MSPS, tuning words are delivered
synchronously to WR clock and interpolated
4 times.
DDS PLL:*
- Locks the phase of the DDS numerically controlled oscillator to the phase of the RF input signal.
- Analog phase detector (ADF4002) followed by a simple antialiasing filter and a 16-bit 1MSPS ADC
- The true loop filter is digital (a simple PI controller for the moment).
- The loop filter works at 1/1024 of the WR clock rate (~122 kHz) to reduce the amount of data samples to send. Interpolation is done with a CIC (cascaded integrator-comb) filter.
- Corrections wrs the baseline frequency are added to the DDS.
Data streaming:*
- Correction values are timestamped and sent over Ethernet (through the streamers from the WR tutorial).
- Received corrections are "executed" after a fixed delay (set to 20 us for the moment).
- Point-to-point only for the moment, MAC addresses are fixed.
Useful documentation:
Tom's PH-ESE Demo presentation - contains also preliminary measurements