Technical Documentation - 2017-02-03 14:37:24.601501
The scope of the following document is to evaluate the phase noise and
stability floor of the Digital Dual Mixer Time Difference (DDMTD) phase
detector in the WR PLL architecture. The measurement has been done on
the WR Switch (Virtex-6) The effect of the DDMTD common clock noise on
the phase noise floor is modelled mathematically and verified
experimentally.
The experimental results show a phase noise floor of -108 dBc/Hz (10MHz
carrier) combined with a flicker noise (1/f noise) of -100dBc/Hz at 1Hz
(flicker corner frequency at 5Hz). The flicker noise has been traced to
the LVDS input clock buffer of the FPGA.
The DDMTD is able to provide 4 ps single-shot precision (1 σ) with a
measurement rate up to 3.8 kHz
The stability of the DDMTD has been characterized with Modified Allan
Deviation (MDEV) and Allan Deviation (ADEV). The results are:
- MDEV 4E-13 at Tau=1s for Equivalent Noise BW of 50Hz,
- ADEV, is depending on the Equivalent Noise Bandwidth,
- 4E-13 at Tau=1s for Equivalent Noise BW of 0.5Hz and
- 1E-12 at Tau=1s for Equivalent Noise BW of 50Hz